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/linux/Documentation/devicetree/bindings/clock/st/
H A Dst,clkgen-pll.txt7 [2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
12 "st,clkgen-pll0"
13 "st,clkgen-pll0-a0"
14 "st,clkgen-pll0-c0"
15 "st,clkgen-pll1"
16 "st,clkgen-pll1-c0"
17 "st,stih407-clkgen-plla9"
18 "st,stih418-clkgen-plla9"
29 compatible = "st,clkgen-c32";
34 compatible = "st,stih407-clkgen
[all...]
H A Dst,clkgen.txt34 [3] Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
35 [4] Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
46 compatible = "st,clkgen-c32";
51 compatible = "st,clkgen-pll0";
H A Dst,clkgen-mux.txt13 "st,stih407-clkgen-a9-mux"
25 compatible = "st,stih407-clkgen-a9-mux";
/linux/arch/riscv/boot/dts/starfive/
H A Djh7100.dtsi188 clocks = <&clkgen JH7100_CLK_SDIO0_AHB>,
189 <&clkgen JH7100_CLK_SDIO0_CCLKINT_INV>;
201 clocks = <&clkgen JH7100_CLK_SDIO1_AHB>,
202 <&clkgen JH7100_CLK_SDIO1_CCLKINT_INV>;
214 clocks = <&clkgen JH7100_CLK_GMAC_ROOT_DIV>,
215 <&clkgen JH7100_CLK_GMAC_AHB>,
216 <&clkgen JH7100_CLK_GMAC_PTP_REF>,
217 <&clkgen JH7100_CLK_GMAC_TX_INV>,
218 <&clkgen JH7100_CLK_GMAC_GTX>;
242 clkgen label
[all...]
/linux/arch/arm/boot/dts/st/
H A Dstih418-clock.dtsi34 compatible = "st,clkgen-c32";
39 compatible = "st,stih418-clkgen-plla9";
49 compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
70 compatible = "st,clkgen-c32";
75 compatible = "st,clkgen-pll0-a0";
91 compatible = "st,clkgen-c32";
96 compatible = "st,clkgen-pll0-c0";
103 compatible = "st,clkgen-pll1-c0";
145 compatible = "st,clkgen
[all...]
H A Dstih410-clock.dtsi34 compatible = "st,clkgen-c32";
39 compatible = "st,stih407-clkgen-plla9";
49 compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
70 compatible = "st,clkgen-c32";
75 compatible = "st,clkgen-pll0-a0";
91 compatible = "st,clkgen-c32";
96 compatible = "st,clkgen-pll0-c0";
103 compatible = "st,clkgen-pll1-c0";
145 compatible = "st,clkgen
[all...]
H A Dstih407-clock.dtsi31 compatible = "st,clkgen-c32";
36 compatible = "st,stih407-clkgen-plla9";
43 compatible = "st,stih407-clkgen-a9-mux";
65 compatible = "st,clkgen-c32";
70 compatible = "st,clkgen-pll0-a0";
86 compatible = "st,clkgen-c32";
91 compatible = "st,clkgen-pll0-c0";
98 compatible = "st,clkgen-pll1-c0";
140 compatible = "st,clkgen-c32";
163 compatible = "st,clkgen
[all...]
/linux/arch/riscv/boot/dts/sophgo/
H A Dsg2042.dtsi7 #include <dt-bindings/clock/sophgo,sg2042-clkgen.h>
56 clocks = <&clkgen GATE_CLK_APB_I2C>;
69 clocks = <&clkgen GATE_CLK_APB_I2C>;
82 clocks = <&clkgen GATE_CLK_APB_I2C>;
95 clocks = <&clkgen GATE_CLK_APB_I2C>;
108 clocks = <&clkgen GATE_CLK_APB_GPIO>,
109 <&clkgen GATE_CLK_GPIO_DB>;
130 clocks = <&clkgen GATE_CLK_APB_GPIO>,
131 <&clkgen GATE_CLK_GPIO_DB>;
152 clocks = <&clkgen GATE_CLK_APB_GPI
209 clkgen: clock-controller@7030012000 { global() label
[all...]
/linux/Documentation/devicetree/bindings/clock/
H A Dadi,axi-clkgen.yaml4 $id: http://devicetree.org/schemas/clock/adi,axi-clkgen.yaml#
7 title: Analog Devices AXI clkgen pcore clock generator
22 - adi,axi-clkgen-2.00.a
23 - adi,zynqmp-axi-clkgen-2.00.a
63 compatible = "adi,axi-clkgen-2.00.a";
H A Dsophgo,sg2042-clkgen.yaml4 $id: http://devicetree.org/schemas/clock/sophgo,sg2042-clkgen.yaml#
14 const: sophgo,sg2042-clkgen
36 See <dt-bindings/clock/sophgo,sg2042-clkgen.h> for valid indices.
50 compatible = "sophgo,sg2042-clkgen";
H A Dnvidia,tegra20-car.yaml15 Tegra's clocks, and setting their rates. It comprises CLKGEN and RSTGEN units.
17 CLKGEN provides the registers to program the PLLs. It controls most of
20 CLKGEN input signals include the external clock for the reference frequency
23 Outputs from CLKGEN are inputs clock of the h/w blocks in the Tegra system.
H A Dnvidia,tegra124-car.yaml15 Tegra's clocks, and setting their rates. It comprises CLKGEN and RSTGEN units.
17 CLKGEN provides the registers to program the PLLs. It controls most of
20 CLKGEN input signals include the external clock for the reference frequency
23 Outputs from CLKGEN are inputs clock of the h/w blocks in the Tegra system.
H A Dstarfive,jh7100-audclk.yaml52 clocks = <&clkgen JH7100_CLK_AUDIO_SRC>,
53 <&clkgen JH7100_CLK_AUDIO_12288>,
54 <&clkgen JH7100_CLK_DOM7AHB_BUS>;
H A Dstarfive,jh7100-clkgen.yaml4 $id: http://devicetree.org/schemas/clock/starfive,jh7100-clkgen.yaml#
15 const: starfive,jh7100-clkgen
51 compatible = "starfive,jh7100-clkgen";
H A Dsophgo,sg2042-rpgate.yaml46 clocks = <&clkgen 85>;
/linux/drivers/clk/st/
H A DMakefile2 obj-y += clkgen-mux.o clkgen-pll.o clkgen-fsyn.o clk-flexgen.o
H A Dclkgen-mux.c3 * clkgen-mux.c: ST GEN-MUX Clock driver
16 #include "clkgen.h"
110 CLK_OF_DECLARE(clkgen_a9mux, "st,stih407-clkgen-a9-mux",
H A Dclkgen-pll.c18 #include "clkgen.h"
830 CLK_OF_DECLARE(c32_pll0, "st,clkgen-pll0", clkgen_c32_pll0_setup);
837 CLK_OF_DECLARE(c32_pll0_a0, "st,clkgen-pll0-a0", clkgen_c32_pll0_a0_setup);
844 CLK_OF_DECLARE(c32_pll0_c0, "st,clkgen-pll0-c0", clkgen_c32_pll0_c0_setup);
851 CLK_OF_DECLARE(c32_pll1, "st,clkgen-pll1", clkgen_c32_pll1_setup);
858 CLK_OF_DECLARE(c32_pll1_c0, "st,clkgen-pll1-c0", clkgen_c32_pll1_c0_setup);
865 CLK_OF_DECLARE(c32_plla9, "st,stih407-clkgen-plla9", clkgen_c32_plla9_setup);
872 CLK_OF_DECLARE(c28_plla9, "st,stih418-clkgen-plla9", clkgen_c28_plla9_setup);
/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-sti.c43 *| | clk-125/txclk | clkgen |
44 *| | clkgen | |
47 *| | |clkgen/phyclk-in |
60 * clkgen| 1 | 1 | n/a |
147 /* On GiGa clk source can be either ext or from clkgen */ in stih4xx_fix_retime_src()
151 /* Switch to clkgen for these speeds */ in stih4xx_fix_retime_src()
/linux/Documentation/devicetree/bindings/hwmon/
H A Dstarfive,jh71x0-temp.yaml63 clocks = <&clkgen JH7100_CLK_TEMP_SENSE>,
64 <&clkgen JH7100_CLK_TEMP_APB>;
/linux/drivers/power/sequencing/
H A Dpwrseq-thead-gpu.c58 * cycles is required between de-asserting the clkgen reset and in pwrseq_thead_gpu_enable()
193 devm_reset_control_get_exclusive(parent_dev, "gpu-clkgen"); in pwrseq_thead_gpu_probe()
197 "Failed to get GPU clkgen reset from parent\n"); in pwrseq_thead_gpu_probe()
/linux/drivers/clk/
H A Dclk-axi-clkgen.c3 * AXI clkgen driver
647 .compatible = "adi,zynqmp-axi-clkgen-2.00.a",
651 .compatible = "adi,axi-clkgen-2.00.a",
660 .name = "adi-axi-clkgen",
669 MODULE_DESCRIPTION("Driver for the Analog Devices' AXI clkgen pcore clock generator");
/linux/drivers/clk/sophgo/
H A DMakefile9 obj-$(CONFIG_CLK_SOPHGO_SG2042_CLKGEN) += clk-sg2042-clkgen.o
/linux/Documentation/devicetree/bindings/pwm/
H A Dopencores,pwm.yaml53 clocks = <&clkgen 181>;
/linux/Documentation/devicetree/bindings/firmware/
H A Dthead,th1520-aon.yaml40 - const: gpu-clkgen

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