| /linux/Documentation/devicetree/bindings/serial/ |
| H A D | actions,owl-uart.yaml | 46 clocks = <&cmu CLK_UART0>;
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| H A D | sprd-uart.yaml | 79 clocks = <&clk_ap_apb_gates 9>, <&clk_uart0>, <&ext_26m>;
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| /linux/include/dt-bindings/clock/ |
| H A D | actions,s500-cmu.h | 58 #define CLK_UART0 38 macro
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| H A D | actions,s700-cmu.h | 58 #define CLK_UART0 36 macro
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| H A D | actions,s900-cmu.h | 85 #define CLK_UART0 67 macro
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| H A D | pistachio-clk.h | 39 #define CLK_UART0 48 macro
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| H A D | exynos5250.h | 93 #define CLK_UART0 289 macro
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| H A D | s5pv210.h | 161 #define CLK_UART0 143 macro
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| H A D | exynos5420.h | 66 #define CLK_UART0 257 macro
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| H A D | exynos4.h | 150 #define CLK_UART0 312 macro
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| H A D | exynos3250.h | 222 #define CLK_UART0 216 macro
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| H A D | spacemit,k1-syscon.h | 85 #define CLK_UART0 0 macro
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| H A D | sprd,ums512-clk.h | 139 #define CLK_UART0 11 macro
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| H A D | sprd,sc9860-clk.h | 85 #define CLK_UART0 2 macro
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| H A D | rockchip,rk3528-cru.h | 404 #define CLK_UART0 392 macro
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| /linux/drivers/clk/actions/ |
| H A D | owl-s700.c | 282 static OWL_COMP_DIV(clk_uart0, "uart0", uart_clk_mux_p,
445 &clk_uart0.common,
528 [CLK_UART0] = &clk_uart0.common.hw,
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| /linux/drivers/clk/hisilicon/ |
| H A D | clk-hi3519.c | 58 { HI3519_UART0_CLK, "clk_uart0", "24m",
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| H A D | crg-hi3516cv300.c | 87 { HI3516CV300_UART0_CLK, "clk_uart0", "uart_mux", CLK_SET_RATE_PARENT,
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| /linux/drivers/clk/sophgo/ |
| H A D | clk-cv1800.c | 519 static CV1800_GATE(clk_uart0, clk_uart_parents,
1106 [CLK_UART0] = &clk_uart0.common.hw,
1337 [CLK_UART0] = &clk_uart0.common.hw,
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| /linux/arch/arm/boot/dts/samsung/ |
| H A D | s5pv210.dtsi | 321 clocks = <&clocks CLK_UART0>, <&clocks CLK_UART0>,
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| /linux/arch/arm64/boot/dts/actions/ |
| H A D | s700.dtsi | 119 clocks = <&cmu CLK_UART0>;
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| H A D | s900.dtsi | 125 clocks = <&cmu CLK_UART0>;
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| /linux/arch/arm64/boot/dts/sprd/ |
| H A D | whale2.dtsi | 78 <&ap_clk CLK_UART0>,
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| /linux/arch/arm/boot/dts/actions/ |
| H A D | owl-s500.dtsi | 136 clocks = <&cmu CLK_UART0>;
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| /linux/drivers/clk/samsung/ |
| H A D | clk-exynos5410.c | 198 GATE(CLK_UART0, "uart0", "aclk66", GATE_IP_PERIC, 0, 0, 0),
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