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/qemu/tests/qtest/migration/
H A Dmigration-qmp.c80 QObject *channels, const char *fmt, ...) in migrate_qmp_fail() argument
94 g_assert(!qdict_haskey(args, "channels")); in migrate_qmp_fail()
95 if (channels) { in migrate_qmp_fail()
96 qdict_put_obj(args, "channels", channels); in migrate_qmp_fail()
113 QObject *channels, const char *fmt, ...) in migrate_qmp() argument
126 } else if (!channels) { in migrate_qmp()
131 g_assert(!qdict_haskey(args, "channels")); in migrate_qmp()
132 if (channels) { in migrate_qmp()
133 QList *channel_list = qobject_to(QList, channels); in migrate_qmp()
135 qdict_put_obj(args, "channels", channels); in migrate_qmp()
[all …]
H A Dmisc-tests.c208 QObject *channels; in do_test_validate_uri_channel() local
218 * 'uri' and 'channels' validation is checked even before the migration in do_test_validate_uri_channel()
221 channels = args->connect_channels ? in do_test_validate_uri_channel()
224 migrate_qmp_fail(from, args->connect_uri, channels, "{}"); in do_test_validate_uri_channel()
293 migration_test_add("/migration/validate_uri/channels/both_set", in migration_test_add_misc()
295 migration_test_add("/migration/validate_uri/channels/none_set", in migration_test_add_misc()
H A Dmigration-qmp.h11 QObject *channels, const char *fmt, ...);
15 QObject *channels, const char *fmt, ...);
19 QObject *channels, const char *fmt, ...);
/qemu/hw/usb/
H A Ddev-audio.c41 static void usb_audio_reinit(USBDevice *dev, unsigned channels);
92 * number of channels, data rates, or in fact completely different
117 #define USBAUDIO_PACKET_SIZE(channels) (USBAUDIO_PACKET_SIZE_BASE * channels) argument
586 uint32_t channels) in streambuf_init() argument
589 buf->size = size - (size % USBAUDIO_PACKET_SIZE(channels)); in streambuf_init()
601 static int streambuf_put(struct streambuf *buf, USBPacket *p, uint32_t channels) in streambuf_put() argument
605 if (free < USBAUDIO_PACKET_SIZE(channels)) { in streambuf_put()
608 if (p->iov.size != USBAUDIO_PACKET_SIZE(channels)) { in streambuf_put()
613 assert(buf->prod % USBAUDIO_PACKET_SIZE(channels) == 0); in streambuf_put()
615 USBAUDIO_PACKET_SIZE(channels)); in streambuf_put()
[all …]
/qemu/audio/
H A Djackaudio.c47 int channels; member
96 static void qjack_buffer_create(QJackBuffer *buffer, int channels, int frames) in qjack_buffer_create() argument
98 buffer->channels = channels; in qjack_buffer_create()
103 buffer->data = g_new(float *, channels); in qjack_buffer_create()
104 for (int i = 0; i < channels; ++i) { in qjack_buffer_create()
123 for (int i = 0; i < buffer->channels; ++i) { in qjack_buffer_free()
136 int frames = samples / buffer->channels; in qjack_buffer_write()
148 for (int c = 0; c < buffer->channels; ++c) { in qjack_buffer_write()
162 return frames * buffer->channels * sizeof(float); in qjack_buffer_write()
182 for (int c = 0; c < buffer->channels; ++c) { in qjack_buffer_write_l()
[all …]
H A Dpaaudio.c430 map.channels = ss->channels; in qpa_simple_new()
434 * channels is the usb-audio. We will need some means to set channel in qpa_simple_new()
437 switch (ss->channels) { in qpa_simple_new()
468 dolog("Internal error: unsupported channel count %d\n", ss->channels); in qpa_simple_new()
526 ss.channels = as->nchannels; in qpa_init_out()
575 ss.channels = as->nchannels; in qpa_init_in()
678 v.channels = vol->channels; in qpa_volume_out()
679 for (i = 0; i < vol->channels; ++i) { in qpa_volume_out()
720 v.channels = vol->channels; in qpa_volume_in()
721 for (i = 0; i < vol->channels; ++i) { in qpa_volume_in()
H A Dpwaudio.c31 uint32_t channels; member
486 qpw_set_position(uint32_t channels, uint32_t position[SPA_AUDIO_MAX_CHANNELS]) in qpw_set_position() argument
492 * channels is the usb-audio. We will need some means to set channel in qpw_set_position()
495 switch (channels) { in qpw_set_position()
514 dolog("Internal error: unsupported channel count %d\n", channels); in qpw_set_position()
532 v->info.channels = as->nchannels; in qpw_init_out()
579 v->info.channels = as->nchannels; in qpw_init_in()
660 v->volume.channels = vol->channels; in qpw_voice_set_volume()
662 for (i = 0; i < vol->channels; ++i) { in qpw_voice_set_volume()
667 SPA_PROP_channelVolumes, v->volume.channels, v->volume.values, 0); in qpw_voice_set_volume()
/qemu/hw/i386/kvm/
H A Di8254.c105 pit->channels[0].irq_disabled = kpit.flags & KVM_PIT_FLAGS_HPET_LEGACY; in kvm_pit_get()
107 kchan = &kpit.channels[i]; in kvm_pit_get()
108 sc = &pit->channels[i]; in kvm_pit_get()
124 sc = &pit->channels[0]; in kvm_pit_get()
142 kpit.flags = pit->channels[0].irq_disabled ? KVM_PIT_FLAGS_HPET_LEGACY : 0; in kvm_pit_put()
144 kchan = &kpit.channels[i]; in kvm_pit_put()
145 sc = &pit->channels[i]; in kvm_pit_put()
214 PITChannelState *s = &pit->channels[0]; in kvm_pit_irq_control()
/qemu/hw/misc/
H A Dbcm2835_cprman.c12 * - the PLL channels
16 * channels. Those channel are then connected to the clock muxes. Each mux has
17 * multiples sources (usually the xosc, some of the PLL channels and some "test
33 * | some channels [mux]
193 /* Some channels have an additional fixed divider */ in pll_channel_update()
199 /* Update a PLL and all its channels */
208 CprmanPllChannelState *channel = &s->channels[i]; in pll_update_all_channels()
499 pll_channel_update(&s->channels[i]); in update_channel_from_a2w()
547 * A given CM_PLLx register is shared by both the PLL and the channels in cprman_write()
640 device_cold_reset(DEVICE(&s->channels[i])); in cprman_reset()
[all …]
H A Dstm32l4x5_rcc.c216 old_channel_freq = clock_get_hz(pll->channels[i]); in pll_update()
233 clock_update_hz(pll->channels[i], channel_freq); in pll_update()
258 s->channels[i] = qdev_init_clock_out(DEVICE(s), names[i]); in pll_init()
287 VMSTATE_ARRAY_CLOCK(channels, RccPllState,
1311 s->plls[RCC_PLL_PLL].channels[RCC_PLL_CHANNEL_PLLCLK], in connect_mux_sources()
1313 s->plls[RCC_PLL_PLLSAI1].channels[RCC_PLLSAI1_CHANNEL_PLLSAI1CLK], in connect_mux_sources()
1315 s->plls[RCC_PLL_PLLSAI2].channels[RCC_PLLSAI2_CHANNEL_PLLSAI2CLK], in connect_mux_sources()
1317 s->plls[RCC_PLL_PLL].channels[RCC_PLL_CHANNEL_PLLSAI3CLK], in connect_mux_sources()
1319 s->plls[RCC_PLL_PLL].channels[RCC_PLL_CHANNEL_PLL48M1CLK], in connect_mux_sources()
1321 s->plls[RCC_PLL_PLLSAI1].channels[RCC_PLLSAI1_CHANNEL_PLL48M2CLK], in connect_mux_sources()
[all …]
/qemu/include/hw/xen/interface/
H A Devent_channel.h5 * Event channels between domains.
16 * `incontents 150 evtchn Event Channels
18 * Event channels are the basic primitive provided by Xen for event
33 * Event channels are represented by the evtchn_* fields in
223 * 1. IPI-bound channels always notify the vcpu specified at bind time.
225 * 2. Per-VCPU VIRQ channels always notify the vcpu specified at bind time.
227 * 3. All other channels notify vcpu0 by default. This default is set when
249 * EVTCHNOP_reset: Close all event channels associated with specified domain.
/qemu/hw/timer/
H A Di8254.c139 s = &pit->channels[channel]; in pit_ioport_write()
158 s = &pit->channels[channel]; in pit_ioport_write()
173 s = &pit->channels[addr]; in pit_ioport_write()
208 s = &pit->channels[addr]; in pit_ioport_read()
291 s = &pit->channels[0]; in pit_reset()
302 PITChannelState *s = &pit->channels[0]; in pit_irq_control()
325 PITChannelState *sc = &s->channels[0]; in pit_post_load()
340 s = &pit->channels[0]; in pit_realizefn()
H A Di8254_common.c38 PITChannelState *s = &pit->channels[channel]; in pit_set_gate()
145 PITChannelState *s = &pit->channels[channel]; in pit_get_channel_info()
157 s = &pit->channels[i]; in pit_reset_common()
232 VMSTATE_UINT32_V(channels[0].irq_disabled, PITCommonState, 3),
233 VMSTATE_STRUCT_ARRAY(channels, PITCommonState, 3, 2,
235 VMSTATE_INT64(channels[0].next_transition_time,
/qemu/migration/
H A Dfile.c71 * Enable O_DIRECT for the secondary channels. These are used in file_send_channel_create()
140 int i, channels = 1; in file_create_incoming_channels() local
145 channels += migrate_multifd_channels(); in file_create_incoming_channels()
151 iocs = g_new0(QIOChannel *, channels); in file_create_incoming_channels()
154 for (i = 1; i < channels; i++) { in file_create_incoming_channels()
167 for (i = 0; i < channels; i++) { in file_create_incoming_channels()
H A Dmultifd.c68 * Synchronization point past which no more channels will be
72 /* send channels ready */
219 "number of channels %u", msg.id, migrate_multifd_channels()); in multifd_recv_initial_packet()
371 * using more channels, so ensure it doesn't overflow if the in multifd_send()
499 * channels have no I/O handler callback registered when reaching in multifd_send_cleanup_channel()
969 * Wait until channel creation has started for all channels. The in multifd_send_setup()
970 * creation can still fail, but no more channels will be created in multifd_send_setup()
1012 * using more channels, so ensure it doesn't overflow if the in multifd_recv()
1078 * The migration thread and channels interact differently in multifd_recv_terminate_threads()
1103 * - error quit: We close the channels so the channel threads in multifd_recv_terminate_threads()
[all …]
/qemu/tests/migration-stress/guestperf/
H A Dcomparison.py127 # varying numbers of channels
129 Scenario("compr-multifd-channels-4",
131 Scenario("compr-multifd-channels-8",
133 Scenario("compr-multifd-channels-32",
135 Scenario("compr-multifd-channels-64",
/qemu/hw/i2c/
H A Di2c_mux_pca954x.c37 * @channel: The set of i2c channel buses that act as channels which own the
53 * @nchans: The number of i2c channels this device has.
138 * len should be 1, because they write one byte to enable/disable channels. in pca954x_write_data()
162 /* Reset will disable all channels. */ in pca954x_enter_reset()
208 /* start all channels as disabled. */ in pca954x_init()
/qemu/include/hw/misc/
H A Dnpcm7xx_pwm.h23 /* Each PWM module holds 4 PWM channels. */
79 * @pwm: The PWM channels owned by this module.
80 * @duty_gpio_out: The duty cycle of each PWM channels as a output GPIO.
/qemu/qapi/
H A Dmigration.json60 # between 0 and @dirty-sync-count * @multifd-channels.
637 # adding a second migration channel of type "cpr" in the channels
639 # channels, and enters the postmigrate state. Execution resumes
643 # the CPR channel cannot be specified in the list of channels for
822 # @multifd-channels: Number of channels used to migrate data in
907 'multifd-channels',
1003 # @multifd-channels: Number of channels used to migrate data in
1099 '*multifd-channels': 'uint8',
1125 # "arguments": { "multifd-channels": 5 } }
1213 # @multifd-channels: Number of channels used to migrate data in
[all …]
/qemu/include/standard-headers/linux/
H A Dvirtio_snd.h245 /* minimum # of supported channels */
247 /* maximum # of supported channels */
263 /* selected # of channels */
264 uint8_t channels; member
342 /* maximum possible number of channels */
351 uint8_t channels; member
/qemu/docs/devel/migration/
H A DCPR.rst165 adding a second migration channel of type ``cpr`` in the channels
167 channels, and enters the postmigrate state. Execution resumes in
171 the CPR channel cannot be specified in the list of channels for a
250 {"execute": "migrate", "arguments": { "channels": [
299 {"execute": "migrate", "arguments": { "channels": [
H A Dqatzip-compression.rst9 The following test was conducted using 8 multifd channels and 10Gbps network
22 |8 Channels |Total |down |throughput|pages per | send | recv |
125 number of devices used for migration and the number of multifd channels.
135 * - Number of channels
H A Dvfio.rst96 config that arrived via multifd channels.
221 For data transmitted via multifd channels .load_state_buffer() is called
240 _STOP_COPY state via multifd channels. This helps reduce downtime - especially
248 AUTO, which means that VFIO device state transfer via multifd channels is
/qemu/hw/dma/
H A Di8257.c68 static const int channels[8] = {-1, 2, 3, 1, -1, -1, -1, 0}; variable
75 ichan = channels[nport & 7]; in i8257_write_page()
88 ichan = channels[nport & 7]; in i8257_write_pageh()
101 ichan = channels[nport & 7]; in i8257_read_page()
114 ichan = channels[nport & 7]; in i8257_read_pageh()
248 case 0x06: /* clear mask for all channels */ in i8257_write_cont()
253 case 0x07: /* write mask for all channels */ in i8257_write_cont()
/qemu/include/hw/hyperv/
H A Dvmbus.h40 * Base class for VMBus devices. Includes one or more channels. Identified by
59 * Calculate the number of channels based on the device properties. Called
84 VMBusChannel *channels; member

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