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/linux/drivers/usb/renesas_usbhs/
H A Dfifo.c1 // SPDX-License-Identifier: GPL-1.0+
15 #define usbhsf_get_cfifo(p) (&((p)->fifo_info.cfifo))
17 #define usbhsf_fifo_is_busy(f) ((f)->pipe) /* see usbhs_pipe_select_fifo */
24 INIT_LIST_HEAD(&pkt->node); in usbhs_pkt_init()
32 struct usbhs_priv *priv = usbhs_pipe_to_priv(pkt->pipe); in usbhsf_null_handle()
37 return -EINVAL; in usbhsf_null_handle()
48 void *buf, int len, int zero, int sequence) in usbhs_pkt_push() argument
62 if (!pipe->handler) { in usbhs_pkt_push()
64 pipe->handler = &usbhsf_null_handler; in usbhs_pkt_push()
67 list_move_tail(&pkt->node, &pipe->list); in usbhs_pkt_push()
[all …]
/linux/drivers/isdn/hardware/mISDN/
H A Dhfcsusb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * mISDN driver for Colognechip HFC-S USB chip
5 * Copyright 2001 by Peter Sprenger (sprenger@moving-bytes.de)
6 * Copyright 2008 by Martin Bachem (info@bachem-it.com)
10 * H - l1 driver flags described in hfcsusb.h
11 * G - common mISDN debug flags described at mISDNhw.h
16 * Revision: 0.3.3 (socket), 2008-11-05
34 MODULE_DESCRIPTION("mISDN driver for Colognechip HFC-S USB chip");
46 static void hfcsusb_start_endpoint(struct hfcsusb *hw, int channel);
47 static void hfcsusb_stop_endpoint(struct hfcsusb *hw, int channel);
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H A Dhfcmulti.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * hfcmulti.c low level driver for hfc-4s/hfc-8s/hfc-e1 based cards
7 * Peter Sprenger (sprengermoving-bytes.de)
9 * inspired by existing hfc-pci driver:
10 * Copyright 1999 by Werner Cornelius (werner@isdn-development.de)
22 * Bit 0-7 = 0x00001 = HFC-E1 (1 port)
23 * or Bit 0-7 = 0x00004 = HFC-4S (4 ports)
24 * or Bit 0-7 = 0x00008 = HFC-8S (8 ports)
26 * Bit 9 = 0x00200 = Disable DTMF detect on all B-channels via hardware
38 * example: 0x20204 one HFC-4S with dtmf detection and 128 timeslots on PCM
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/linux/drivers/mailbox/
H A Dcix-mailbox.c1 // SPDX-License-Identifier: GPL-2.0
23 /* [0~7] Fast channel
24 * [8] doorbell base channel
25 * [9]fifo base channel
26 * [10] register base channel
105 * For the REG and FIFO types of transfers, the message format is as follows:
119 if (priv->use_shmem) in cix_mbox_write()
120 iowrite32(val, priv->base + offset - CIX_SHMEM_OFFSET); in cix_mbox_write()
122 iowrite32(val, priv->base + offset); in cix_mbox_write()
127 if (priv->use_shmem) in cix_mbox_read()
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/linux/drivers/scsi/csiostor/
H A Dcsio_hw_t5.c4 * Copyright (c) 2008-2013 Chelsio Communications, Inc. All rights reserved.
15 * - Redistributions of source code must retain the above
19 * - Redistributions in binary form must reproduce the above
42 * Truncation intentional: we only read the bottom 32-bits of the in csio_t5_set_mem_win()
43 * 64-bit BAR0/BAR1 ... We use the hardware backdoor mechanism to in csio_t5_set_mem_win()
46 * accesses to our Configuration Space and we need to set up the PCI-E in csio_t5_set_mem_win()
48 * coming across the PCI-E link. in csio_t5_set_mem_win()
60 WINDOW_V(ilog2(MEMWIN_APERTURE) - 10), in csio_t5_set_mem_win()
76 -1, 1 }, in csio_t5_pcie_intr_handler()
77 { MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 }, in csio_t5_pcie_intr_handler()
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/linux/drivers/rpmsg/
H A Dqcom_smd.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
27 * The Qualcomm Shared Memory communication solution provides point-to-point
30 * Each channel consists of a control item (channel info) and a ring buffer
31 * pair. The channel info carry information related to channel state, flow
37 * Upon creating a new channel the remote processor allocates channel info and
39 * interrupt is sent to the other end of the channel and a scan for new
40 * channels should be done. A channel never goes away, it will only change
44 * channel by setting the state of its end of the channel to "opening" and
46 * consume the channel. Upon finding a consumer we finish the handshake and the
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H A Dqcom_glink_smem.c1 // SPDX-License-Identifier: GPL-2.0
56 void *fifo; member
66 struct qcom_glink_smem *smem = pipe->smem; in glink_smem_rx_avail()
67 size_t len; in glink_smem_rx_avail() local
68 void *fifo; in glink_smem_rx_avail() local
72 if (!pipe->fifo) { in glink_smem_rx_avail()
73 fifo = qcom_smem_get(smem->remote_pid, in glink_smem_rx_avail()
74 SMEM_GLINK_NATIVE_XPRT_FIFO_1, &len); in glink_smem_rx_avail()
75 if (IS_ERR(fifo)) { in glink_smem_rx_avail()
76 pr_err("failed to acquire RX fifo handle: %ld\n", in glink_smem_rx_avail()
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H A Dqcom_glink_native.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016-2017, Linaro Ltd
48 * struct glink_defer_cmd - deferred incoming control message
64 * struct glink_core_rx_intent - RX intent
67 * @data: pointer to the data (may be NULL for zero-copy)
71 * @in_use: To mark if intent is already in use for the channel
87 * struct qcom_glink - driver context, relates to one remote subsystem
90 * @rx_pipe: pipe object for receive FIFO
91 * @tx_pipe: pipe object for transmit FIFO
95 * @tx_lock: synchronizes operations on the tx fifo
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H A Dqcom_glink_rpm.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016-2017, Linaro Ltd
27 #define RPM_TOC_MAX_ENTRIES ((RPM_TOC_SIZE - sizeof(struct rpm_toc)) / \
54 void __iomem *fifo; member
75 head = readl(pipe->head); in glink_rpm_rx_avail()
76 tail = readl(pipe->tail); in glink_rpm_rx_avail()
79 return pipe->native.length - tail + head; in glink_rpm_rx_avail()
81 return head - tail; in glink_rpm_rx_avail()
89 size_t len; in glink_rpm_rx_peek() local
91 tail = readl(pipe->tail); in glink_rpm_rx_peek()
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/linux/drivers/spi/
H A Dspi-dw-dma.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/dma-mapping.h>
15 #include <linux/platform_data/dma-dw.h>
19 #include "spi-dw.h"
30 if (s->dma_dev != chan->device->dev) in dw_spi_dma_chan_filter()
33 chan->private = s; in dw_spi_dma_chan_filter()
43 def_burst = dws->fifo_len / 2; in dw_spi_dma_maxburst_init()
45 ret = dma_get_slave_caps(dws->rxchan, &caps); in dw_spi_dma_maxburst_init()
51 dws->rxburst = min(max_burst, def_burst); in dw_spi_dma_maxburst_init()
52 dw_writel(dws, DW_SPI_DMARDLR, dws->rxburst - 1); in dw_spi_dma_maxburst_init()
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H A Dspi-bcm2835.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 * spi-ath79.c, Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
11 * spi-atmel.c, Copyright (C) 2006 Atmel Corporation
19 #include <linux/dma-mapping.h>
76 #define DRV_NAME "spi-bcm2835"
85 * struct bcm2835_spi - BCM2835 SPI controller
88 * @cs_gpio: chip-select GPIO descriptor
90 * @irq: interrupt, signals TX FIFO empty or RX FIFO ¾ full
102 * @debugfs_dir: the debugfs directory - neede to remove debugfs when
116 * @fill_tx_desc: preallocated TX DMA descriptor used for RX-only transfers
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H A Dspi-au1550.c1 // SPDX-License-Identifier: GPL-2.0-or-later
21 #include <linux/dma-mapping.h>
23 #include <asm/mach-au1x00/au1000.h>
24 #include <asm/mach-au1x00/au1xxx_psc.h>
25 #include <asm/mach-au1x00/au1xxx_dbdma.h>
27 #include <asm/mach-au1x00/au1550_spi.h>
46 unsigned int len; member
76 /* we use an 8-bit memory device for dma transfers to/from spi fifo */
103 u32 mainclk_hz = hw->pdata->mainclk_hz; in au1550_spi_baudcfg()
120 brg--; in au1550_spi_baudcfg()
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/linux/Documentation/devicetree/bindings/crypto/
H A Dfsl,sec2.0.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale SoC SEC Security Engines versions 1.x-2.x-3.x
10 - J. Neuschäfer <j.ne@posteo.net>
16 high to low. Warning - SEC1 and SEC2 are mutually exclusive.
18 - items:
19 - const: fsl,sec3.3
20 - const: fsl,sec3.1
21 - const: fsl,sec3.0
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/linux/drivers/crypto/
H A Dtalitos.h1 /* SPDX-License-Identifier: BSD-3-Clause */
5 * Copyright (c) 2006-2011 Freescale Semiconductor, Inc.
20 __be16 len; /* length */ member
39 struct talitos_ptr ptr[7]; /* ptr/len pair array */
43 #define TALITOS_DESC_SIZE (sizeof(struct talitos_desc) - sizeof(__be32))
46 * talitos_edesc - s/w-extended descriptor
74 * talitos_request - descriptor submission request
88 /* per-channel fifo management */
92 /* request fifo */
93 struct talitos_request *fifo; member
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/linux/sound/arm/
H A Daaci.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/sound/arm/aaci.c - ARM PrimeCell AACI PL041 driver
28 #define DRIVER_NAME "aaci-pl041"
39 u32 v, maincr = aaci->maincr | MAINCR_SCRA(ac97->num); in aaci_ac97_select_codec()
44 v = readl(aaci->base + AACI_SLFR); in aaci_ac97_select_codec()
46 readl(aaci->base + AACI_SL2RX); in aaci_ac97_select_codec()
48 readl(aaci->base + AACI_SL1RX); in aaci_ac97_select_codec()
50 if (maincr != readl(aaci->base + AACI_MAINCR)) { in aaci_ac97_select_codec()
51 writel(maincr, aaci->base + AACI_MAINCR); in aaci_ac97_select_codec()
52 readl(aaci->base + AACI_MAINCR); in aaci_ac97_select_codec()
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/linux/drivers/dma/
H A Daltera-msgdma.c1 // SPDX-License-Identifier: GPL-2.0-or-later
13 #include <linux/dma-mapping.h>
30 * struct msgdma_extended_desc - implements an extended descriptor
33 * @len: the number of bytes to transfer per descriptor
46 u32 len; member
69 * descriptor FIFO(s)
107 #define MSGDMA_CSR_RW_FILL_LEVEL 0x08 /* 31:16 - write fill level */
108 /* 15:00 - read fill level */
109 #define MSGDMA_CSR_RESP_FILL_LEVEL 0x0c /* response FIFO fill level */
110 #define MSGDMA_CSR_RW_SEQ_NUM 0x10 /* 31:16 - write seq number */
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/linux/drivers/dma/dw/
H A Didma32.c1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (C) 2013,2018,2020-2021 Intel Corporation
38 struct device *slave = dwc->chan.slave; in idma32_get_slave_devfn()
43 return to_pci_dev(slave)->devfn; in idma32_get_slave_devfn()
48 struct dw_dma *dw = to_dw_dma(dwc->chan.device); in idma32_initialize_chan_xbar()
54 /* DMA Channel ID Configuration register must be programmed first */ in idma32_initialize_chan_xbar()
58 value |= dwc->chan.chan_id; in idma32_initialize_chan_xbar()
62 /* Configure channel attributes */ in idma32_initialize_chan_xbar()
63 value = readl(misc + DMA_CTL_CH(dwc->chan.chan_id)); in idma32_initialize_chan_xbar()
69 switch (dwc->direction) { in idma32_initialize_chan_xbar()
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/linux/drivers/usb/musb/
H A Dmusb_host.c1 // SPDX-License-Identifier: GPL-2.0
6 * Copyright (C) 2005-2006 by Texas Instruments
7 * Copyright (C) 2006-2007 Nokia Corporation
8 * Copyright (C) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
19 #include <linux/dma-mapping.h>
25 /* MUSB HOST status 22-mar-2006
27 * - There's still lots of partial code duplication for fault paths, so
30 * - PIO mostly behaved when last tested.
37 * - DMA (CPPI) ... partially behaves, not currently recommended
42 * - DMA (Mentor/OMAP) ...has at least toggle update problems
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/linux/drivers/misc/
H A Dhpilo.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2008 Hewlett-Packard Development Company, L.P.
52 static inline int mk_entry(int id, int len) in mk_entry() argument
54 int qlen = len & 7 ? (len >> 3) + 1 : len >> 3; in mk_entry()
64 * FIFO queues, shared with hardware.
75 struct fifo *fifo_q = FIFOBARTOHANDLE(fifobar); in fifo_enqueue()
79 spin_lock_irqsave(&hw->fifo_lock, flags); in fifo_enqueue()
80 if (!(fifo_q->fifobar[(fifo_q->tail + 1) & fifo_q->imask] in fifo_enqueue()
82 fifo_q->fifobar[fifo_q->tail & fifo_q->imask] |= in fifo_enqueue()
83 (entry & ENTRY_MASK_NOSTATE) | fifo_q->merge; in fifo_enqueue()
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/linux/drivers/dma/stm32/
H A Dstm32-dma3.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/dma-mapping.h>
24 #include "../virt-dma.h"
56 /* MISR DMA non-secure/secure masked interrupt status register */
59 /* CxLBAR DMA channel x linked_list base address register */
62 /* CxCIDCFGR DMA channel x CID register */
76 /* CxSEMCR DMA channel x semaphore control register */
80 /* CxFCR DMA channel x flag clear register */
88 /* CxSR DMA channel x status register */
99 /* CxCR DMA channel x control register */
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/linux/sound/firewire/
H A Damdtp-am824.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * AM824 format in Audio and Music Data Transmission Protocol (IEC 61883-6)
6 * Copyright (c) 2015 Takashi Sakamoto <o-takashi@sakamocchi.jp>
11 #include "amdtp-am824.h"
15 /* "Clock-based rate control mode" is just supported. */
42 * amdtp_am824_set_parameters - set stream parameters
46 * as AM824 multi-bit linear audio
47 * @midi_ports: the number of MIDI ports (i.e., MPX-MIDI Data Channels)
58 struct amdtp_am824 *p = s->protocol; in amdtp_am824_set_parameters()
64 return -EINVAL; in amdtp_am824_set_parameters()
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/linux/drivers/net/wireless/realtek/rtw88/
H A Dfw.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
71 val = rtw_read32_mask(rtwdev, reg->addr, reg->mask); in _rtw_fw_dump_dbg_info()
74 reg->desc, reg->addr, reg->mask, val); in _rtw_fw_dump_dbg_info()
100 sub_cmd_id = c2h->payload[0]; in rtw_fw_c2h_cmd_handle_ext()
148 struct rtw_c2h_ra_rpt *ra_rpt = (struct rtw_c2h_ra_rpt *)ra_data->payload; in rtw_fw_ra_report_iter()
149 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; in rtw_fw_ra_report_iter()
154 mac_id = ra_rpt->mac_id; in rtw_fw_ra_report_iter()
155 if (si->mac_id != mac_id) in rtw_fw_ra_report_iter()
158 si->ra_report.txrate.flags = 0; in rtw_fw_ra_report_iter()
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/linux/drivers/net/can/rcar/
H A Drcar_canfd.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Renesas R-Car CAN FD device driver
7 /* The R-Car CAN FD controller can operate in either one of the below two modes
8 * - CAN FD only mode
9 * - Classical CAN (CAN 2.0) only mode
16 * "renesas,no-can-fd" optional property to the device tree node. A h/w reset is
74 /* Non-operational status */
87 ((x) & ((FIELD_PREP(RCANFD_GERFL_EEF, (_gpriv)->channels_mask)) | \
88 RCANFD_GERFL_MES | ((_gpriv)->fdmode ? RCANFD_GERFL_CMPOF : 0))); \
95 #define RCANFD_GAFLECTR_AFLPN(gpriv, page_num) ((page_num) & (gpriv)->info->max_aflpn)
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/linux/arch/mips/alchemy/common/
H A Ddma.c4 * A DMA channel allocator for Au1x00. API is modeled loosely off of
9 * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
40 #include <asm/mach-au1x00/au1000.h>
41 #include <asm/mach-au1x00/au1000_dma.h>
55 * done interrupt, you won't know the irq number until the DMA channel is
59 /* DMA Channel register block spacing */
65 {.dev_id = -1,},
66 {.dev_id = -1,},
67 {.dev_id = -1,},
68 {.dev_id = -1,},
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/linux/drivers/tty/
H A Dmips_ejtag_fdc.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2007-2015 Imagination Technologies Ltd
71 /* Default channel for the early console */
80 * and space becoming available in TX FIFO.
87 * struct mips_ejtag_fdc_tty_port - Wrapper struct for FDC tty_port.
117 * struct mips_ejtag_fdc_tty - Driver data for FDC as a whole.
121 * @fdc_name: FDC name (not for base of channel names).
123 * @ports: Per-channel data.
125 * FIFO.
129 * @tx_fifo: TX FIFO size.
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