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/linux-5.10/drivers/usb/cdns3/
Dcore.c28 static int cdns3_idle_init(struct cdns3 *cdns);
30 static int cdns3_role_start(struct cdns3 *cdns, enum usb_role role) in cdns3_role_start() argument
37 mutex_lock(&cdns->mutex); in cdns3_role_start()
38 cdns->role = role; in cdns3_role_start()
39 mutex_unlock(&cdns->mutex); in cdns3_role_start()
41 if (!cdns->roles[role]) in cdns3_role_start()
44 if (cdns->roles[role]->state == CDNS3_ROLE_STATE_ACTIVE) in cdns3_role_start()
47 mutex_lock(&cdns->mutex); in cdns3_role_start()
48 ret = cdns->roles[role]->start(cdns); in cdns3_role_start()
50 cdns->roles[role]->state = CDNS3_ROLE_STATE_ACTIVE; in cdns3_role_start()
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Ddrd.c26 * @cdns: pointer to context structure
31 int cdns3_set_mode(struct cdns3 *cdns, enum usb_dr_mode mode) in cdns3_set_mode() argument
41 dev_dbg(cdns->dev, "Set controller to OTG mode\n"); in cdns3_set_mode()
42 if (cdns->version == CDNS3_CONTROLLER_V1) { in cdns3_set_mode()
43 reg = readl(&cdns->otg_v1_regs->override); in cdns3_set_mode()
45 writel(reg, &cdns->otg_v1_regs->override); in cdns3_set_mode()
53 if (cdns->phyrst_a_enable) { in cdns3_set_mode()
54 reg = readl(&cdns->otg_v1_regs->phyrst_cfg); in cdns3_set_mode()
56 writel(reg, &cdns->otg_v1_regs->phyrst_cfg); in cdns3_set_mode()
59 reg = readl(&cdns->otg_v0_regs->ctrl1); in cdns3_set_mode()
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Dhost.c18 static int __cdns3_host_init(struct cdns3 *cdns) in __cdns3_host_init() argument
24 cdns3_drd_host_on(cdns); in __cdns3_host_init()
28 dev_err(cdns->dev, "couldn't allocate xHCI device\n"); in __cdns3_host_init()
32 xhci->dev.parent = cdns->dev; in __cdns3_host_init()
33 cdns->host_dev = xhci; in __cdns3_host_init()
35 ret = platform_device_add_resources(xhci, cdns->xhci_res, in __cdns3_host_init()
38 dev_err(cdns->dev, "couldn't add resources to xHCI device\n"); in __cdns3_host_init()
44 dev_err(cdns->dev, "failed to register xHCI device\n"); in __cdns3_host_init()
51 cdns->xhci_regs = hcd->regs; in __cdns3_host_init()
59 static void cdns3_host_exit(struct cdns3 *cdns) in cdns3_host_exit() argument
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Ddrd.h162 bool cdns3_is_host(struct cdns3 *cdns);
163 bool cdns3_is_device(struct cdns3 *cdns);
164 int cdns3_get_id(struct cdns3 *cdns);
165 int cdns3_get_vbus(struct cdns3 *cdns);
166 int cdns3_drd_init(struct cdns3 *cdns);
167 int cdns3_drd_exit(struct cdns3 *cdns);
168 int cdns3_drd_update_mode(struct cdns3 *cdns);
169 int cdns3_drd_gadget_on(struct cdns3 *cdns);
170 void cdns3_drd_gadget_off(struct cdns3 *cdns);
171 int cdns3_drd_host_on(struct cdns3 *cdns);
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Dgadget-export.h15 int cdns3_gadget_init(struct cdns3 *cdns);
16 void cdns3_gadget_exit(struct cdns3 *cdns);
19 static inline int cdns3_gadget_init(struct cdns3 *cdns) in cdns3_gadget_init() argument
24 static inline void cdns3_gadget_exit(struct cdns3 *cdns) { } in cdns3_gadget_exit() argument
/linux-5.10/drivers/soundwire/
Dcadence_master.c198 static inline u32 cdns_readl(struct sdw_cdns *cdns, int offset) in cdns_readl() argument
200 return readl(cdns->registers + offset); in cdns_readl()
203 static inline void cdns_writel(struct sdw_cdns *cdns, int offset, u32 value) in cdns_writel() argument
205 writel(value, cdns->registers + offset); in cdns_writel()
208 static inline void cdns_updatel(struct sdw_cdns *cdns, in cdns_updatel() argument
213 tmp = cdns_readl(cdns, offset); in cdns_updatel()
215 cdns_writel(cdns, offset, tmp); in cdns_updatel()
218 static int cdns_set_wait(struct sdw_cdns *cdns, int offset, u32 mask, u32 value) in cdns_set_wait() argument
225 reg_read = readl(cdns->registers + offset); in cdns_set_wait()
236 static int cdns_clear_bit(struct sdw_cdns *cdns, int offset, u32 value) in cdns_clear_bit() argument
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Dintel.c123 #define cdns_to_intel(_cdns) container_of(_cdns, struct sdw_intel, cdns)
268 struct sdw_bus *bus = &sdw->cdns.bus; in intel_set_m_datamode()
286 struct sdw_bus *bus = &sdw->cdns.bus; in intel_set_s_datamode()
303 struct dentry *root = sdw->cdns.bus.debugfs; in intel_debugfs_init()
319 sdw_cdns_debugfs_init(&sdw->cdns, sdw->debugfs); in intel_debugfs_init()
340 struct sdw_bus *bus = &sdw->cdns.bus; in intel_link_power_up()
366 dev_dbg(sdw->cdns.dev, "%s: powering up all links\n", __func__); in intel_link_power_up()
369 dev_dbg(sdw->cdns.dev, in intel_link_power_up()
391 dev_err(sdw->cdns.dev, "Failed to power up link: %d\n", ret); in intel_link_power_up()
399 dev_err(sdw->cdns.dev, in intel_link_power_up()
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Dcadence_master.h147 int sdw_cdns_probe(struct sdw_cdns *cdns);
153 int sdw_cdns_init(struct sdw_cdns *cdns);
154 int sdw_cdns_pdi_init(struct sdw_cdns *cdns,
156 int sdw_cdns_exit_reset(struct sdw_cdns *cdns);
157 int sdw_cdns_enable_interrupt(struct sdw_cdns *cdns, bool state);
159 bool sdw_cdns_is_clock_stop(struct sdw_cdns *cdns);
160 int sdw_cdns_clock_stop(struct sdw_cdns *cdns, bool block_wake);
161 int sdw_cdns_clock_restart(struct sdw_cdns *cdns, bool bus_reset);
164 void sdw_cdns_debugfs_init(struct sdw_cdns *cdns, struct dentry *root);
167 struct sdw_cdns_pdi *sdw_cdns_alloc_pdi(struct sdw_cdns *cdns,
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/linux-5.10/Documentation/devicetree/bindings/mtd/
Dcadence-quadspi.txt5 Generic default - "cdns,qspi-nor".
6 For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor".
7 For TI AM654 SoC - "ti,am654-ospi", "cdns,qspi-nor".
14 - cdns,fifo-depth : Size of the data FIFO in words.
15 - cdns,fifo-width : Bus width of the data FIFO in bytes.
16 - cdns,trigger-address : 32-bit indirect AHB trigger address.
19 - cdns,is-decoded-cs : Flag to indicate whether decoder is used or not.
20 - cdns,rclk-en : Flag to indicate that QSPI return clock is used to latch
27 - cdns,read-delay : Delay for read capture logic, in clock cycles
28 - cdns,tshsl-ns : Delay in nanoseconds for the length that the master
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/linux-5.10/Documentation/devicetree/bindings/net/
Dmacb.txt4 - compatible: Should be "cdns,[<chip>-]{macb|gem}"
5 Use "cdns,at91rm9200-emac" Atmel at91rm9200 SoC.
6 Use "cdns,at91sam9260-macb" for Atmel at91sam9 SoCs.
7 Use "cdns,sam9x60-macb" for Microchip sam9x60 SoC.
8 Use "cdns,np4-macb" for NP4 SoC devices.
9 Use "cdns,at32ap7000-macb" for other 10/100 usage or use the generic form: "cdns,macb".
10 Use "cdns,pc302-gem" for Picochip picoXcell pc302 and later devices based on
11 the Cadence GEM, or the generic form: "cdns,gem".
16 Use "cdns,zynq-gem" Xilinx Zynq-7xxx SoC.
17 Use "cdns,zynqmp-gem" for Zynq Ultrascale+ MPSoC.
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/linux-5.10/Documentation/devicetree/bindings/phy/
Dphy-cadence-torrent.yaml22 - cdns,torrent-phy
88 cdns,phy-type:
96 cdns,num-lanes:
103 cdns,ssc-mode:
112 cdns,max-bit-rate:
123 - cdns,phy-type
124 - cdns,num-lanes
150 compatible = "cdns,torrent-phy";
165 cdns,phy-type = <PHY_TYPE_DP>;
166 cdns,num-lanes = <4>;
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Dphy-cadence-sierra.txt5 - compatible: Must be "cdns,sierra-phy-t0" for Sierra in Cadence platform
23 - cdns,autoconf: A boolean property whose presence indicates that the
42 - cdns,num-lanes: Number of lanes in this group. From 1 to 4. The
44 - cdns,phy-type: Can be PHY_TYPE_PCIE or PHY_TYPE_USB3, depending on
49 compatible = "cdns,sierra-phy-t0";
60 cdns,num-lanes = <2>;
62 cdns,phy-type = <PHY_TYPE_PCIE>;
67 cdns,num-lanes = <1>;
69 cdns,phy-type = <PHY_TYPE_PCIE>;
/linux-5.10/Documentation/devicetree/bindings/mmc/
Dcdns,sdhci.yaml4 $id: http://devicetree.org/schemas/mmc/cdns,sdhci.yaml#
21 - const: cdns,sd4hc
37 cdns,phy-input-delay-sd-highspeed:
43 cdns,phy-input-delay-legacy:
49 cdns,phy-input-delay-sd-uhs-sdr12:
55 cdns,phy-input-delay-sd-uhs-sdr25:
61 cdns,phy-input-delay-sd-uhs-sdr50:
67 cdns,phy-input-delay-sd-uhs-ddr50:
73 cdns,phy-input-delay-mmc-highspeed:
79 cdns,phy-input-delay-mmc-ddr:
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/linux-5.10/Documentation/devicetree/bindings/pci/
Dcdns,cdns-pcie-ep.yaml4 $id: http://devicetree.org/schemas/pci/cdns,cdns-pcie-ep.yaml#
13 - $ref: "cdns-pcie-ep.yaml#"
18 const: cdns,cdns-pcie-ep
41 compatible = "cdns,cdns-pcie-ep";
45 cdns,max-outbound-regions = <16>;
Dcdns,cdns-pcie-host.yaml4 $id: http://devicetree.org/schemas/pci/cdns,cdns-pcie-host.yaml#
14 - $ref: "cdns-pcie-host.yaml#"
18 const: cdns,cdns-pcie-host
43 compatible = "cdns,cdns-pcie-host";
/linux-5.10/arch/arm/boot/dts/
Dsocfpga_arria10_socdk_qspi.dts20 cdns,page-size = <256>;
21 cdns,block-size = <16>;
22 cdns,read-delay = <3>;
23 cdns,tshsl-ns = <50>;
24 cdns,tsd2d-ns = <50>;
25 cdns,tchsh-ns = <4>;
26 cdns,tslch-ns = <4>;
Dsocfpga_cyclone5_vining_fpga.dts232 cdns,page-size = <256>;
233 cdns,block-size = <16>;
234 cdns,read-delay = <4>;
235 cdns,tshsl-ns = <50>;
236 cdns,tsd2d-ns = <50>;
237 cdns,tchsh-ns = <4>;
238 cdns,tslch-ns = <4>;
249 cdns,page-size = <256>;
250 cdns,block-size = <16>;
251 cdns,read-delay = <4>;
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Dsocfpga_cyclone5_sodia.dts124 cdns,page-size = <256>;
125 cdns,block-size = <16>;
126 cdns,read-delay = <4>;
127 cdns,tshsl-ns = <50>;
128 cdns,tsd2d-ns = <50>;
129 cdns,tchsh-ns = <4>;
130 cdns,tslch-ns = <4>;
Dsocfpga_arria5_socdk.dts127 cdns,page-size = <256>;
128 cdns,block-size = <16>;
129 cdns,read-delay = <4>;
130 cdns,tshsl-ns = <50>;
131 cdns,tsd2d-ns = <50>;
132 cdns,tchsh-ns = <4>;
133 cdns,tslch-ns = <4>;
Dsocfpga_cyclone5_socdk.dts132 cdns,page-size = <256>;
133 cdns,block-size = <16>;
134 cdns,read-delay = <4>;
135 cdns,tshsl-ns = <50>;
136 cdns,tsd2d-ns = <50>;
137 cdns,tchsh-ns = <4>;
138 cdns,tslch-ns = <4>;
/linux-5.10/drivers/gpu/drm/bridge/cadence/
DMakefile2 obj-$(CONFIG_DRM_CDNS_MHDP8546) += cdns-mhdp8546.o
3 cdns-mhdp8546-y := cdns-mhdp8546-core.o
4 cdns-mhdp8546-$(CONFIG_DRM_CDNS_MHDP8546_J721E) += cdns-mhdp8546-j721e.o
/linux-5.10/Documentation/devicetree/bindings/ufs/
Dcdns,ufshc.txt9 "cdns,ufshc" - Generic CDNS HCI,
10 "cdns,ufshc-m31-16nm" - CDNS UFS HC + M31 16nm PHY
26 compatible = "cdns,ufshc", "jedec,ufs-2.0";
/linux-5.10/arch/arm64/boot/dts/intel/
Dsocfpga_agilex_socdk.dts118 cdns,page-size = <256>;
119 cdns,block-size = <16>;
120 cdns,read-delay = <1>;
121 cdns,tshsl-ns = <50>;
122 cdns,tsd2d-ns = <50>;
123 cdns,tchsh-ns = <4>;
124 cdns,tslch-ns = <4>;
/linux-5.10/arch/xtensa/boot/dts/
Dcsp.dts5 compatible = "cdns,xtensa-xtfpga";
11 …bootargs = "earlycon=cdns,0xfd000000,115200 console=tty0 console=ttyPS0,115200 root=/dev/ram0 rw e…
23 compatible = "cdns,xtensa-cpu";
29 compatible = "cdns,xtensa-pic";
48 compatible = "xlnx,xuartps", "cdns,uart-r1p8";
/linux-5.10/drivers/mmc/host/
Dsdhci-cadence.c80 { "cdns,phy-input-delay-sd-highspeed", SDHCI_CDNS_PHY_DLY_SD_HS, },
81 { "cdns,phy-input-delay-legacy", SDHCI_CDNS_PHY_DLY_SD_DEFAULT, },
82 { "cdns,phy-input-delay-sd-uhs-sdr12", SDHCI_CDNS_PHY_DLY_UHS_SDR12, },
83 { "cdns,phy-input-delay-sd-uhs-sdr25", SDHCI_CDNS_PHY_DLY_UHS_SDR25, },
84 { "cdns,phy-input-delay-sd-uhs-sdr50", SDHCI_CDNS_PHY_DLY_UHS_SDR50, },
85 { "cdns,phy-input-delay-sd-uhs-ddr50", SDHCI_CDNS_PHY_DLY_UHS_DDR50, },
86 { "cdns,phy-input-delay-mmc-highspeed", SDHCI_CDNS_PHY_DLY_EMMC_SDR, },
87 { "cdns,phy-input-delay-mmc-ddr", SDHCI_CDNS_PHY_DLY_EMMC_DDR, },
88 { "cdns,phy-dll-delay-sdclk", SDHCI_CDNS_PHY_DLY_SDCLK, },
89 { "cdns,phy-dll-delay-sdclk-hsmmc", SDHCI_CDNS_PHY_DLY_HSMMC, },
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