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/linux/drivers/clk/sunxi-ng/
H A DMakefile3 obj-$(CONFIG_SUNXI_CCU) += sunxi-ccu.o
6 sunxi-ccu-y += ccu_common.o
7 sunxi-ccu-y += ccu_mmc_timing.o
8 sunxi-ccu-y += ccu_reset.o
11 sunxi-ccu-y += ccu_div.o
12 sunxi-ccu-y += ccu_frac.o
13 sunxi-ccu-y += ccu_gate.o
14 sunxi-ccu-y += ccu_mux.o
15 sunxi-ccu-y += ccu_mult.o
16 sunxi-ccu
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H A DKconfig11 tristate "Support for the Allwinner newer F1C100s CCU"
16 tristate "Support for the Allwinner D1/R528/T113 CCU"
21 tristate "Support for the Allwinner D1/R528/T113 PRCM CCU"
26 tristate "Support for the Allwinner A64 CCU"
31 tristate "Support for the Allwinner A100 CCU"
36 tristate "Support for the Allwinner A100 PRCM CCU"
41 tristate "Support for the Allwinner H6 CCU"
46 tristate "Support for the Allwinner H616 CCU"
51 tristate "Support for the Allwinner H6 and H616 PRCM CCU"
56 tristate "Support for the Allwinner A523/T527 CCU"
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H A Dccu_reset.c16 struct ccu_reset *ccu = rcdev_to_ccu_reset(rcdev); in ccu_reset_assert() local
17 const struct ccu_reset_map *map = &ccu->reset_map[id]; in ccu_reset_assert()
21 spin_lock_irqsave(ccu->lock, flags); in ccu_reset_assert()
23 reg = readl(ccu->base + map->reg); in ccu_reset_assert()
24 writel(reg & ~map->bit, ccu->base + map->reg); in ccu_reset_assert()
26 spin_unlock_irqrestore(ccu->lock, flags); in ccu_reset_assert()
34 struct ccu_reset *ccu = rcdev_to_ccu_reset(rcdev); in ccu_reset_deassert() local
35 const struct ccu_reset_map *map = &ccu->reset_map[id]; in ccu_reset_deassert()
39 spin_lock_irqsave(ccu->lock, flags); in ccu_reset_deassert()
41 reg = readl(ccu in ccu_reset_deassert()
62 struct ccu_reset *ccu = rcdev_to_ccu_reset(rcdev); ccu_reset_status() local
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/linux/Documentation/devicetree/bindings/clock/
H A Dallwinner,sun4i-a10-ccu.yaml4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-ccu.yaml#
22 - allwinner,sun4i-a10-ccu
23 - allwinner,sun5i-a10s-ccu
24 - allwinner,sun5i-a13-ccu
25 - allwinner,sun6i-a31-ccu
26 - allwinner,sun7i-a20-ccu
27 - allwinner,sun8i-a23-ccu
28 - allwinner,sun8i-a33-ccu
29 - allwinner,sun8i-a83t-ccu
30 - allwinner,sun8i-a83t-r-ccu
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H A Dbaikal,bt1-ccu-div.yaml5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-div.yaml#
15 responsible for the chip subsystems clocking and resetting. The CCU is
19 by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The
22 registers. Baikal-T1 CCU is logically divided into the next components:
24 in general can provide any frequency supported by the CCU PLLs).
32 | Baikal-T1 CCU |
50 output is primarily connected to a set of CCU PLLs. Some of PLLs CLKOUT are
51 then passed over CCU dividers to create signals required for the target clock
66 where CLKIN is the reference clock coming either from CCU PLLs or from an
77 devices, are united into a single clocks provider called System Devices CCU
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/linux/drivers/clk/bcm/
H A Dclk-kona.c17 * CCU. (I believe these polices are named "Deep Sleep", "Economy",
102 /* CCU access */
104 /* Read a 32-bit register value from a CCU's address space. */
105 static inline u32 __ccu_read(struct ccu_data *ccu, u32 reg_offset) in __ccu_read() argument
107 return readl(ccu->base + reg_offset); in __ccu_read()
110 /* Write a 32-bit register value into a CCU's address space. */
112 __ccu_write(struct ccu_data *ccu, u32 reg_offset, u32 reg_val) in __ccu_write() argument
114 writel(reg_val, ccu->base + reg_offset); in __ccu_write()
117 static inline unsigned long ccu_lock(struct ccu_data *ccu) in ccu_lock() argument
121 spin_lock_irqsave(&ccu in ccu_lock()
125 ccu_unlock(struct ccu_data * ccu,unsigned long flags) ccu_unlock() argument
134 __ccu_write_enable(struct ccu_data * ccu) __ccu_write_enable() argument
145 __ccu_write_disable(struct ccu_data * ccu) __ccu_write_disable() argument
166 __ccu_wait_bit(struct ccu_data * ccu,u32 reg_offset,u32 bit,bool want) __ccu_wait_bit() argument
189 __ccu_policy_engine_start(struct ccu_data * ccu,bool sync) __ccu_policy_engine_start() argument
243 __ccu_policy_engine_stop(struct ccu_data * ccu) __ccu_policy_engine_stop() argument
285 policy_init(struct ccu_data * ccu,struct bcm_clk_policy * policy) policy_init() argument
333 __is_clk_gate_enabled(struct ccu_data * ccu,struct bcm_clk_gate * gate) __is_clk_gate_enabled() argument
350 is_clk_gate_enabled(struct ccu_data * ccu,struct bcm_clk_gate * gate) is_clk_gate_enabled() argument
371 __gate_commit(struct ccu_data * ccu,struct bcm_clk_gate * gate) __gate_commit() argument
422 gate_init(struct ccu_data * ccu,struct bcm_clk_gate * gate) gate_init() argument
436 __clk_gate(struct ccu_data * ccu,struct bcm_clk_gate * gate,bool enable) __clk_gate() argument
461 clk_gate(struct ccu_data * ccu,const char * name,struct bcm_clk_gate * gate,bool enable) clk_gate() argument
502 hyst_init(struct ccu_data * ccu,struct bcm_clk_hyst * hyst) hyst_init() argument
528 __clk_trigger(struct ccu_data * ccu,struct bcm_clk_trig * trig) __clk_trigger() argument
539 divider_read_scaled(struct ccu_data * ccu,struct bcm_clk_div * div) divider_read_scaled() argument
566 __div_commit(struct ccu_data * ccu,struct bcm_clk_gate * gate,struct bcm_clk_div * div,struct bcm_clk_trig * trig) __div_commit() argument
622 div_init(struct ccu_data * ccu,struct bcm_clk_gate * gate,struct bcm_clk_div * div,struct bcm_clk_trig * trig) div_init() argument
630 divider_write(struct ccu_data * ccu,struct bcm_clk_gate * gate,struct bcm_clk_div * div,struct bcm_clk_trig * trig,u64 scaled_div) divider_write() argument
668 clk_recalc_rate(struct ccu_data * ccu,struct bcm_clk_div * div,struct bcm_clk_div * pre_div,unsigned long parent_rate) clk_recalc_rate() argument
723 round_rate(struct ccu_data * ccu,struct bcm_clk_div * div,struct bcm_clk_div * pre_div,unsigned long rate,unsigned long parent_rate,u64 * scaled_div) round_rate() argument
815 selector_read_index(struct ccu_data * ccu,struct bcm_clk_sel * sel) selector_read_index() argument
849 __sel_commit(struct ccu_data * ccu,struct bcm_clk_gate * gate,struct bcm_clk_sel * sel,struct bcm_clk_trig * trig) __sel_commit() argument
906 sel_init(struct ccu_data * ccu,struct bcm_clk_gate * gate,struct bcm_clk_sel * sel,struct bcm_clk_trig * trig) sel_init() argument
919 selector_write(struct ccu_data * ccu,struct bcm_clk_gate * gate,struct bcm_clk_sel * sel,struct bcm_clk_trig * trig,u8 index) selector_write() argument
1171 struct ccu_data *ccu = bcm_clk->ccu; __peri_clk_init() local
1231 kona_ccu_init(struct ccu_data * ccu) kona_ccu_init() argument
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/linux/arch/arm/boot/dts/allwinner/
H A Dsunxi-h3-h5.dtsi45 #include <dt-bindings/clock/sun8i-h3-ccu.h>
46 #include <dt-bindings/clock/sun8i-r-ccu.h>
49 #include <dt-bindings/reset/sun8i-h3-ccu.h>
50 #include <dt-bindings/reset/sun8i-r-ccu.h>
67 <&ccu CLK_TCON0>, <&ccu CLK_HDMI>;
76 <&ccu CLK_TVE>;
119 clocks = <&ccu CLK_BUS_DE>,
120 <&ccu CLK_DE>;
123 resets = <&ccu RST_BUS_D
391 ccu: clock@1c20000 { global() label
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H A Dsun4i-a10.dtsi46 #include <dt-bindings/clock/sun4i-a10-ccu.h>
47 #include <dt-bindings/reset/sun4i-a10-ccu.h>
67 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
68 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
69 <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>;
77 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI
650 ccu: clock@1c20000 { global() label
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H A Dsuniv-f1c100s.dtsi7 #include <dt-bindings/clock/suniv-ccu-f1c100s.h>
8 #include <dt-bindings/reset/suniv-ccu-f1c100s.h>
78 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_BUS_SPI0>;
80 resets = <&ccu RST_BUS_SPI0>;
92 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_BUS_SPI1>;
94 resets = <&ccu RST_BUS_SPI1>;
105 clocks = <&ccu CLK_BUS_MMC0>,
106 <&ccu CLK_MMC
172 ccu: clock@1c20000 { global() label
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H A Dsun8i-v3s.dtsi46 #include <dt-bindings/clock/sun8i-v3s-ccu.h>
47 #include <dt-bindings/reset/sun8i-v3s-ccu.h>
65 <&ccu CLK_TCON0>;
78 clocks = <&ccu CLK_CPU>;
127 clocks = <&ccu CLK_BUS_DE>,
128 <&ccu CLK_DE>;
131 resets = <&ccu RST_BUS_DE>;
181 clocks = <&ccu CLK_BUS_DMA>;
182 resets = <&ccu RST_BUS_DMA>;
190 clocks = <&ccu CLK_BUS_TCON
345 ccu: clock@1c20000 { global() label
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H A Dsun5i.dtsi45 #include <dt-bindings/clock/sun5i-ccu.h>
47 #include <dt-bindings/reset/sun5i-ccu.h>
62 clocks = <&ccu CLK_CPU>;
75 clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
76 <&ccu CLK_TCON_CH0>, <&ccu CLK_DRAM_DE_BE>;
84 clocks = <&ccu CLK_AHB_TVE>, <&ccu CLK_AHB_LC
434 ccu: clock@1c20000 { global() label
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H A Dsun7i-a20.dtsi48 #include <dt-bindings/clock/sun7i-a20-ccu.h>
49 #include <dt-bindings/reset/sun4i-a10-ccu.h>
70 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
71 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
72 <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>,
73 <&ccu CLK_HDMI>;
81 clocks = <&ccu CLK_AHB_LCD
759 ccu: clock@1c20000 { global() label
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H A Dsun8i-a23-a33.dtsi48 #include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
49 #include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
65 clocks = <&ccu CLK_BUS_LCD>, <&ccu CLK_BUS_DE_BE>,
66 <&ccu CLK_LCD_CH0>, <&ccu CLK_DE_BE>,
67 <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_DRC>;
160 clocks = <&ccu CLK_BUS_DMA>;
161 resets = <&ccu RST_BUS_DM
331 ccu: clock@1c20000 { global() label
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H A Dsun8i-a83t.dtsi47 #include <dt-bindings/clock/sun8i-a83t-ccu.h>
49 #include <dt-bindings/clock/sun8i-r-ccu.h>
50 #include <dt-bindings/reset/sun8i-a83t-ccu.h>
52 #include <dt-bindings/reset/sun8i-r-ccu.h>
67 clocks = <&ccu CLK_C0CPUX>;
78 clocks = <&ccu CLK_C0CPUX>;
89 clocks = <&ccu CLK_C0CPUX>;
100 clocks = <&ccu CLK_C0CPUX>;
111 clocks = <&ccu CLK_C1CPUX>;
122 clocks = <&ccu CLK_C1CPU
700 ccu: clock@1c20000 { global() label
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H A Dsun8i-h3.dtsi78 clocks = <&ccu CLK_CPUX>;
88 clocks = <&ccu CLK_CPUX>;
98 clocks = <&ccu CLK_CPUX>;
108 clocks = <&ccu CLK_CPUX>;
156 clocks = <&ccu CLK_BUS_DEINTERLACE>,
157 <&ccu CLK_DEINTERLACE>,
158 <&ccu CLK_DRAM_DEINTERLACE>;
160 resets = <&ccu RST_BUS_DEINTERLACE>;
191 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_V
[all...]
H A Dsun8i-a33.dtsi128 clocks = <&ccu CLK_CPUX>;
135 clocks = <&ccu CLK_CPUX>;
145 clocks = <&ccu CLK_CPUX>;
155 clocks = <&ccu CLK_CPUX>;
209 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
210 <&ccu CLK_DRAM_VE>;
212 resets = <&ccu RST_BUS_VE>;
221 clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_S
[all...]
/linux/arch/riscv/boot/dts/allwinner/
H A Dsunxi-d1s-t113.dtsi7 #include <dt-bindings/clock/sun20i-d1-ccu.h>
8 #include <dt-bindings/clock/sun20i-d1-r-ccu.h>
11 #include <dt-bindings/reset/sun20i-d1-ccu.h>
12 #include <dt-bindings/reset/sun20i-d1-r-ccu.h>
46 clocks = <&ccu CLK_APB0>,
148 ccu: clock-controller@2001000 { label
149 compatible = "allwinner,sun20i-d1-ccu";
162 clocks = <&ccu CLK_BUS_GPADC>;
163 resets = <&ccu RST_BUS_GPADC>;
174 clocks = <&ccu CLK_BUS_DMI
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/linux/arch/arm64/boot/dts/allwinner/
H A Dsun50i-h616.dtsi7 #include <dt-bindings/clock/sun50i-h616-ccu.h>
8 #include <dt-bindings/clock/sun50i-h6-r-ccu.h>
10 #include <dt-bindings/reset/sun50i-h616-ccu.h>
11 #include <dt-bindings/reset/sun50i-h6-r-ccu.h>
28 clocks = <&ccu CLK_CPUX>;
44 clocks = <&ccu CLK_CPUX>;
60 clocks = <&ccu CLK_CPUX>;
76 clocks = <&ccu CLK_CPUX>;
161 clocks = <&ccu CLK_GPU0>, <&ccu CLK_BUS_GP
194 ccu: clock@3001000 { global() label
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H A Dsun50i-a64.dtsi6 #include <dt-bindings/clock/sun50i-a64-ccu.h>
9 #include <dt-bindings/clock/sun8i-r-ccu.h>
11 #include <dt-bindings/reset/sun50i-a64-ccu.h>
13 #include <dt-bindings/reset/sun8i-r-ccu.h>
30 clocks = <&ccu CLK_TCON0>,
40 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>;
54 clocks = <&ccu CLK_CPUX>;
71 clocks = <&ccu CLK_CPUX>;
88 clocks = <&ccu CLK_CPU
699 ccu: clock@1c20000 { global() label
[all...]
H A Dsun50i-h6.dtsi5 #include <dt-bindings/clock/sun50i-h6-ccu.h>
6 #include <dt-bindings/clock/sun50i-h6-r-ccu.h>
10 #include <dt-bindings/reset/sun50i-h6-ccu.h>
11 #include <dt-bindings/reset/sun50i-h6-r-ccu.h>
29 clocks = <&ccu CLK_CPUX>;
45 clocks = <&ccu CLK_CPUX>;
61 clocks = <&ccu CLK_CPUX>;
77 clocks = <&ccu CLK_CPUX>;
156 clocks = <&ccu CLK_BUS_DE>,
157 <&ccu CLK_D
273 ccu: clock@3001000 { global() label
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H A Dsun55i-a523.dtsi6 #include <dt-bindings/clock/sun55i-a523-ccu.h>
7 #include <dt-bindings/clock/sun55i-a523-r-ccu.h>
8 #include <dt-bindings/reset/sun55i-a523-ccu.h>
9 #include <dt-bindings/reset/sun55i-a523-r-ccu.h>
119 clocks = <&ccu CLK_GPU>, <&ccu CLK_BUS_GPU>;
122 resets = <&ccu RST_BUS_GPU>;
139 clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc CLK_OSC32K>;
204 ccu: clock-controller@2001000 { label
205 compatible = "allwinner,sun55i-a523-ccu";
[all...]
H A Dsun50i-a100.dtsi7 #include <dt-bindings/clock/sun50i-a100-ccu.h>
8 #include <dt-bindings/clock/sun50i-a100-r-ccu.h>
9 #include <dt-bindings/reset/sun50i-a100-ccu.h>
10 #include <dt-bindings/reset/sun50i-a100-r-ccu.h>
26 clocks = <&ccu CLK_CPUX>;
34 clocks = <&ccu CLK_CPUX>;
42 clocks = <&ccu CLK_CPUX>;
50 clocks = <&ccu CLK_CPUX>;
141 ccu: clock@3001000 { label
142 compatible = "allwinner,sun50i-a100-ccu";
[all...]
H A Dsun50i-h5.dtsi18 clocks = <&ccu CLK_CPUX>;
27 clocks = <&ccu CLK_CPUX>;
36 clocks = <&ccu CLK_CPUX>;
45 clocks = <&ccu CLK_CPUX>;
103 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
104 <&ccu CLK_DRAM_VE>;
106 resets = <&ccu RST_BUS_VE>;
115 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_C
[all...]
/linux/include/dt-bindings/clock/
H A Dbcm281xx.h16 * These are the bcm281xx CCU device tree "compatible" strings.
21 #define BCM281XX_DT_ROOT_CCU_COMPAT "brcm,bcm11351-root-ccu"
22 #define BCM281XX_DT_AON_CCU_COMPAT "brcm,bcm11351-aon-ccu"
23 #define BCM281XX_DT_HUB_CCU_COMPAT "brcm,bcm11351-hub-ccu"
24 #define BCM281XX_DT_MASTER_CCU_COMPAT "brcm,bcm11351-master-ccu"
25 #define BCM281XX_DT_SLAVE_CCU_COMPAT "brcm,bcm11351-slave-ccu"
27 /* root CCU clock ids */
32 /* aon CCU clock ids */
39 /* hub CCU clock ids */
44 /* master CCU cloc
[all...]
/linux/drivers/clk/baikal-t1/
H A DKconfig10 means of the CCU control registers. These domains and devices placed
13 to select Baikal-T1 CCU PLLs and Dividers drivers.
18 bool "Baikal-T1 CCU PLLs support"
31 bool "Baikal-T1 CCU Dividers support"
35 Enable this to support the CCU dividers used to distribute clocks
36 between AXI-bus and system devices coming from CCU PLLs of Baikal-T1
37 SoC. CCU dividers can be either configurable or with fixed divider,
38 either gateable or ungateable. Some of the CCU dividers can be as well
42 bool "Baikal-T1 CCU Resets support"
47 Enable this to support the CCU rese
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