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Searched full:apll (Results 1 – 25 of 25) sorted by relevance

/linux-3.3/drivers/cpufreq/
Dexynos4210-cpufreq.c100 /* APLL FOUT L0: 1200MHz */
103 /* APLL FOUT L1: 1000MHz */
106 /* APLL FOUT L2: 800MHz */
109 /* APLL FOUT L3: 500MHz */
112 /* APLL FOUT L4: 200MHz */
159 /* 2. Set APLL Lock time */ in exynos4210_set_apll()
173 /* 5. MUX_CORE_SEL = APLL */ in exynos4210_set_apll()
200 /* 2. Change just s value in apll m,p,s value */ in exynos4210_set_frequency()
209 /* 2. Change the apll m,p,s value */ in exynos4210_set_frequency()
214 /* 1. Change just s value in apll m,p,s value */ in exynos4210_set_frequency()
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Ds5pv210-cpufreq.c32 /* APLL M,P,S values for 1G/800Mhz */
124 * { APLL, A2M, HCLK_MSYS, PCLK_MSYS,
284 * APLL should be changed in this level in s5pv210_target()
285 * APLL -> MPLL(for stable transition) -> APLL in s5pv210_target()
377 * 6. Turn on APLL in s5pv210_target()
420 /* 9. Change MPLL to APLL in MSYS_MUX */ in s5pv210_target()
Dexynos-cpufreq.c81 * ARM clock source will be changed APLL to MPLL temporary in exynos_target()
/linux-3.3/arch/arm/mach-omap2/
Dclkt2xxx_apll.c2 * OMAP2xxx APLL clock control functions
45 /* Enable an APLL if off */
55 return 0; /* apll already enabled */ in omap2_clk_apll_enable()
101 /* Stop APLL */
Dcm2xxx_3xxx.c161 * APLL autoidle control
Dclock2420_data.c579 * functional clocks. Fixed APLL functional source clocks are managed in
Dclock2430_data.c525 * functional clocks. Fixed APLL functional source clocks are managed in
/linux-3.3/arch/arm/plat-s5p/
Dclock.c56 /* APLL clock output
93 /* Possible clock sources for APLL Mux */
/linux-3.3/sound/soc/codecs/
Dtwl4030.c136 /* reference counts of AIF/APLL users */
1236 /* AIF and APLL clocks for running DAIs (including loopback) */
1301 SND_SOC_DAPM_SUPPLY("APLL Enable", SND_SOC_NOPM, 0, 0, apll_event,
1437 /* Supply for the digital part (APLL) */
1438 {"Digital Voice Playback Mixer", NULL, "APLL Enable"},
1514 /* Must be always connected (for AIF and APLL) */
1519 /* Must be always connected (for APLL) */
1535 /* Must be always connected (for AIF and APLL) */
1871 dev_err(codec->dev, "Unsupported APLL mclk: %u\n", freq); in twl4030_set_dai_sysclk()
1877 "Mismatch in APLL mclk: %u (configured: %u)\n", in twl4030_set_dai_sysclk()
[all …]
Dadau1373.c1155 /* APLL input needs to be >= 8Mhz, so in case freq_in is less we use the in adau1373_set_pll()
/linux-3.3/arch/arm/mach-s3c64xx/
Dclock.c777 unsigned long apll; in s3c64xx_setup_clocks() local
801 apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON)); in s3c64xx_setup_clocks()
806 apll, mpll, epll); in s3c64xx_setup_clocks()
810 hclk2 = apll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2); in s3c64xx_setup_clocks()
823 clk_fout_apll.rate = apll; in s3c64xx_setup_clocks()
/linux-3.3/drivers/staging/bcm/
DDDRInit.c16 // Changed source for X-bar and MIPS clock to APLL
126 // Changed source for X-bar and MIPS clock to APLL
186 // Changed source for X-bar and MIPS clock to APLL
198 // Changed source for X-bar and MIPS clock to APLL
201 // Changed source for X-bar and MIPS clock to APLL
363 // Changed source for X-bar and MIPS clock to APLL
425 // Changed source for X-bar and MIPS clock to APLL
601 // Changed source for X-bar and MIPS clock to APLL
664 // Changed source for X-bar and MIPS clock to APLL
/linux-3.3/arch/arm/mach-s5p64x0/
Dclock-s5p6440.c540 unsigned long apll; in s5p6440_setup_clocks() local
558 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_APLL_CON), pll_4502); in s5p6440_setup_clocks()
563 clk_fout_apll.rate = apll; in s5p6440_setup_clocks()
569 print_mhz(apll), print_mhz(mpll), print_mhz(epll)); in s5p6440_setup_clocks()
Dclock-s5p6450.c606 unsigned long apll; in s5p6450_setup_clocks() local
625 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_APLL_CON), pll_4502); in s5p6450_setup_clocks()
632 clk_fout_apll.rate = apll; in s5p6450_setup_clocks()
639 print_mhz(apll), print_mhz(mpll), print_mhz(epll), in s5p6450_setup_clocks()
/linux-3.3/include/media/
Dsaa7115.h43 #define SAA7115_FREQ_FL_APLL (1 << 2) /* SA 3A[3], APLL, SAA7114/5 only */
/linux-3.3/arch/arm/mach-s5pc100/
Dclock.c1177 unsigned long apll; in s5pc100_setup_clocks() local
1193 apll = s5p_get_pll65xx(xtal, __raw_readl(S5P_APLL_CON)); in s5pc100_setup_clocks()
1199 print_mhz(apll), print_mhz(mpll), print_mhz(epll), print_mhz(hpll)); in s5pc100_setup_clocks()
1201 clk_fout_apll.rate = apll; in s5pc100_setup_clocks()
/linux-3.3/drivers/mfd/
Dtwl4030-audio.c172 /* Configure APLL_INFREQ and disable APLL if enabled */ in twl4030_audio_probe()
/linux-3.3/arch/arm/mach-exynos/
Dclock.c1424 unsigned long apll = 0; in exynos4_setup_clocks() local
1452 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0), in exynos4_setup_clocks()
1463 apll = s5p_get_pll35xx(xtal, __raw_readl(S5P_APLL_CON0)); in exynos4_setup_clocks()
1482 apll, mpll, epll, vpll); in exynos4_setup_clocks()
/linux-3.3/sound/soc/omap/
Domap3pandora.c137 {"PCM DAC", NULL, "APLL Enable"},
/linux-3.3/arch/arm/mach-s5pv210/
Dclock.c1240 unsigned long apll; in s5pv210_setup_clocks() local
1267 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508); in s5pv210_setup_clocks()
1281 apll, mpll, epll, vpll); in s5pv210_setup_clocks()
/linux-3.3/arch/arm/mach-omap1/
Dusb.c468 pr_debug("APLL %04x DPLL %04x REQ %04x\n", omap_readw(ULPD_APLL_CTRL), in omap_1510_usb_init()
Dclock.c396 /* Determine current rate and ensure clock is based on 96MHz APLL */ in omap1_init_ext_clk()
/linux-3.3/drivers/usb/host/
Dohci-omap.c78 /* guesstimate for T5 == 1x 32K clock + APLL lock time */ in omap_ohci_clock_power()
/linux-3.3/drivers/media/video/
Dsaa7115.c88 u8 apll; member
732 if (state->apll) in saa711x_s_clock_freq()
1300 state->apll = (flags & SAA7115_FREQ_FL_APLL) ? 1 : 0; in saa711x_s_crystal_freq()
/linux-3.3/drivers/net/ethernet/dec/tulip/
Dde4x5.h687 #define SICR_ASE 0x00000080 /* APLL Start Enable*/