| /linux/Documentation/admin-guide/hw-vuln/ |
| H A D | indirect-target-selection.rst | 26 Affected CPUs
28 Below is the list of ITS affected CPUs [#f2]_ [#f3]_:
34 SKYLAKE_X (step >= 6) 06_55H Affected Affected
35 ICELAKE_X 06_6AH Not affected Affected
36 ICELAKE_D 06_6CH Not affected Affected
37 ICELAKE_L 06_7EH Not affected Affected
38 TIGERLAKE_L 06_8CH Not affected Affected
39 TIGERLAKE 06_8DH Not affected Affected
40 KABYLAKE_L (step >= 12) 06_8EH Affected Affected
41 KABYLAKE (step >= 13) 06_9EH Affected Affected
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| H A D | processor_mmio_stale_data.rst | 9 are not affected. System environments using virtualization where MMIO access is
61 processors affected by FBSDP, this may expose stale data from the fill buffers
67 into client core fill buffers, processors affected by MFBDS can leak data from
77 Affected Processors
79 Not all the CPUs are affected by all the variants. For instance, most
83 Below is the list of affected Intel processors [#f1]_:
108 If a CPU is in the affected processor list, but not affected by a variant, it
115 Newer processors and microcode update on existing affected processors added new
122 Bit 13 - SBDR_SSDP_NO - When set, processor is not affected by either the
125 Bit 14 - FBSDP_NO - When set, processor is not affected by the Fill Buffer
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| H A D | reg-file-data-sampling.rst | 11 Affected Processors
13 Below is the list of affected Intel processors [#f1]_:
36 mitigation strategy to force the CPU to clear the affected buffers before an
39 The microcode clears the affected CPU buffers when the VERW instruction is
45 before VMentry. None of the affected cores support SMT, so VERW is not required
50 Newer processors and microcode update on existing affected processors added new
54 - Bit 27 - RFDS_NO - When set, processor is not affected by RFDS.
55 - Bit 28 - RFDS_CLEAR - When set, processor is affected by RFDS, and has the
56 microcode that clears the affected buffers on VERW execution.
83 * - 'Not affected'
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| H A D | mds.rst | 8 Affected processors
23 Whether a processor is affected or not can be read out from the MDS
26 Not all processors are affected by all variants of MDS, but the mitigation
100 * - 'Not affected'
135 The kernel detects the affected CPUs and the presence of the microcode
138 If a CPU is affected and the microcode is available, then the kernel
148 The mitigation for MDS clears the affected CPU buffers on return to user
152 is only affected by MSBDS and not any other MDS variant, because the
155 For CPUs which are only affected by MSBDS the user space, guest and idle
156 transition mitigations are sufficient and SMT is not affected.
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| H A D | tsx_async_abort.rst | 10 Affected processors
19 Whether a processor is affected or not can be read out from the TAA
99 …- The CPU is affected by this vulnerability and the microcode and kernel mitigation are not applie…
118 * - 'Not affected'
119 - The CPU is not affected by this issue.
124 The kernel detects the affected CPUs and the presence of the microcode which is
125 required. If a CPU is affected and the microcode is available, then the kernel
135 Affected systems where the host has TAA microcode and TAA is mitigated by
152 off This option disables the TAA mitigation on affected platforms.
154 is affected, the system is vulnerable.
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| H A D | vmscape.rst | 13 Affected processors
16 The following CPU families are affected by VMSCAPE:
20 - Cascade Lake generation - (Parts affected by ITS guest/host separation)
21 - Alder Lake and newer (Parts affected by BHI)
23 Note that, BHI affected parts that use BHB clearing software mitigation e.g.
75 * 'Not affected':
110 not known to be affected.
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| H A D | special-register-buffer-data-sampling.rst | 17 Affected processors
20 be affected.
22 A processor is affected by SRBDS if its Family_Model and stepping is
25 latter class of processors are only affected when Intel TSX is enabled
26 by software using TSX_CTRL_MSR otherwise they are not affected.
118 affected platforms.
130 Not affected Processor not vulnerable
141 affected but with no way to know if host
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| H A D | cross-thread-rsb.rst | 18 Affected processors
38 Affected SMT-capable processors support 1T and 2T modes of execution when SMT
46 In affected processors, the return address predictor (RAP) is partitioned
61 An attack can be mounted on affected processors by performing a series of CALL
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| H A D | gather_data_sampling.rst | 76 use the microcode mitigation when available or disable AVX on affected systems
89 Not affected Processor not vulnerable.
102 affected but with no way to know if host
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| /linux/Documentation/arch/x86/ |
| H A D | mds.rst | 74 thread case (SMT off): Force the CPU to clear the affected buffers.
78 the affected CPU buffers when the VERW instruction is executed.
83 VERW can be avoided. If the CPU is not affected by L1TF then VERW needs to
119 off Mitigation is disabled. Either the CPU is not affected or
122 full Mitigation is enabled. CPU is affected and MD_CLEAR is
125 vmwerv Mitigation is enabled. CPU is affected and MD_CLEAR is not
132 If the CPU is affected and mds=off is not supplied on the kernel command
143 on affected CPUs when the mitigation is not disabled on the kernel
174 cleared on affected CPUs when SMT is active. This addresses the
181 The idle clearing is enabled on CPUs which are only affected by MSBDS
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| H A D | tsx_async_abort.rst | 37 off Mitigation is disabled. Either the CPU is not affected or
43 verw Mitigation is enabled. CPU is affected and MD_CLEAR is
46 ucode needed Mitigation is enabled. CPU is affected and MD_CLEAR is not
53 If the CPU is affected and the "tsx_async_abort" kernel command line parameter is
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| /linux/arch/x86/kernel/ |
| H A D | smp.c | 69 * 5AP. symmetric IO mode (normal Linux operation) not affected.
71 * 6AP. 'noapic' mode might be affected - fixed in later steppings
94 * 6AP. not affected - worked around in hardware
95 * 7AP. not affected - worked around in hardware
97 * 9AP. only 'noapic' mode affected. Might generate spurious
100 * 10AP. not affected - worked around in hardware
104 * 12AP. not affected - worked around in hardware
105 * 13AP. not affected - worked around in hardware
107 * 15AP. not affected - worked around in hardware
108 * 16AP. not affected - worked around in hardware
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| /linux/arch/arm64/ |
| H A D | Kconfig | 462 The affected design reports FEAT_HAFDBS as not implemented in
512 the kernel if an affected CPU is detected.
534 the kernel if an affected CPU is detected.
557 only patch the kernel if an affected CPU is detected.
579 the kernel if an affected CPU is detected.
590 Affected Cortex-A57 parts might deadlock when exclusive load/store
597 the kernel if an affected CPU is detected.
608 Affected Cortex-A57 parts might report a Stage 2 translation
617 the kernel if an affected CPU is detected.
629 Affected parts may corrupt the AES state if an interrupt is
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| /linux/security/integrity/evm/ |
| H A D | evm_main.c | 435 * @dentry: pointer to the affected dentry
452 * @dentry: pointer to the affected dentry
575 * @dentry: pointer to the affected dentry
576 * @xattr_name: pointer to the affected extended attribute name
613 * @dentry: pointer to the affected dentry
614 * @xattr_name: pointer to the affected extended attribute name
663 * @dentry: pointer to the affected dentry
716 * @dentry: pointer to the affected dentry
767 * @xattr_name: pointer to the affected extended attribute name
792 * @dentry: pointer to the affected dentry
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| /linux/arch/alpha/kernel/ |
| H A D | bugs.c | 26 return sprintf(buf, "Not affected\n"); in cpu_show_meltdown()
35 return sprintf(buf, "Not affected\n"); in cpu_show_spectre_v1()
44 return sprintf(buf, "Not affected\n"); in cpu_show_spectre_v2()
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| /linux/arch/x86/include/asm/ |
| H A D | cpufeatures.h | 479 #define X86_FEATURE_SRSO_NO (20*32+29) /* CPU is not affected by SRSO */
480 #define X86_FEATURE_SRSO_USER_KERNEL_NO (20*32+30) /* CPU is not affected by SRSO across user/kerne…
543 #define X86_BUG_AMD_E400 X86_BUG(13) /* "amd_e400" CPU is among the affected by Erratum 400 */
544 #define X86_BUG_CPU_MELTDOWN X86_BUG(14) /* "cpu_meltdown" CPU is affected by meltdown attack and …
545 #define X86_BUG_SPECTRE_V1 X86_BUG(15) /* "spectre_v1" CPU is affected by Spectre variant 1 attack…
546 #define X86_BUG_SPECTRE_V2 X86_BUG(16) /* "spectre_v2" CPU is affected by Spectre variant 2 attack…
547 #define X86_BUG_SPEC_STORE_BYPASS X86_BUG(17) /* "spec_store_bypass" CPU is affected by speculative…
548 #define X86_BUG_L1TF X86_BUG(18) /* "l1tf" CPU is affected by L1 Terminal Fault */
549 #define X86_BUG_MDS X86_BUG(19) /* "mds" CPU is affected by Microarchitectural data sampling */
550 #define X86_BUG_MSBDS_ONLY X86_BUG(20) /* "msbds_only" CPU is only affected by the MSDBS variant …
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| /linux/tools/arch/x86/include/asm/ |
| H A D | cpufeatures.h | 479 #define X86_FEATURE_SRSO_NO (20*32+29) /* CPU is not affected by SRSO */
480 #define X86_FEATURE_SRSO_USER_KERNEL_NO (20*32+30) /* CPU is not affected by SRSO across user/kerne…
543 #define X86_BUG_AMD_E400 X86_BUG(13) /* "amd_e400" CPU is among the affected by Erratum 400 */
544 #define X86_BUG_CPU_MELTDOWN X86_BUG(14) /* "cpu_meltdown" CPU is affected by meltdown attack and …
545 #define X86_BUG_SPECTRE_V1 X86_BUG(15) /* "spectre_v1" CPU is affected by Spectre variant 1 attack…
546 #define X86_BUG_SPECTRE_V2 X86_BUG(16) /* "spectre_v2" CPU is affected by Spectre variant 2 attack…
547 #define X86_BUG_SPEC_STORE_BYPASS X86_BUG(17) /* "spec_store_bypass" CPU is affected by speculative…
548 #define X86_BUG_L1TF X86_BUG(18) /* "l1tf" CPU is affected by L1 Terminal Fault */
549 #define X86_BUG_MDS X86_BUG(19) /* "mds" CPU is affected by Microarchitectural data sampling */
550 #define X86_BUG_MSBDS_ONLY X86_BUG(20) /* "msbds_only" CPU is only affected by the MSDBS variant …
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| /linux/Documentation/process/ |
| H A D | embargoed-hardware-issues.rst | 46 While hardware security issues are often handled by the affected silicon
129 description of the problem and a list of any known affected silicon. If
130 your organization builds or distributes the affected hardware, we encourage
131 you to also consider what other hardware could be affected. The disclosing
132 party is responsible for contacting the affected silicon vendors in a
229 To allow the affected silicon vendors to work with their internal teams and
233 Designated representatives of the affected silicon vendors are
236 response team about the handover. The affected silicon vendor must
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| H A D | security-bugs.rst | 20 * **affected kernel version range**: with no version indication, your report
73 affected subsystem's maintainers and Cc: the Linux kernel security team. Do
103 return anything, it means the affected file is part of a wider subsystem, so we
182 the reporter or an affected party for up to 7 calendar days from the start
222 mailing list UNTIL a fix is accepted by the affected code's maintainers
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| /linux/include/linux/ |
| H A D | cpu_pm.h | 28 * CPU notifications apply to a single CPU and must be called on the affected
29 * CPU. They are used to save per-cpu context for affected blocks.
32 * are used to save any global context for affected blocks, and must be called
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| /linux/drivers/net/can/rockchip/ |
| H A D | rockchip_canfd-rx.c | 140 * Not affected if: in rkcanfd_rxstx_filter()
148 /* Not affected if: in rkcanfd_rxstx_filter()
156 /* Not affected if: in rkcanfd_rxstx_filter()
162 /* Not affected if: in rkcanfd_rxstx_filter()
169 /* Affected by Erratum 6 */ in rkcanfd_rxstx_filter()
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| /linux/Documentation/PCI/ |
| H A D | pci-error-recovery.rst | 18 pSeries boxes. A typical action taken is to disconnect the affected device,
22 offered, so that the affected PCI device(s) are reset and put back
24 between the affected device drivers and the PCI controller chip.
31 is reported as soon as possible to all affected device drivers,
133 every driver affected by the error.
181 thus, if one device sleeps/schedules, all devices are affected.
198 DMA), and then calls the mmio_enabled() callback on all affected
378 The platform will call the resume() callback on all affected device
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| /linux/arch/riscv/kernel/ |
| H A D | bugs.c | 49 return sprintf(buf, "Not affected\n"); in cpu_show_ghostwrite()
58 return sprintf(buf, "Not affected\n"); in cpu_show_ghostwrite()
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| /linux/tools/perf/pmu-events/arch/common/common/ |
| H A D | legacy-hardware.json | 14 …"BriefDescription": "Retired instructions. Be careful, these can be affected by various issues, mo…
69 "BriefDescription": "Total cycles; not affected by CPU frequency scaling.",
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| /linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | actions,s500-pinctrl.yaml | 73 List of gpio pin groups affected by the functions specified in
123 List of gpio pin groups affected by the drive-strength property
141 List of gpio pins affected by the bias-pull-* and
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