Searched full:usbphyc (Results 1 – 24 of 24) sorted by relevance
138 struct stm32_usbphyc *usbphyc; member169 static int stm32_usbphyc_regulators_enable(struct stm32_usbphyc *usbphyc) in stm32_usbphyc_regulators_enable() argument173 ret = regulator_enable(usbphyc->vdda1v1); in stm32_usbphyc_regulators_enable()177 ret = regulator_enable(usbphyc->vdda1v8); in stm32_usbphyc_regulators_enable()184 regulator_disable(usbphyc->vdda1v1); in stm32_usbphyc_regulators_enable()189 static int stm32_usbphyc_regulators_disable(struct stm32_usbphyc *usbphyc) in stm32_usbphyc_regulators_disable() argument193 ret = regulator_disable(usbphyc->vdda1v8); in stm32_usbphyc_regulators_disable()197 ret = regulator_disable(usbphyc->vdda1v1); in stm32_usbphyc_regulators_disable()231 static int stm32_usbphyc_pll_init(struct stm32_usbphyc *usbphyc) in stm32_usbphyc_pll_init() argument234 u32 clk_rate = clk_get_rate(usbphyc->clk); in stm32_usbphyc_pll_init()[all …]
7 obj-$(CONFIG_PHY_STM32_USBPHYC) += phy-stm32-usbphyc.o
57 (USBPHYC) and the two 8-bit wide UTMI+ interfaces. First interface is
4 $id: http://devicetree.org/schemas/phy/phy-stm32-usbphyc.yaml#11 The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI16 USBPHYC31 const: st,stm32mp1-usbphyc243 usbphyc: usbphyc@5a006000 {244 compatible = "st,stm32mp1-usbphyc";
129 &usbphyc {
146 &usbphyc {
206 &usbphyc {
187 &usbphyc {
977 clocks = <&usbphyc>, <&rcc USBH>;986 clocks = <&usbphyc>, <&rcc USBH>;1628 usbphyc: usbphyc@5a006000 { label1632 compatible = "st,stm32mp1-usbphyc";
329 &usbphyc {
280 &usbphyc {
311 &usbphyc {
332 &usbphyc {
393 &usbphyc {
383 &usbphyc {
504 &usbphyc {
508 &usbphyc {
388 &usbphyc {
520 &usbphyc {
563 &usbphyc {
403 &usbphyc {
585 &usbphyc {
726 &usbphyc {
1119 &usbphyc {