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/linux/Documentation/translations/zh_CN/arch/loongarch/
H A Dirq-chip-model.rst27 CPU串口（UARTs）中断发送到LIOINTC，而其他所有设备的中断则分别发送到所连接的PCH-PIC/
36 | LIOINTC | <-- | UARTs |
63 CPU串口（UARTs）中断发送到LIOINTC，而其他所有设备的中断则分别发送到所连接的PCH-PIC/
72 | EIOINTC | | LIOINTC | <-- | UARTs |
94 CPU串口 (UARTs) 中断发送到PCH-PIC, 而其他所有设备的中断则分别发送到所连接的PCH_PIC/
113 | UARTs | | Devices | | Devices |
149 CPU串口（UARTs）中断发送到LIOINTC，PCH-MSI中断发送到AVECINTC，而后通过AVECINTC直接
159 | EIOINTC | | AVECINTC | | LIOINTC | <-- | UARTs |
/linux/Documentation/devicetree/bindings/soc/aspeed/
H A Duart-routing.yaml17 the built-in UARTS and physical serial I/O ports.
20 This can be used to enable Host <-> BMC communication via UARTs, e.g. to
24 which owns the system configuration policy, to configure how UARTs and
/linux/Documentation/arch/loongarch/
H A Dirq-chip-model.rst23 to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices
33 | LIOINTC | <-- | UARTs |
60 to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices
70 | EIOINTC | | LIOINTC | <-- | UARTs |
92 go to CPUINTC directly, CPU UARTS interrupts go to PCH-PIC, while all other
112 | UARTs | | Devices | | Devices |
156 to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, PCH-MSI interrupts go
166 | EIOINTC | | AVECINTC | | LIOINTC | <-- | UARTs |
/linux/Documentation/translations/zh_TW/arch/loongarch/
H A Dirq-chip-model.rst27 CPU串口（UARTs）中斷髮送到LIOINTC，而其他所有設備的中斷則分別發送到所連接的PCH-PIC/
36 | LIOINTC | <-- | UARTs |
63 CPU串口（UARTs）中斷髮送到LIOINTC，而其他所有設備的中斷則分別發送到所連接的PCH-PIC/
72 | EIOINTC | | LIOINTC | <-- | UARTs |
/linux/drivers/net/wireless/broadcom/brcm80211/include/
H A Dchipcommon.h156 /* UARTs */
233 #define CC_CAP_UARTS_MASK 0x00000003 /* Number of UARTs */
235 #define CC_CAP_UCLKSEL 0x00000018 /* UARTs clock select */
236 /* UARTs are driven by internal divided clock */
238 #define CC_CAP_UARTGPIO 0x00000020 /* UARTs own GPIOs 15:12 */
/linux/drivers/tty/serial/
H A DKconfig136 This enables the driver for the on-chip UARTs of the Atmel
169 Say Y here if you wish to have the internal AT91 UARTs
172 64). This is necessary if you also want other UARTs, such as
173 external 8250/16C550 compatible UARTs.
187 This enables the driver for the on-chip UARTs of the Amlogic
207 This enables the driver for the on-chip UARTs of the Cirrus
225 Support for the on-chip UARTs on the Samsung
261 Support for the on-chip UARTs on the NVIDIA Tegra series SOCs
692 Those are UARTs completely different from the Standard UARTs on the
766 UARTs.
[all …]
/linux/drivers/tty/serial/8250/
H A D8250_pxa.c3 * drivers/tty/serial/8250/8250_pxa.c -- driver for PXA on-board UARTS
169 MODULE_DESCRIPTION("driver for PXA on-board UARTS");
/linux/arch/parisc/include/asm/
H A Dserial.h6 * This is used for 16550-compatible UARTs
/linux/include/uapi/linux/
H A Dserial_core.h27 #define PORT_XR17V35X 24 /* Exar XR17V35x UARTs */
143 /* Altera UARTs */
H A Dserial_reg.h98 some Freescale UARTs) */
239 * The Intel XScale on-chip UARTs define these bits
348 * Extra serial register definitions for the internal UARTs
/linux/drivers/char/mwave/
H A DMakefile12 # To have the mwave driver disable other uarts if necessary
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dbrcm,bcm7120-l2-intc.yaml24 controller, in particular for UARTs
116 typically UARTs. Setting these bits will make their respective interrupt
/linux/arch/mips/include/asm/mach-rc32434/
H A Dirq.h17 /* 16550 UARTs */
/linux/include/linux/ssb/
H A Dssb_driver_extif.h11 * support external devices such as UARTs and the BCM2019 Bluetooth
13 * The external interface core also contains 2 on-chip 16550 UARTs, clock
H A Dssb_driver_chipcommon.h8 * jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer,
26 #define SSB_CHIPCO_CAP_NRUART 0x00000003 /* # of UARTs */
29 #define SSB_CHIPCO_CAP_UARTCLK_INT 0x00000008 /* UARTs are driven by internal divided clock */
30 #define SSB_CHIPCO_CAP_UARTGPIO 0x00000020 /* UARTs on GPIO 15-12 */
/linux/arch/x86/kernel/
H A Djailhouse.c183 * platform UARTs since setup data version 2. in jailhouse_serial_workaround()
185 * In case of version 1, we don't know which UARTs belong Linux. In in jailhouse_serial_workaround()
/linux/arch/arm/mach-s3c/
H A Ddev-uart-s3c64xx.c25 /* 64xx uarts are closer together */
H A Dpm-common.c43 * restore the UARTs state yet
/linux/drivers/tty/serial/jsm/
H A Djsm_driver.c131 * 2 I/O Mapped UARTs and Status in jsm_probe_one()
133 * 4 Memory Mapped UARTs and Status in jsm_probe_one()
/linux/drivers/platform/x86/
H A Dserdev_helpers.h12 * create a serdev-controller device for these UARTs instead of a /dev/ttyS#.
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dstarfive,jh7110-sys-pinctrl.yaml16 includes a number of other UARTs, I2Cs, SPIs, PWMs etc.
/linux/Documentation/devicetree/bindings/serial/
H A Dqcom,msm-uartdm.yaml20 Note:: Aliases may be defined to ensure the correct ordering of the UARTs.
H A Dserial.yaml14 This document lists a set of generic properties for describing UARTs in a
/linux/arch/sparc/include/asm/
H A Dns87303.h57 /* Tape UARTs and Parallel Port Config Register (TUP) bits */
/linux/Documentation/driver-api/serial/
H A Dserial-iso7816.rst14 Some CPUs/UARTs (e.g., Microchip AT91) contain a built-in mode capable of

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