/linux/Documentation/devicetree/bindings/interrupt-controller/ |
H A D | al,alpine-msix.yaml | 27 al,msi-num-spis: 28 description: number of SPIs assigned to the MSI frame, relative to SPI0 36 - al,msi-num-spis 48 al,msi-num-spis = <160>;
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H A D | arm,gic.yaml | 84 2 = high-to-low edge triggered (invalid for SPIs) 86 8 = active low level-sensitive (invalid for SPIs). 174 arm,msi-num-spis: 176 this property should contain the number of SPIs assigned to the
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H A D | socionext,synquacer-exiu.yaml | 15 level-high type GICv3 SPIs.
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H A D | ti,omap4-wugen-mpu.yaml | 21 - Only SPIs can use the WUGEN as an interrupt parent. SGIs and PPIs are
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H A D | nvidia,tegra20-ictlr.yaml | 24 - Only SPIs can use the ictlr as an interrupt parent. SGIs and PPIs
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/linux/Documentation/devicetree/bindings/pinctrl/ |
H A D | mediatek,mt76x8-pinctrl.yaml | 42 spi, spi cs1, spis, sw_r, uart0, uart1, uart2, utif, wdt, 83 spi cs1, spis, uart0, uart1, uart2, wdt, wled_an, 266 enum: [spis] 343 const: spis 347 enum: [spis] 393 p3led_kn, p4led_an, p4led_kn, pwm0, pwm1, sdmode, spis]
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H A D | img,pistachio-pinctrl.txt | 64 mfio11 spis 65 mfio12 spis 66 mfio13 spis 67 mfio14 spis
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H A D | starfive,jh7110-sys-pinctrl.yaml | 16 includes a number of other UARTs, I2Cs, SPIs, PWMs etc.
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/linux/net/ipv6/netfilter/ |
H A D | ip6t_ah.c | 65 spi_match(ahinfo->spis[0], ahinfo->spis[1], in ah_mt6() 77 return spi_match(ahinfo->spis[0], ahinfo->spis[1], in ah_mt6()
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/linux/arch/arm64/kvm/vgic/ |
H A D | vgic-init.c | 183 * @nr_spis: number of spis, frozen by caller 191 dist->spis = kcalloc(nr_spis, sizeof(struct vgic_irq), GFP_KERNEL_ACCOUNT); in kvm_vgic_dist_init() 192 if (!dist->spis) in kvm_vgic_dist_init() 204 struct vgic_irq *irq = &dist->spis[i]; in kvm_vgic_dist_init() 222 kfree(dist->spis); in kvm_vgic_dist_init() 223 dist->spis = NULL; in kvm_vgic_dist_init() 367 * - the number of spis 389 /* freeze the number of spis */ in vgic_init() 428 kfree(dist->spis); in kvm_vgic_dist_destroy() 429 dist->spis = NULL; in kvm_vgic_dist_destroy()
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H A D | vgic-irqfd.c | 125 * Injecting SPIs is always possible in atomic context in kvm_arch_set_irq_inatomic()
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/linux/arch/arm64/boot/dts/broadcom/northstar2/ |
H A D | ns2.dtsi | 373 arm,msi-num-spis = <16>; 381 arm,msi-num-spis = <16>; 389 arm,msi-num-spis = <16>; 397 arm,msi-num-spis = <16>; 405 arm,msi-num-spis = <16>; 413 arm,msi-num-spis = <16>; 421 arm,msi-num-spis = <16>; 429 arm,msi-num-spis = <16>;
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/linux/net/ipv4/netfilter/ |
H A D | ipt_ah.c | 50 return spi_match(ahinfo->spis[0], ahinfo->spis[1], in ah_mt()
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/linux/net/netfilter/ |
H A D | xt_esp.c | 56 return spi_match(espinfo->spis[0], espinfo->spis[1], ntohl(eh->spi), in esp_mt()
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H A D | xt_ipcomp.c | 60 return spi_match(compinfo->spis[0], compinfo->spis[1], in comp_mt()
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/linux/drivers/pinctrl/mediatek/ |
H A D | pinctrl-mt76x8.c | 95 FUNC("spis utif", 2, 14, 4), 96 FUNC("spis", 0, 14, 4), 193 GRP_G("spis", spis_grp, MT76X8_GPIO_MODE_MASK,
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/linux/arch/arm64/boot/dts/marvell/ |
H A D | armada-ap80x.dtsi | 115 arm,msi-num-spis = <32>; 122 arm,msi-num-spis = <32>; 129 arm,msi-num-spis = <32>; 136 arm,msi-num-spis = <32>;
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/linux/Documentation/devicetree/bindings/arm/ |
H A D | pmu.yaml | 89 When using SPIs, specifies a list of phandles to CPU 91 the SPIs listed in the interrupts property.
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/linux/include/uapi/linux/netfilter_ipv4/ |
H A D | ipt_ah.h | 8 __u32 spis[2]; /* Security Parameter Index */ member
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/linux/include/uapi/linux/netfilter/ |
H A D | xt_esp.h | 8 __u32 spis[2]; /* Security Parameter Index */ member
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H A D | xt_ipcomp.h | 8 __u32 spis[2]; /* Security Parameter Index */ member
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/linux/include/uapi/linux/netfilter_ipv6/ |
H A D | ip6t_ah.h | 8 __u32 spis[2]; /* Security Parameter Index */ member
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/linux/include/kvm/ |
H A D | arm_vgic.h | 127 * SPIs and LPIs: The VCPU whose ap_list 277 struct vgic_irq *spis; member 433 * Setup a default flat gsi routing table mapping all SPIs
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/linux/Documentation/devicetree/bindings/timer/ |
H A D | arm,arch_timer_mmio.yaml | 17 The memory mapped timer is attached to a GIC to deliver its interrupts via SPIs.
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H A D | arm,arch_timer.yaml | 19 to deliver its interrupts via SPIs.
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