| /linux/drivers/bcma/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
16 # Support for Block-I/O. SELECT this from the driver that needs it.
26 bool "Support for BCMA on PCI-host bus"
46 BCMA bus may have many versions of PCIe core. This driver
48 1) PCIe core working in clientmode
49 2) PCIe Gen 2 clientmode core
51 In general PCIe (Gen 2) clientmode core is required on PCIe
54 This driver is also prerequisite for a hostmode PCIe core
67 Driver for the Broadcom MIPS core attached to Broadcom specific
78 bool "ChipCommon-attached serial flash support"
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|
| /linux/Documentation/devicetree/bindings/pci/ |
| H A D | baikal,bt1-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/baikal,bt1-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Baikal-T1 PCIe Root Port Controller
10 - Serge Semin <fancer.lancer@gmail.com>
13 Embedded into Baikal-T1 SoC Root Complex controller with a single port
14 activated. It's based on the DWC RC PCIe v4.60a IP-core, which is configured
18 performed by software. There four in- and four outbound iATU regions
19 which can be used to emit all required TLP types on the PCIe bus.
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| H A D | starfive,jh7110-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/starfive,jh7110-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 PCIe host controller
10 - Kevin Xie <kevin.xie@starfivetech.com>
13 - $ref: plda,xpressrich3-axi-common.yaml#
17 const: starfive,jh7110-pcie
23 reg-names:
28 - description: NOC bus clock
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|
| H A D | snps,dw-pcie-ep.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare PCIe endpoint interface
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
14 Synopsys DesignWare PCIe host controller endpoint
16 # Please create a separate DT-schema for your DWC PCIe Endpoint controller
17 # and make sure it's assigned with the vendor-specific compatible string.
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| H A D | snps,dw-pcie.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare PCIe interface
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
14 Synopsys DesignWare PCIe host controller
16 # Please create a separate DT-schema for your DWC PCIe Root Port controller
17 # and make sure it's assigned with the vendor-specific compatible string.
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| H A D | snps,dw-pcie-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DWC PCIe RP/EP controller
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
14 Generic Synopsys DesignWare PCIe Root Port and Endpoint controller
22 DWC PCIe CSR space is normally accessed over the dedicated Data Bus
23 Interface - DBI. In accordance with the reference manual the register
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|
| /linux/Documentation/devicetree/bindings/net/wireless/ |
| H A D | qcom,ath12k-wsi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/wireless/qcom,ath12k-wsi.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Qualcomm Technologies ath12k wireless devices (PCIe) with WSI interface
11 - Jeff Johnson <jjohnson@kernel.org>
14 Qualcomm Technologies IEEE 802.11be PCIe devices with WSI interface.
23 multiple WSI-supported devices together, forming a WSI group.
28 +-------+ +-------+ +-------+
31 +----->| wsi |------->| wsi |------->| wsi |-----+
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| /linux/Documentation/devicetree/bindings/phy/ |
| H A D | phy-miphy365x.txt | 5 for SATA and PCIe.
8 - compatible : Should be "st,miphy365x-phy"
9 - st,syscfg : Phandle / integer array property. Phandle of sysconfig group
11 an entry for each port sub-node, specifying the control
14 Required nodes : A sub-node is required for each channel the controller
16 'reg' and 'reg-names' properties are used inside these
21 - #phy-cells : Should be 1 (See second example)
23 - PHY_TYPE_SATA
24 - PHY_TYPE_PCI
25 - reg : Address and length of register sets for each device in
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| /linux/Documentation/devicetree/bindings/arm/bcm/ |
| H A D | brcm,hr2.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 A9 ARM CPUs, DDR2/DDR3 memory, PCIe GEN-2, USB 2.0 and USB 3.0, serial and NAND
13 flash and a PCIe attached integrated switching engine.
16 - Florian Fainelli <f.fainelli@gmail.com>
23 - enum:
24 - ubnt,unifi-switch8
25 - const: brcm,bcm53342
26 - const: brcm,hr2
|
| /linux/Documentation/devicetree/bindings/net/bluetooth/ |
| H A D | brcm,bcm4377-bluetooth.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/bluetooth/brcm,bcm4377-bluetooth.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom BCM4377 family PCIe Bluetooth Chips
10 - Sven Peter <sven@svenpeter.dev>
13 This binding describes Broadcom BCM4377 family PCIe-attached bluetooth chips
14 usually found in Apple machines. The Wi-Fi part of the chip is described in
15 bindings/net/wireless/brcm,bcm4329-fmac.yaml.
18 - $ref: bluetooth-controller.yaml#
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|
| /linux/Documentation/driver-api/ |
| H A D | men-chameleon-bus.rst | 31 ----------------------
38 -----------------------------------------
40 The current implementation is limited to PCI and PCIe based carrier devices
44 - Multi-resource MCB devices like the VME Controller or M-Module carrier.
45 - MCB devices that need another MCB device, like SRAM for a DMA Controller's
47 - A per-carrier IRQ domain for carrier devices that have one (or more) IRQs
48 per MCB device like PCIe based carriers with MSI or MSI-X support.
55 - The MEN Chameleon Bus itself,
56 - drivers for MCB Carrier Devices and
57 - the parser for the Chameleon table.
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|
| H A D | xillybus.rst | 10 - Introduction
11 -- Background
12 -- Xillybus Overview
14 - Usage
15 -- User interface
16 -- Synchronization
17 -- Seekable pipes
19 - Internals
20 -- Source code organization
21 -- Pipe attributes
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| /linux/Documentation/networking/ |
| H A D | representors.rst | 1 .. SPDX-License-Identifier: GPL-2.0
9 used to control internal switching on SmartNICs. For the closely-related port
10 representors on physical (multi-port) switches, see
14 ----------
16 Since the mid-2010s, network cards have started offering more complex
17 virtualisation capabilities than the legacy SR-IOV approach (with its simple
18 MAC/VLAN-based switching model) can support. This led to a desire to offload
19 software-defined networks (such as OpenVSwitch) to these NICs to specify the
24 virtual switches and IOV devices. Just as each physical port of a Linux-
42 -----------
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|
| /linux/Documentation/PCI/endpoint/ |
| H A D | pci-ntb-howto.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 PCI Non-Transparent Bridge (NTB) Endpoint Function (EPF) User Guide
9 This document is a guide to help users use pci-epf-ntb function driver
13 Documentation/PCI/endpoint/pci-ntb-function.rst
19 ---------------------------
27 2900000.pcie-ep 2910000.pcie-ep
32 2900000.pcie-ep 2910000.pcie-ep
36 -------------------------
40 # ls /sys/bus/pci-epf/drivers
49 Creating pci-epf-ntb Device
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|
| /linux/drivers/scsi/mpt3sas/mpi/ |
| H A D | mpi2_pci.h | 2 * Copyright 2000-2020 Broadcom Inc. All rights reserved.
6 * Title: MPI PCIe Attached Devices structures and definitions.
17 * ---------------
20 * -------- -------- ------------------------------------------------------
21 * 03-16-15 02.00.00 Initial version.
22 * 02-17-16 02.00.01 Removed AHCI support.
24 * 07-01-16 02.00.02 Added MPI26_NVME_FLAGS_FORCE_ADMIN_ERR_RESP to
26 * 07-22-18 02.00.03 Updted flags field for NVME Encapsulated req
27 * 12-17-18 02.00.04 Added MPI26_PCIE_DEVINFO_SCSI
29 * --------------------------------------------------------------------------
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|
| /linux/drivers/usb/dwc3/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
22 Select this if you have ULPI type PHY attached to your DWC3
78 tristate "PCIe-based Platforms"
82 If you're using the DesignWare Core IP with a PCIe (but not HAPS
86 tristate "Synopsys PCIe-based HAPS Platforms"
90 If you're using the DesignWare Core IP with a Synopsys PCIe HAPS
189 or dual-role mode.
|
| /linux/arch/arm64/boot/dts/freescale/ |
| H A D | imx8mp-venice-gw82xx.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/leds/common.h>
8 #include <dt-bindings/phy/phy-imx8-pcie.h>
17 led-controller {
18 compatible = "gpio-leds";
19 pinctrl-names = "default";
20 pinctrl-0 = <&pinctrl_gpio_leds>;
22 led-0 {
26 default-state = "on";
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|
| H A D | imx8mp-venice-gw71xx.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/leds/common.h>
8 #include <dt-bindings/phy/phy-imx8-pcie.h>
12 compatible = "gpio-usb-b-connector", "usb-b-connector";
13 pinctrl-names = "default";
14 pinctrl-0 = <&pinctrl_usbcon1>;
16 label = "Type-C";
17 id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
21 remote-endpoint = <&usb3_dwc>;
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|
| /linux/Documentation/driver-api/cxl/devices/ |
| H A D | device-types.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 covers some basic background on device types and on-device resources used by the platform and OS
20 ------
21 The basic interaction protocol, similar to PCIe configuration mechanisms.
30 ---------
36 ---------
45 Type-1
46 ------
48 A Type-1 CXL device:
52 * Allows Device-to-Host coherence and Host-to-Device snoops.
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|
| /linux/arch/powerpc/boot/dts/fsl/ |
| H A D | t104xd4rdb.dtsi | 36 reserved-memory {
37 #address-cells = <2>;
38 #size-cells = <2>;
41 bman_fbpr: bman-fbpr {
45 qman_fqd: qman-fqd {
49 qman_pfdr: qman-pfdr {
62 #address-cells = <1>;
63 #size-cells = <1>;
64 compatible = "cfi-flash";
66 bank-width = <2>;
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|
| /linux/Documentation/ABI/testing/ |
| H A D | sysfs-bus-pci | 4 Contact: linux-pci@vger.kernel.org
15 (Note: kernels before 2.6.28 may require echo -n).
20 Contact: linux-pci@vger.kernel.org
31 (Note: kernels before 2.6.28 may require echo -n).
36 Contact: linux-pci@vger.kernel.org
55 Contact: Chris Wright <chrisw@sous-sol.org>
72 Contact: Linux PCI developers <linux-pci@vger.kernel.org>
74 Writing a non-zero value to this attribute will
76 re-discover previously removed devices.
80 Contact: Linux PCI developers <linux-pci@vger.kernel.org>
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|
| /linux/Documentation/devicetree/bindings/bus/ |
| H A D | brcm,bus-axi.txt | 5 - compatible : brcm,bus-axi
7 - reg : iomem address range of chipcommon core
13 them manually through device tree. Use an interrupt-map to specify the
17 The top-level axi bus may contain children representing attached cores
25 compatible = "brcm,bus-axi";
28 #address-cells = <1>;
29 #size-cells = <1>;
30 #interrupt-cells = <1>;
31 interrupt-map-mask = <0x000fffff 0xffff>;
32 interrupt-map =
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|
| /linux/drivers/pci/controller/mobiveil/ |
| H A D | pcie-mobiveil-host.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Mobiveil PCIe Host controller
6 * Copyright 2019-2020 NXP
15 #include <linux/irqchip/irq-msi-lib.h>
26 #include "pcie-mobiveil.h"
36 * attached to RC in mobiveil_pcie_valid_device()
38 if ((bus->primary == to_pci_host_bridge(bus->bridge)->busnr) && (PCI_SLOT(devfn) > 0)) in mobiveil_pcie_valid_device()
45 * mobiveil_pcie_map_bus - routine to get the configuration base of either
51 struct mobiveil_pcie *pcie = bus->sysdata; in mobiveil_pcie_map_bus() local
52 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_map_bus()
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|
| /linux/drivers/pci/controller/cadence/ |
| H A D | pcie-cadence.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 // Cadence PCIe controller driver.
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
11 #include <linux/pci-epf.h>
117 (((aperture) - 2) << ((bar) * 8))
150 /* Region r Outbound AXI to PCIe Address Translation Register 0 */
155 (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK)
163 /* Region r Outbound AXI to PCIe Address Translation Register 1 */
167 /* Region r Outbound PCIe Descriptor Register 0 */
183 /* Region r Outbound PCIe Descriptor Register 1 */
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| /linux/Documentation/devicetree/bindings/net/dsa/ |
| H A D | mscc,ocelot.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vladimir Oltean <vladimir.oltean@nxp.com>
11 - Claudiu Manoil <claudiu.manoil@nxp.com>
12 - Alexandre Belloni <alexandre.belloni@bootlin.com>
13 - UNGLinuxDriver@microchip.com
16 There are multiple switches which are either part of the Ocelot-1 family, or
19 SPI or PCIe. The present DSA binding shall be used when the host controlling
21 (which is attached to an Ethernet port of the host), rather than through
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|