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/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx7ulp.dtsi300 pcc3: clock-controller@40b30000 { label
301 compatible = "fsl,imx7ulp-pcc3";
333 clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>,
336 assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
346 clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>,
349 assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
359 clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
361 assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
371 clocks = <&pcc3 IMX7ULP_CLK_LPUART7>;
373 assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART7>;
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dimx8ulp-pcc-clock.yaml21 - fsl,imx8ulp-pcc3
46 compatible = "fsl,imx8ulp-pcc3";
H A Dimx7ulp-pcc-clock.yaml24 A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
41 - fsl,imx7ulp-pcc3
H A Dimx7ulp-scg-clock.yaml24 A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
/linux/include/dt-bindings/reset/
H A Dimx8ulp-pcc-reset.h9 /* PCC3 */
/linux/include/dt-bindings/clock/
H A Dimx7ulp-clock.h94 /* PCC3 */
H A Dimx8ulp-clock.h119 /* PCC3 */
/linux/drivers/clk/imx/
H A Dclk-imx7ulp.c197 /* PCC3 */ in imx7ulp_clk_pcc3_init()
228 CLK_OF_DECLARE(imx7ulp_clk_pcc3, "fsl,imx7ulp-pcc3", imx7ulp_clk_pcc3_init);
H A Dclk-imx8ulp.c327 /* PCC3 */ in imx8ulp_clk_pcc3_init()
390 /* register the pcc3 reset controller */ in imx8ulp_clk_pcc3_init()
549 { .compatible = "fsl,imx8ulp-pcc3", .data = imx8ulp_clk_pcc3_init },
/linux/drivers/pinctrl/tegra/
H A Dpinctrl-tegra30.c519 PINCTRL_PIN(TEGRA_PIN_SDMMC4_RST_N_PCC3, "SDMMC4_RST_N PCC3"),