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/linux/drivers/pci/msi/
H A Dapi.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCI MSI/MSI-X — Exported APIs for device drivers
5 * Copyright (C) 2003-2004 Intel
14 #include "msi.h"
17 * pci_enable_msi() - Enable MSI interrupt mode on device
20 * Legacy device driver API to enable MSI interrupts mode on device and
22 * Linux IRQ will be saved at @dev->irq. The driver must invoke
40 * pci_disable_msi() - Disable MSI interrupt mode on device
43 * Legacy device driver API to disable MSI interrupt mode on device,
45 * The PCI device Linux IRQ (@dev->irq) is restored to its default
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H A Dmsi.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCI Message Signaled Interrupt (MSI)
5 * Copyright (C) 2003-2004 Intel
16 #include "msi.h"
21 * pci_msi_supported - check whether MSI may be enabled on a device
22 * @dev: pointer to the pci_dev data structure of MSI device function
26 * to determine if MSI/-X are supported for the device. If MSI/-X is
33 /* MSI must be globally enabled and supported by the device */ in pci_msi_supported()
37 if (!dev || dev->no_msi) in pci_msi_supported()
49 * Any bridge which does NOT route MSI transactions from its in pci_msi_supported()
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/linux/arch/sparc/kernel/
H A Dpci_msi.c1 // SPDX-License-Identifier: GPL-2.0
2 /* pci_msi.c: Sparc64 MSI support common layer.
18 struct pci_pbm_info *pbm = msiq_cookie->pbm; in sparc64_msiq_interrupt()
19 unsigned long msiqid = msiq_cookie->msiqid; in sparc64_msiq_interrupt()
24 ops = pbm->msi_ops; in sparc64_msiq_interrupt()
26 err = ops->get_head(pbm, msiqid, &head); in sparc64_msiq_interrupt()
32 unsigned long msi; in sparc64_msiq_interrupt() local
34 err = ops->dequeue_msi(pbm, msiqid, &head, &msi); in sparc64_msiq_interrupt()
38 irq = pbm->msi_irq_table[msi - pbm->msi_first]; in sparc64_msiq_interrupt()
49 err = ops->set_head(pbm, msiqid, head); in sparc64_msiq_interrupt()
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/linux/Documentation/translations/zh_CN/PCI/
H A Dmsi-howto.rst1 .. SPDX-License-Identifier: GPL-2.0
3 .. include:: ../disclaimer-zh_CN.rst
5 :Original: Documentation/PCI/msi-howto.rst
26 本指南介绍了消息标记中断（MSI）的基本知识，使用MSI相对于传统中断机制的优势，如何
27 改变你的驱动程序以使用MSI或MSI-X，以及在设备不支持MSI时可以尝试的一些基本诊断方法。
36 MSI-X功能也随着PCI 3.0被引入。它比MSI支持每个设备更多的中断，并允许独立配置中断。
38 设备可以同时支持MSI和MSI-X，但一次只能启用一个。
50 之前，中断就已经到达了（这在PCI-PCI桥后面的设备中变得更有可能）。为了确保所有的数
65 PCI设备被初始化为使用基于引脚的中断。设备驱动程序必须将设备设置为使用MSI或MSI-X。
70 -------------------
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/linux/Documentation/PCI/endpoint/
H A Dpci-ntb-function.rst1 .. SPDX-License-Identifier: GPL-2.0
9 PCI Non-Transparent Bridges (NTB) allow two host systems to communicate
26 .. code-block:: text
28 +-------------+ +-------------+
32 +------^------+ +------^------+
35 +---------|-------------------------------------------------|---------+
36 | +------v------+ +------v------+ |
40 | | <-----------------------------------> | |
45 | +-------------+ +-------------+ |
46 +---------------------------------------------------------------------+
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H A Dpci-test-function.rst1 .. SPDX-License-Identifier: GPL-2.0
11 However with the addition of EP-core in linux kernel, it is possible
45 Bit 1 raise MSI IRQ
46 Bit 2 raise MSI-X IRQ
82 This register contains the interrupt type (Legacy/MSI) triggered
83 for the READ/WRITE/COPY and raise IRQ (Legacy/MSI) commands.
89 MSI 1
90 MSI-X 2
101 MSI [1 .. 32]
102 MSI-X [1 .. 2048]
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dbrcm,bcm2712-msix.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm2712-msix.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom bcm2712 MSI-X Interrupt Peripheral support
10 - Stanimir Varbanov <svarbanov@suse.de>
15 external MSI-X controller for PCIe root complex.
18 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
22 const: brcm,bcm2712-mip
26 - description: Base register address
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H A Dmarvell,mpic.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/marvell,mpic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell Armada 370, 375, 38x, 39x, XP Interrupt Controller
10 - Marek Behún <kabel@kernel.org>
13 The top-level interrupt controller on Marvell Armada 370 and XP. On these
14 platforms it also provides inter-processor interrupts.
16 On Marvell Armada 375, 38x and 39x this controller is wired under ARM GIC.
18 Provides MSI handling for the PCIe controllers.
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H A Darm,gic.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
22 - $ref: /schemas/interrupt-controller.yaml#
27 - items:
28 - enum:
29 - arm,arm11mp-gic
30 - arm,cortex-a15-gic
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/linux/arch/powerpc/sysdev/
H A Dmpic_u3msi.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright 2006-2007, Michael Ellerman, IBM Corporation.
9 #include <linux/msi.h>
12 #include <asm/ppc-pci.h>
39 .name = "MPIC-U3MSI",
66 for (bus = pdev->bus; bus && bus->self; bus = bus->parent) { in find_ht_magic_addr()
67 pos = pci_find_ht_capability(bus->self, HT_CAPTYPE_MSI_MAPPING); in find_ht_magic_addr()
69 return read_ht_magic_addr(bus->self, pos); in find_ht_magic_addr()
77 struct pci_controller *hose = pci_bus_to_host(pdev->bus); in find_u4_magic_addr()
82 * the MSI number and that triggers the right interrupt, but in find_u4_magic_addr()
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H A Dmsi_bitmap.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2006-2008, Michael Ellerman, IBM Corporation.
20 spin_lock_irqsave(&bmp->lock, flags); in msi_bitmap_alloc_hwirqs()
22 offset = bitmap_find_next_zero_area(bmp->bitmap, bmp->irq_count, 0, in msi_bitmap_alloc_hwirqs()
23 num, (1 << order) - 1); in msi_bitmap_alloc_hwirqs()
24 if (offset > bmp->irq_count) in msi_bitmap_alloc_hwirqs()
27 bitmap_set(bmp->bitmap, offset, num); in msi_bitmap_alloc_hwirqs()
28 spin_unlock_irqrestore(&bmp->lock, flags); in msi_bitmap_alloc_hwirqs()
30 pr_debug("msi_bitmap: allocated 0x%x at offset 0x%x\n", num, offset); in msi_bitmap_alloc_hwirqs()
34 spin_unlock_irqrestore(&bmp->lock, flags); in msi_bitmap_alloc_hwirqs()
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/linux/drivers/pci/controller/mobiveil/
H A Dpcie-mobiveil-host.c1 // SPDX-License-Identifier: GPL-2.0
6 * Copyright 2019-2020 NXP
15 #include <linux/irqchip/irq-msi-lib.h>
20 #include <linux/msi.h>
26 #include "pcie-mobiveil.h"
38 if ((bus->primary == to_pci_host_bridge(bus->bridge)->busnr) && (PCI_SLOT(devfn) > 0)) in mobiveil_pcie_valid_device()
45 * mobiveil_pcie_map_bus - routine to get the configuration base of either
51 struct mobiveil_pcie *pcie = bus->sysdata; in mobiveil_pcie_map_bus()
52 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_map_bus()
60 return pcie->csr_axi_slave_base + where; in mobiveil_pcie_map_bus()
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/linux/drivers/xen/xen-pciback/
H A Dpciback_ops.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCI Backend Operations - respond to PCI requests from Frontend
35 if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) in xen_pcibk_control_isr()
39 dev_data->enable_intx = 0; in xen_pcibk_control_isr()
40 dev_data->ack_intr = 0; in xen_pcibk_control_isr()
42 enable = dev_data->enable_intx; in xen_pcibk_control_isr()
45 if (!enable && !dev_data->isr_on) in xen_pcibk_control_isr()
49 * b/c when device transitions to MSI, the dev->irq is in xen_pcibk_control_isr()
50 * overwritten with the MSI vector. in xen_pcibk_control_isr()
53 dev_data->irq = dev->irq; in xen_pcibk_control_isr()
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/linux/arch/powerpc/platforms/pasemi/
H A Dmsi.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Copyright 2006-2007, Michael Ellerman, IBM Corporation.
13 #include <linux/msi.h>
16 #include <asm/ppc-pci.h>
23 * needs more than 32 MSI's down the road we'll have to rethink this,
36 pr_debug("mpic_pasemi_msi_mask_irq %d\n", data->irq); in mpic_pasemi_msi_mask_irq()
43 pr_debug("mpic_pasemi_msi_unmask_irq %d\n", data->irq); in mpic_pasemi_msi_unmask_irq()
55 .name = "PASEMI-MSI",
65 msi_for_each_desc(entry, &pdev->dev, MSI_DESC_ASSOCIATED) { in pasemi_msi_teardown_msi_irqs()
66 hwirq = virq_to_hw(entry->irq); in pasemi_msi_teardown_msi_irqs()
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/linux/drivers/irqchip/
H A Dirq-bcm2712-mip.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/msi.h>
14 #include <linux/irqchip/irq-msi-lib.h>
30 * struct mip_priv - MSI-X interrupt controller data
33 * @msg_addr: PCIe MSI-X address
34 * @msi_base: MSI base
36 * @msi_offset: MSI offset
57 msg->address_hi = upper_32_bits(mip->msg_addr); in mip_compose_msi_msg()
58 msg->address_lo = lower_32_bits(mip->msg_addr); in mip_compose_msi_msg()
59 msg->data = d->hwirq; in mip_compose_msi_msg()
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/linux/drivers/platform/x86/
H A Dmsi-wmi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * MSI WMI hotkeys
7 * Most stuff taken over from hp-wmi
14 #include <linux/input/sparse-keymap.h>
22 MODULE_DESCRIPTION("MSI laptop WMI hotkeys driver");
25 #define DRV_NAME "msi-wmi"
27 #define MSIWMI_BIOS_GUID "551A1F84-FBDD-4125-91DB-3EA8F44F1D45"
28 #define MSIWMI_MSI_EVENT_GUID "B6F3EEF2-3D2F-49DC-9DE3-85BCE18C62F2"
29 #define MSIWMI_WIND_EVENT_GUID "5B3CC38A-40D9-7245-8AE6-1145B751BE3F"
36 /* Generic MSI keys (not present on MSI Wind) */
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/linux/Documentation/misc-devices/
H A Dpci-endpoint-test.rst1 .. SPDX-License-Identifier: GPL-2.0
17 #) raise MSI IRQ
18 #) raise MSI-X IRQ
23 This misc driver creates /dev/pci-endpoint-test.<num> for every
28 -----
36 Tests message signalled interrupts. The MSI number
39 Tests message signalled interrupts. The MSI-X number
43 should be passed as argument (0: Legacy, 1:MSI, 2:MSI-X).
56 .. [1] Documentation/PCI/endpoint/function/binding/pci-test.rst
/linux/arch/mips/pci/
H A Dmsi-octeon.c6 * Copyright (C) 2005-2009, 2010 Cavium Networks
10 #include <linux/msi.h>
15 #include <asm/octeon/cvmx-npi-defs.h>
16 #include <asm/octeon/cvmx-pci-defs.h>
17 #include <asm/octeon/cvmx-npei-defs.h>
18 #include <asm/octeon/cvmx-sli-defs.h>
19 #include <asm/octeon/cvmx-pexp-defs.h>
20 #include <asm/octeon/pci-octeon.h>
23 * Each bit in msi_free_irq_bitmask represents a MSI interrupt that is
31 * is used so we can disable all of the MSI interrupts when a device
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/linux/Documentation/networking/device_drivers/ethernet/neterion/
H A Ds2io.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Neterion's (Formerly S2io) Xframe I/II PCI-X 10GbE driver
7 Release notes for Neterion's (Formerly S2io) Xframe I/II PCI-X 10GbE driver.
10 - 1. Introduction
11 - 2. Identifying the adapter/interface
12 - 3. Features supported
13 - 4. Command line parameters
14 - 5. Performance suggestions
15 - 6. Available Downloads
20 This Linux driver supports Neterion's Xframe I PCI-X 1.0 and
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/linux/drivers/pci/controller/
H A Dpcie-xilinx-dma-pl.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/irqchip/irq-msi-lib.h>
14 #include <linux/msi.h>
19 #include "pcie-xilinx-common.h"
36 #define IMR(x) BIT(XILINX_PCIE_INTR_ ##x) argument
47 IMR(MSI) | \
77 /* Number of MSI IRQs */
86 * struct xilinx_pl_dma_variant - PL DMA PCIe variant information
102 * struct pl_dma_pcie - PCIe port information
112 * @msi: MSI information
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/linux/drivers/misc/vmw_vmci/
H A Dvmci_guest.c1 // SPDX-License-Identifier: GPL-2.0-only
43 MODULE_PARM_DESC(disable_msi, "Disable MSI use in driver - (default=0)");
47 MODULE_PARM_DESC(disable_msix, "Disable MSI-X use in driver - (default=0)");
104 if (dev->mmio_base != NULL) in vmci_read_reg()
105 return readl(dev->mmio_base + reg); in vmci_read_reg()
106 return ioread32(dev->iobase + reg); in vmci_read_reg()
111 if (dev->mmio_base != NULL) in vmci_write_reg()
112 writel(val, dev->mmio_base + reg); in vmci_write_reg()
114 iowrite32(val, dev->iobase + reg); in vmci_write_reg()
120 if (vmci_dev->mmio_base == NULL) in vmci_read_data()
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/linux/Documentation/PCI/
H A Dpci.rst1 .. SPDX-License-Identifier: GPL-2.0
7 :Authors: - Martin Mares <mj@ucw.cz>
8 - Grant Grundler <grundler@parisc-linux.org>
11 Since each CPU architecture implements different chip-sets and PCI devices
18 by Jonathan Corbet, Alessandro Rubini, and Greg Kroah-Hartman.
26 "Linux PCI" <linux-pci@atrey.karlin.mff.cuni.cz> mailing list.
38 supporting hot-pluggable PCI, CardBus, and Express-Card in a single driver].
45 - Enable the device
46 - Request MMIO/IOP resources
47 - Set the DMA mask size (for both coherent and streaming DMA)
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/linux/include/linux/
H A Dpci-epc.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 #include <linux/pci-epf.h>
17 UNKNOWN_INTERFACE = -1,
36 * struct pci_epc_map - information about EPC memory for mapping a RC PCI
65 * struct pci_epc_ops - set of function pointers for performing EPC operations
74 * @set_msi: ops to set the requested number of MSI interrupts in the MSI
76 * @get_msi: ops to get the number of MSI interrupts allocated by the RC from
77 * the MSI capability register
78 * @set_msix: ops to set the requested number of MSI-X interrupts in the
79 * MSI-X capability register
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H A Dpci-epf.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 #include <linux/msi.h>
23 NO_BAR = -1,
33 * struct pci_epf_header - represents standard configuration header
36 * @revid: specifies a device-specific revision identifier
37 * @progif_code: identifies a specific register-level programming interface
41 * @subsys_vendor_id: vendor of the add-in card or subsystem
59 * struct pci_epf_ops - set of function pointers for performing EPF operations
63 * @add_cfs: ops to initialize function-specific configfs attributes
73 * struct pci_epc_event_ops - Callbacks for capturing the EPC events
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/linux/arch/powerpc/platforms/44x/
H A Dhsta_msi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * MSI support for PPC4xx SoCs using High Speed Transfer Assist (HSTA) for
11 #include <linux/msi.h>
18 #include <asm/ppc-pci.h>
23 /* The ioremapped HSTA MSI IO space */
26 /* Physical address of HSTA MSI IO space */
45 /* We don't support MSI-X */ in hsta_setup_msi_irqs()
47 pr_debug("%s: MSI-X not supported.\n", __func__); in hsta_setup_msi_irqs()
48 return -EINVAL; in hsta_setup_msi_irqs()
51 msi_for_each_desc(entry, &dev->dev, MSI_DESC_NOTASSOCIATED) { in hsta_setup_msi_irqs()
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