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/linux/drivers/net/
H A Dmii.c3 mii.c: MII interface library
34 #include <linux/mii.h>
36 static u32 mii_get_an(struct mii_if_info *mii, u16 addr) in mii_get_an() argument
40 advert = mii->mdio_read(mii->dev, mii->phy_id, addr); in mii_get_an()
47 * @mii: MII interface
53 void mii_ethtool_gset(struct mii_if_info *mii, struct ethtool_cmd *ecmd) in mii_ethtool_gset() argument
55 struct net_device *dev = mii->dev; in mii_ethtool_gset()
63 if (mii->supports_gmii) in mii_ethtool_gset()
74 ecmd->phy_address = mii->phy_id; in mii_ethtool_gset()
79 bmcr = mii->mdio_read(dev, mii->phy_id, MII_BMCR); in mii_ethtool_gset()
[all …]
/linux/drivers/net/ethernet/stmicro/stmmac/
H A Dstmmac_mdio.c4 Provides Bus interface for MII registers
16 #include <linux/mii.h>
84 unsigned int mii_address = priv->hw->mii.addr; in stmmac_xgmac2_mdio_read()
85 unsigned int mii_data = priv->hw->mii.data; in stmmac_xgmac2_mdio_read()
93 /* Wait until any existing MII operation is complete */ in stmmac_xgmac2_mdio_read()
100 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) in stmmac_xgmac2_mdio_read()
101 & priv->hw->mii.clk_csr_mask; in stmmac_xgmac2_mdio_read()
104 /* Wait until any existing MII operation is complete */ in stmmac_xgmac2_mdio_read()
111 /* Set the MII address register to read */ in stmmac_xgmac2_mdio_read()
115 /* Wait until any existing MII operation is complete */ in stmmac_xgmac2_mdio_read()
[all …]
H A Ddwmac100_core.c185 mac->mii.addr = MAC_MII_ADDR; in dwmac100_setup()
186 mac->mii.data = MAC_MII_DATA; in dwmac100_setup()
187 mac->mii.addr_shift = 11; in dwmac100_setup()
188 mac->mii.addr_mask = 0x0000F800; in dwmac100_setup()
189 mac->mii.reg_shift = 6; in dwmac100_setup()
190 mac->mii.reg_mask = 0x000007C0; in dwmac100_setup()
191 mac->mii.clk_csr_shift = 2; in dwmac100_setup()
192 mac->mii.clk_csr_mask = GENMASK(5, 2); in dwmac100_setup()
/linux/drivers/net/mdio/
H A Dmdio-regmap.c56 struct mii_bus *mii; in devm_mdio_regmap_register() local
62 mii = devm_mdiobus_alloc_size(config->parent, sizeof(*mr)); in devm_mdio_regmap_register()
63 if (!mii) in devm_mdio_regmap_register()
66 mr = mii->priv; in devm_mdio_regmap_register()
70 mii->name = DRV_NAME; in devm_mdio_regmap_register()
71 strscpy(mii->id, config->name, MII_BUS_ID_SIZE); in devm_mdio_regmap_register()
72 mii->parent = config->parent; in devm_mdio_regmap_register()
73 mii->read = mdio_regmap_read_c22; in devm_mdio_regmap_register()
74 mii->write = mdio_regmap_write_c22; in devm_mdio_regmap_register()
77 mii->phy_mask = ~BIT(config->valid_addr); in devm_mdio_regmap_register()
[all …]
H A Dmdio-i2c.c453 struct mii_bus *mii; in mdio_i2c_alloc() local
459 mii = mdiobus_alloc(); in mdio_i2c_alloc()
460 if (!mii) in mdio_i2c_alloc()
463 snprintf(mii->id, MII_BUS_ID_SIZE, "i2c:%s", dev_name(parent)); in mdio_i2c_alloc()
464 mii->parent = parent; in mdio_i2c_alloc()
465 mii->priv = i2c; in mdio_i2c_alloc()
470 mii->read = smbus_byte_mii_read_default_c22; in mdio_i2c_alloc()
471 mii->write = smbus_byte_mii_write_default_c22; in mdio_i2c_alloc()
472 return mii; in mdio_i2c_alloc()
482 mdiobus_free(mii); in mdio_i2c_alloc()
[all …]
/linux/drivers/net/ethernet/samsung/sxgbe/
H A Dsxgbe_mdio.c13 #include <linux/mii.h>
27 #define SXGBE_MII_BUSY 0x00400000 /* mii busy */
49 writel(reg, sp->ioaddr + sp->hw->mii.data); in sxgbe_mdio_ctrl_data()
60 writel(reg, sp->ioaddr + sp->hw->mii.addr); in sxgbe_mdio_c45()
74 writel(reg, sp->ioaddr + sp->hw->mii.addr); in sxgbe_mdio_c22()
82 const struct mii_regs *mii = &sp->hw->mii; in sxgbe_mdio_access_c22() local
85 rc = sxgbe_mdio_busy_wait(sp->ioaddr, mii->data); in sxgbe_mdio_access_c22()
95 return sxgbe_mdio_busy_wait(sp->ioaddr, mii->data); in sxgbe_mdio_access_c22()
102 const struct mii_regs *mii = &sp->hw->mii; in sxgbe_mdio_access_c45() local
105 rc = sxgbe_mdio_busy_wait(sp->ioaddr, mii->data); in sxgbe_mdio_access_c45()
[all …]
/linux/Documentation/devicetree/bindings/net/pcs/
H A Drenesas,rzn1-miic.yaml7 title: Renesas RZ/N1 MII converter
13 This MII converter is present on the Renesas RZ/N1 SoC family. It is
14 responsible to do MII passthrough or convert it to RMII/RGMII.
34 - description: MII reference clock
37 - description: AHB clock used for the MII converter register interface
47 description: MII Switch PORTIN configuration. This value should use one of
56 "^mii-conv@[0-5]$":
58 description: MII converter port
62 description: MII Converter port number.
147 mii_conv1: mii-conv@1 {
[all …]
/linux/drivers/bcma/
H A Ddriver_chipcommon_b.c36 void __iomem *mii = ccb->mii; in bcma_chipco_b_mii_write() local
38 writel(offset, mii + BCMA_CCB_MII_MNG_CTL); in bcma_chipco_b_mii_write()
39 bcma_wait_reg(bus, mii + BCMA_CCB_MII_MNG_CTL, 0x0100, 0x0000, 100); in bcma_chipco_b_mii_write()
40 writel(value, mii + BCMA_CCB_MII_MNG_CMD_DATA); in bcma_chipco_b_mii_write()
41 bcma_wait_reg(bus, mii + BCMA_CCB_MII_MNG_CTL, 0x0100, 0x0000, 100); in bcma_chipco_b_mii_write()
51 ccb->mii = ioremap(ccb->core->addr_s[1], BCMA_CORE_SIZE); in bcma_core_chipcommon_b_init()
52 if (!ccb->mii) in bcma_core_chipcommon_b_init()
60 if (ccb->mii) in bcma_core_chipcommon_b_free()
61 iounmap(ccb->mii); in bcma_core_chipcommon_b_free()
/linux/include/linux/
H A Dsungem_phy.h21 /* Structure used to statically define an mii/gii based PHY */
70 /* MII definitions missing from mii.h */
77 /* MII BCM5201 MULTIPHY interrupt register */
86 /* MII BCM5201 MULTIPHY register bits */
90 /* MII BCM5221 Additional registers */
99 /* MII BCM5241 Additional registers */
102 /* MII BCM5400 1000-BASET Control register */
106 /* MII BCM5400 AUXCONTROL register */
110 /* MII BCM5400 AUXSTATUS register */
H A Dmii.h3 * linux/mii.h: definitions for MII-compatible transceivers
14 #include <uapi/linux/mii.h>
33 extern int mii_link_ok (struct mii_if_info *mii);
34 extern int mii_nway_restart (struct mii_if_info *mii);
35 extern void mii_ethtool_gset(struct mii_if_info *mii, struct ethtool_cmd *ecmd);
37 struct mii_if_info *mii, struct ethtool_link_ksettings *cmd);
38 extern int mii_ethtool_sset(struct mii_if_info *mii, struct ethtool_cmd *ecmd);
40 struct mii_if_info *mii, const struct ethtool_link_ksettings *cmd);
41 extern int mii_check_gmii_support(struct mii_if_info *mii);
42 extern void mii_check_link (struct mii_if_info *mii);
[all …]
H A Dmii_timestamper.h3 * Support for generic time stamping devices on MII buses.
17 * struct mii_timestamper - Callback interface to MII time stamping devices.
20 * the MII time stamping device promises to deliver it using
25 * @txtstamp: Requests a Tx timestamp for 'skb'. The MII time stamping
68 * struct mii_timestamping_ctrl - MII time stamping controller interface.
74 * MII timestamper instance or PTR_ERR.
/linux/Documentation/devicetree/bindings/ptp/
H A Dtimestamper.txt1 Time stamps from MII bus snooping devices
3 This binding supports non-PHY devices that snoop the MII bus and
6 alone MII time stamping drivers use this binding to specify the
9 Non-PHY MII time stamping drivers typically talk to the control
12 time stamping channels, each of which snoops on a MII bus.
15 stamping channel from the controller device to that phy's MII bus.
40 In this example, time stamps from the MII bus attached to phy@1 will
/linux/drivers/pinctrl/
H A Dpinctrl-falcon.c136 MFP_FALCON(GPIO64, MII, GPIO, NONE, NONE),
137 MFP_FALCON(GPIO65, MII, GPIO, NONE, NONE),
138 MFP_FALCON(GPIO66, MII, GPIO, NONE, NONE),
139 MFP_FALCON(GPIO67, MII, GPIO, NONE, NONE),
140 MFP_FALCON(GPIO68, MII, GPIO, NONE, NONE),
141 MFP_FALCON(GPIO69, MII, GPIO, NONE, NONE),
142 MFP_FALCON(GPIO70, MII, GPIO, NONE, NONE),
143 MFP_FALCON(GPIO71, MII, GPIO, NONE, NONE),
144 MFP_FALCON(GPIO72, MII, GPIO, NONE, NONE),
145 MFP_FALCON(GPIO73, MII, GPIO, NONE, NONE),
[all …]
H A Dpinctrl-xway.c115 MFP_XWAY(GPIO0, GPIO, EXIN, MII, TDM),
119 MFP_XWAY(GPIO4, GPIO, GPT, EPHY, MII),
120 MFP_XWAY(GPIO5, GPIO, MII, ASC, GPT),
121 MFP_XWAY(GPIO6, GPIO, MII, ASC, EXIN),
122 MFP_XWAY(GPIO7, GPIO, SPI, MII, JTAG),
123 MFP_XWAY(GPIO8, GPIO, SPI, MII, JTAG),
124 MFP_XWAY(GPIO9, GPIO, SPI, MII, JTAG),
125 MFP_XWAY(GPIO10, GPIO, SPI, MII, JTAG),
127 MFP_XWAY(GPIO12, GPIO, EBU, MII, SDIO),
128 MFP_XWAY(GPIO13, GPIO, EBU, MII, CGU),
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmarvell,kirkwood-pinctrl.txt33 mii(col)
35 mii(crs)
41 mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col)
43 mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs)
47 mpp35 35 gpio, mii(rxerr)
71 mii(col), mii-1(rxerr)
73 mii(crs), sata0(prsnt)
79 mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col)
81 mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs)
100 mpp35 35 gpio, ge1(rxerr), sata0(act), mii(rxerr)
[all …]
H A Dmarvell,armada-37xx-pinctrl.txt120 - functions mii, gpio
144 - functions ptp, mii
148 - functions ptp, mii
152 - functions mii, mii_err
190 rgmii_pins: mii-pins {
192 function = "mii";
/linux/Documentation/devicetree/bindings/net/dsa/
H A Dmicrel,ks8995.yaml19 fabric, connected to an external MII interface name MII-P5. This is
20 unrelated from the CPU-facing port 5 which is used for DSA MII traffic.
82 phy-mode = "mii";
96 /* The WAN port connected on MII-P5 */
100 phy-mode = "mii";
106 phy-mode = "mii";
/linux/arch/arm/boot/dts/ti/omap/
H A Dam335x-boneblack.dts139 "[mii col]",
140 "[mii crs]",
141 "[mii rx err]",
142 "[mii tx en]",
143 "[mii rx dv]",
148 "[mii tx clk]",
149 "[mii rx clk]",
/linux/drivers/net/usb/
H A Dsr9700.c19 #include <linux/mii.h>
250 return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL); in sr9700_ioctl()
329 struct mii_if_info *mii; in sr9700_bind() local
346 mii = &dev->mii; in sr9700_bind()
347 mii->dev = netdev; in sr9700_bind()
348 mii->mdio_read = sr_mdio_read; in sr9700_bind()
349 mii->mdio_write = sr_mdio_write; in sr9700_bind()
350 mii->phy_id_mask = 0x1f; in sr9700_bind()
351 mii->reg_num_mask = 0x1f; in sr9700_bind()
379 sr_mdio_write(netdev, mii->phy_id, MII_BMCR, BMCR_RESET); in sr9700_bind()
[all …]
H A Dsr9800.c19 #include <linux/mii.h>
174 netdev_err(dev->net, "Failed to enable software MII access\n"); in sr_set_sw_mii()
184 netdev_err(dev->net, "Failed to enable hardware MII access\n"); in sr_set_hw_mii()
369 /* Get the PHY Identifier from the PHYSID1 & PHYSID2 MII registers */
378 phy_reg = sr_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID1); in sr_get_phyid()
389 phy_reg = sr_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID2); in sr_get_phyid()
485 return mii_link_ok(&dev->mii); in sr_get_link()
492 return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL); in sr_ioctl()
539 mii_check_media(&dev->mii, 1, 1); in sr9800_link_reset()
540 mii_ethtool_gset(&dev->mii, &ecmd); in sr9800_link_reset()
[all …]
H A Dr8153_ecm.c4 #include <linux/mii.h>
106 dev->mii.dev = dev->net; in r8153_bind()
107 dev->mii.mdio_read = r8153_ecm_mdio_read; in r8153_bind()
108 dev->mii.mdio_write = r8153_ecm_mdio_write; in r8153_bind()
109 dev->mii.reg_num_mask = 0x1f; in r8153_bind()
110 dev->mii.supports_gmii = 1; in r8153_bind()
/linux/drivers/net/phy/
H A Dmii_timestamper.c3 // Support for generic time stamping devices on MII buses.
19 * register_mii_tstamp_controller() - registers an MII time stamping device.
48 * unregister_mii_tstamp_controller() - unregisters an MII time stamping device.
71 * register_mii_timestamper - Enables a given port of an MII time stamper.
73 * @node: The device tree node of the MII time stamp controller.
104 * unregister_mii_timestamper - Disables a given MII time stamper.
/linux/arch/arm/boot/dts/intel/ixp/
H A Dintel-ixp42x-linksys-wrv54g.dts92 phy-mode = "mii";
98 phy-mode = "mii";
104 phy-mode = "mii";
110 phy-mode = "mii";
116 phy-mode = "mii";
194 phy-mode = "mii";
228 * EthC connects to MII-P5 on the KS8995 bypassing
235 phy-mode = "mii";
/linux/drivers/net/ethernet/renesas/
H A DKconfig23 select MII
34 select MII
47 select MII
57 select MII
/linux/drivers/net/ethernet/smsc/
H A Depic100.c85 #include <linux/mii.h>
280 signed char phys[4]; /* MII device addresses. */
284 struct mii_if_info mii; member
372 ep->mii.dev = dev; in epic_init_one()
373 ep->mii.mdio_read = mdio_read; in epic_init_one()
374 ep->mii.mdio_write = mdio_write; in epic_init_one()
375 ep->mii.phy_id_mask = 0x1f; in epic_init_one()
376 ep->mii.reg_num_mask = 0x1f; in epic_init_one()
407 /* Magic?! If we don't set this bit the MII interface won't work. */ in epic_init_one()
412 /* Turn on the MII transceiver. */ in epic_init_one()
[all …]

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