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/linux/Documentation/devicetree/bindings/phy/
H A Dqcom,qusb2-phy.yaml116 qcom,hstx-trim-value:
118 It is a 4 bit value that specifies tuning for HSTX
139 It is a 1 bit value that specifies how long the HSTX
180 qcom,hstx-trim-value: false
H A Drealtek,usb2phy.yaml96 realtek,inverse-hstx-sync-clock:
148 realtek,inverse-hstx-sync-clock: false
172 realtek,inverse-hstx-sync-clock;
/linux/include/dt-bindings/phy/
H A Dphy-qcom-qusb2.h9 /* PHY HSTX TRIM bit values (24mA to 15mA) */
/linux/Documentation/devicetree/bindings/display/msm/
H A Ddsi-phy-10nm.yaml64 for the HSTX drive. Use supported levels (mV) to offset the drive level
/linux/arch/arm64/boot/dts/qcom/
H A Dsdm850-samsung-w737.dts604 qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>;
632 qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_22_8_MA>;
H A Dsdm845-mtp.dts733 qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>;
767 qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_22_8_MA>;
H A Dsdm845-db845c.dts1072 qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>;
1100 qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_22_8_MA>;
H A Dsdm845-xiaomi-beryllium-common.dtsi601 qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>;
H A Dsdm845-xiaomi-polaris.dts660 qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>;
H A Dsdm845-oneplus-common.dtsi787 qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>;
H A Dsdm845-samsung-starqltechn.dts921 qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>;
H A Dmsm8996.dtsi760 qusb2p_hstx_trim: hstx-trim@24e {
765 qusb2s_hstx_trim: hstx-trim@24f {
H A Dqcm2290.dtsi790 qusb2_hstx_trim: hstx-trim@25b {
H A Dsdm630.dtsi595 qusb2_hstx_trim: hstx-trim@240 {
H A Dsdm845.dtsi1222 qusb2p_hstx_trim: hstx-trim-primary@1eb {
1227 qusb2s_hstx_trim: hstx-trim-secondary@1eb {
H A Dmsm8998.dtsi856 qusb2_hstx_trim: hstx-trim@23a {
H A Dsm6115.dtsi982 qusb2_hstx_trim: hstx-trim@25b {
H A Dqcs615.dtsi510 qusb2_hstx_trim: hstx-trim@1f8 {
H A Dsc7180.dtsi813 qusb2p_hstx_trim: hstx-trim-primary@25b {
/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qusb2.c1051 dev_dbg(dev, "failed to lookup tune2 hstx trim value\n"); in qusb2_phy_probe()
1072 if (!of_property_read_u32(dev->of_node, "qcom,hstx-trim-value", in qusb2_phy_probe()
/linux/drivers/phy/realtek/
H A Dphy-rtk-usb2.c978 if (of_property_read_bool(np, "realtek,inverse-hstx-sync-clock")) in parse_phy_data()
/linux/drivers/gpu/drm/bridge/cadence/
H A Dcdns-dsi-core.c890 * HSTX and LPRX timeouts are both expressed in TX byte clk cycles and in cdns_dsi_bridge_atomic_pre_enable()
/linux/drivers/gpu/drm/vc4/
H A Dvc4_dsi.c1515 DSI_PORT_BIT(INT_HSTX_TO), "HSTX timeout"); in vc4_dsi_irq_handler()