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/linux/Documentation/devicetree/bindings/media/
H A Drockchip-rga.yaml78 <&cru HCLK_RGA>,
/linux/include/dt-bindings/clock/
H A Drk3188-cru-common.h128 #define HCLK_RGA 466 macro
H A Drk3128-cru.h138 #define HCLK_RGA 467 macro
H A Drk3228-cru.h136 #define HCLK_RGA 467 macro
H A Drv1108-cru.h154 #define HCLK_RGA 335 macro
H A Drockchip,rk3562-cru.h335 #define HCLK_RGA 323 macro
H A Drk3328-cru.h201 #define HCLK_RGA 340 macro
H A Drk3288-cru.h188 #define HCLK_RGA 470 macro
H A Drk3368-cru.h175 #define HCLK_RGA 470 macro
H A Drockchip,rv1126-cru.h281 #define HCLK_RGA 217 macro
H A Drk3399-cru.h325 #define HCLK_RGA 485 macro
H A Drk3568-cru.h308 #define HCLK_RGA 244 macro
/linux/Documentation/devicetree/bindings/power/
H A Drockchip,power-controller.yaml223 <&cru HCLK_RGA>;
/linux/drivers/clk/rockchip/
H A Dclk-rk3128.c468 GATE(HCLK_RGA, "hclk_rga", "hclk_vio", 0, RK2928_CLKGATE_CON(6), 10, GFLAGS),
H A Dclk-rk3228.c543 GATE(HCLK_RGA, "hclk_rga", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 1, GFLAGS),
H A Dclk-rv1108.c455 GATE(HCLK_RGA, "hclk_rga", "hclk_vio_pre", 0,
H A Dclk-rk3188.c462 GATE(HCLK_RGA, "hclk_rga", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 10, GFLAGS),
H A Dclk-rk3328.c718 GATE(HCLK_RGA, "hclk_rga", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 11, GFLAGS),
H A Dclk-rk3368.c743 GATE(HCLK_RGA, "hclk_rga", "hclk_vio", 0, RK3368_CLKGATE_CON(16), 1, GFLAGS),
H A Dclk-px30.c822 GATE(HCLK_RGA, "hclk_rga", "hclk_vo_pre", 0, PX30_CLKGATE_CON(3), 8, GFLAGS),
H A Dclk-rk3288.c784 GATE(HCLK_RGA, "hclk_rga", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 1, GFLAGS),
H A Dclk-rv1126.c737 GATE(HCLK_RGA, "hclk_rga", "hclk_pdvo", 0,
/linux/arch/arm/boot/dts/rockchip/
H A Drk322x.dtsi210 <&cru HCLK_RGA>,
701 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
H A Drk3188.dtsi723 <&cru HCLK_RGA>;
H A Drk3066a.dtsi801 <&cru HCLK_RGA>;

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