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/linux/drivers/memory/tegra/
H A Dtegra210-emc.h117 #define EMC_MRW4 0x13c macro
853 u32 emc_mrw4; member
H A Dtegra124-emc.c122 #define EMC_MRW4 0x13c macro
797 emc_ccfifo_writel(emc, timing->emc_mode_4, EMC_MRW4); in tegra_emc_prepare_timing_change()
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dnvidia,tegra124-emc.yaml129 value of the EMC_MRW4 register for this set of timings