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/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dbrcm,brcmstb-memc-ddr.yaml4 $id: http://devicetree.org/schemas/memory-controllers/brcm,brcmstb-memc-ddr.yaml#
18 - brcm,brcmstb-memc-ddr-rev-b.2.2
19 - brcm,brcmstb-memc-ddr-rev-b.2.3
20 - brcm,brcmstb-memc-ddr-rev-b.2.5
21 - brcm,brcmstb-memc-ddr-rev-b.2.6
22 - brcm,brcmstb-memc-ddr-rev-b.2.7
23 - brcm,brcmstb-memc-ddr-rev-b.2.8
24 - brcm,brcmstb-memc-ddr-rev-b.3.0
25 - brcm,brcmstb-memc-ddr-rev-b.3.1
26 - brcm,brcmstb-memc-ddr
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H A Dqca,ath79-ddr-controller.yaml4 $id: http://devicetree.org/schemas/memory-controllers/qca,ath79-ddr-controller.yaml#
7 title: Qualcomm Atheros AR7xxx/AR9xxx DDR controller
13 The DDR controller of the AR7xxx and AR9xxx families provides an interface to
14 flush the FIFO between various devices and the DDR. This is mainly used by
22 - const: qca,ar9132-ddr-controller
23 - const: qca,ar7240-ddr-controller
26 - qca,ar7100-ddr-controller
27 - qca,ar7240-ddr-controller
29 "#qca,ddr-wb-channel-cells":
41 - "#qca,ddr
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H A Dcalxeda-ddr-ctrlr.yaml4 $id: http://devicetree.org/schemas/memory-controllers/calxeda-ddr-ctrlr.yaml#
7 title: Calxeda DDR memory controller
10 The Calxeda DDR memory controller is initialised and programmed by the
20 - calxeda,hb-ddr-ctrl
21 - calxeda,ecx-2000-ddr-ctrl
39 compatible = "calxeda,hb-ddr-ctrl";
H A Dxlnx,versal-ddrmc-edac.yaml7 title: Xilinx Versal DDRMC (Integrated DDR Memory Controller)
14 The integrated DDR Memory Controllers (DDRMCs) support both DDR4 and LPDDR4/
15 4X memory interfaces. Versal DDR memory controller has an optional ECC support
24 - description: DDR Memory Controller registers
25 - description: NOC registers corresponding to DDR Memory Controller
/linux/Documentation/devicetree/bindings/perf/
H A Dfsl-imx-ddr.yaml4 $id: http://devicetree.org/schemas/perf/fsl-imx-ddr.yaml#
7 title: Freescale(NXP) IMX8/9 DDR performance monitor
16 - fsl,imx8-ddr-pmu
17 - fsl,imx8m-ddr-pmu
18 - fsl,imx8mq-ddr-pmu
19 - fsl,imx8mm-ddr-pmu
20 - fsl,imx8mn-ddr-pmu
21 - fsl,imx8mp-ddr-pmu
22 - fsl,imx93-ddr-pmu
25 - fsl,imx8mm-ddr
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H A Damlogic,g12-ddr-pmu.yaml4 $id: http://devicetree.org/schemas/perf/amlogic,g12-ddr-pmu.yaml#
7 title: Amlogic G12 DDR performance monitor
13 Amlogic G12 series SoC integrate DDR bandwidth monitor.
21 - amlogic,g12a-ddr-pmu
22 - amlogic,g12b-ddr-pmu
23 - amlogic,sm1-ddr-pmu
49 compatible = "amlogic,g12a-ddr-pmu";
/linux/tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/
H A Dmetrics.json19 "BriefDescription": "bytes of all masters read from ddr",
27 "BriefDescription": "bytes of all masters write to ddr",
35 "BriefDescription": "bytes of all a55 read from ddr",
43 "BriefDescription": "bytes of all a55 write to ddr (part1)",
51 "BriefDescription": "bytes of all a55 write to ddr (part2)",
59 "BriefDescription": "bytes of a55 core 0 read from ddr",
67 "BriefDescription": "bytes of a55 core 0 write to ddr",
75 "BriefDescription": "bytes of a55 core 1 read from ddr",
83 "BriefDescription": "bytes of a55 core 1 write to ddr",
91 "BriefDescription": "bytes of a55 core 2 read from ddr",
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/linux/tools/perf/pmu-events/arch/arm64/freescale/imx8mp/sys/
H A Dmetrics.json3 "BriefDescription": "bytes of all masters read from ddr",
11 "BriefDescription": "bytes of all masters write to ddr",
19 "BriefDescription": "bytes of a53 core read from ddr",
27 "BriefDescription": "bytes of a53 core write to ddr",
35 "BriefDescription": "bytes of supermix(m7) core read from ddr",
43 "BriefDescription": "bytes of supermix(m7) write to ddr",
51 "BriefDescription": "bytes of gpu 3d read from ddr",
59 "BriefDescription": "bytes of gpu 3d write to ddr",
67 "BriefDescription": "bytes of gpu 2d read from ddr",
75 "BriefDescription": "bytes of gpu 2d write to ddr",
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H A Dddrc.json3 "BriefDescription": "ddr cycles event",
10 "BriefDescription": "ddr read-cycles event",
17 "BriefDescription": "ddr write-cycles event",
24 "BriefDescription": "ddr read event",
31 "BriefDescription": "ddr write event",
/linux/Documentation/devicetree/bindings/arm/bcm/
H A Dbrcm,brcmstb.txt148 independently (control registers, DDR PHYs, etc.). One might consider
163 == DDR PHY control
165 Control registers for this memory controller's DDR PHY.
169 "brcm,brcmstb-ddr-phy-v71.1"
170 "brcm,brcmstb-ddr-phy-v72.0"
171 "brcm,brcmstb-ddr-phy-v225.1"
172 "brcm,brcmstb-ddr-phy-v240.1"
173 "brcm,brcmstb-ddr-phy-v240.2"
175 - reg : the DDR PHY register range
177 == DDR SHIMPH
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/linux/Documentation/devicetree/bindings/mips/brcm/
H A Dsoc.txt45 independently (control registers, DDR PHYs, etc.). One might consider
58 the entire memory controller (including all sub nodes: DDR PHY,
75 memc-ddr@2000 {
79 ddr-phy@6000 {
86 == DDR PHY control
88 Control registers for this memory controller's DDR PHY.
92 "brcm,brcmstb-ddr-phy-v64.5"
93 "brcm,brcmstb-ddr-phy"
95 - reg : the DDR PHY register range and length
99 ddr
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/linux/arch/mips/include/asm/mach-rc32434/
H A Dddr.h2 * Definitions for the DDR registers
34 /* DDR register structure */
51 /* DDR banks masks */
56 /* DDR bank0 registers */
86 /* DDR bank C registers */
91 /* Custom DDR bank registers */
102 /* DDR QSC registers */
114 /* DDR LLC registers */
126 /* DDR LLFC registers */
132 /* DDR DLLT
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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dqca,ar7100-cpu-intc.yaml13 On most SoC the IRQ controller need to flush the DDR FIFO before running the
15 qca,ddr-wb-channels and qca,ddr-wb-channel-interrupts properties.
31 qca,ddr-wb-channel-interrupts:
35 qca,ddr-wb-channels:
54 qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
55 qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
60 #qca,ddr-wb-channel-cells = <1>;
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm7445.dtsi239 memc-ddr@2000 {
240 compatible = "brcm,brcmstb-memc-ddr-rev-b.1.x",
241 "brcm,brcmstb-memc-ddr";
245 ddr-phy@6000 {
246 compatible = "brcm,brcmstb-ddr-phy-v240.1";
251 compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
262 memc-ddr@2000 {
263 compatible = "brcm,brcmstb-memc-ddr-rev-b.1.x",
264 "brcm,brcmstb-memc-ddr";
268 ddr
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/linux/include/linux/
H A Dfsl-diu-fb.h65 * These are the fields of area descriptor(in DDR memory) for every plane
68 /* Word 0(32-bit) in DDR memory */
81 /* Word 1(32-bit) in DDR memory */
84 /* Word 2(32-bit) in DDR memory */
92 /* Word 3(32-bit) in DDR memory */
100 /* Word 4(32-bit) in DDR memory */
108 /* Word 5(32-bit) in DDR memory */
116 /* Word 6(32-bit) in DDR memory */
122 /* Word 7(32-bit) in DDR memory */
129 /* Word 8(32-bit) in DDR memor
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/linux/arch/mips/rb532/
H A Dprom.c21 #include <asm/mach-rc32434/ddr.h>
29 .name = "ddr-reg",
103 struct ddr_ram __iomem *ddr; in prom_init() local
107 ddr = ioremap(ddr_reg[0].start, in prom_init()
110 if (!ddr) { in prom_init()
111 printk(KERN_ERR "Unable to remap DDR register\n"); in prom_init()
115 ddrbase = (phys_addr_t)&ddr->ddrbase; in prom_init()
116 memsize = (phys_addr_t)&ddr->ddrmask; in prom_init()
/linux/tools/perf/pmu-events/arch/arm64/freescale/imx8mq/sys/
H A Dddrc.json3 "BriefDescription": "ddr cycles event",
10 "BriefDescription": "ddr read-cycles event",
17 "BriefDescription": "ddr write-cycles event",
24 "BriefDescription": "ddr read event",
31 "BriefDescription": "ddr write event",
/linux/tools/perf/pmu-events/arch/arm64/freescale/imx8mn/sys/
H A Dddrc.json3 "BriefDescription": "ddr cycles event",
10 "BriefDescription": "ddr read-cycles event",
17 "BriefDescription": "ddr write-cycles event",
24 "BriefDescription": "ddr read event",
31 "BriefDescription": "ddr write event",
/linux/tools/perf/pmu-events/arch/arm64/freescale/imx8mm/sys/
H A Dddrc.json3 "BriefDescription": "ddr cycles event",
10 "BriefDescription": "ddr read-cycles event",
17 "BriefDescription": "ddr write-cycles event",
24 "BriefDescription": "ddr read event",
31 "BriefDescription": "ddr write event",
/linux/Documentation/devicetree/bindings/clock/
H A Damlogic,meson8-ddr-clkc.yaml4 $id: http://devicetree.org/schemas/clock/amlogic,meson8-ddr-clkc.yaml#
7 title: Amlogic DDR Clock Controller
15 - amlogic,meson8-ddr-clkc
16 - amlogic,meson8b-ddr-clkc
43 compatible = "amlogic,meson8-ddr-clkc";
/linux/drivers/media/pci/tw5864/
H A Dtw5864-reg.h17 /* DDR controller enabled */
30 * Video Frame mapping in DDR
76 * 0->3 4 VLC data buffer in DDR (1M each)
77 * 0->7 8 VLC data buffer in DDR (512k each)
145 /* DDR Single Access Page Number */
147 /* DDR-DPR Burst Read Enable */
150 * DDR A/B Select as HOST access
156 * DDR Access Mode Select
157 * 0 Single R/W Access (Host <-> DDR)
287 /* DDR bas
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/linux/drivers/soc/qcom/
H A Dqcom_stats.c153 * DDR statistic have two different types of details encoded. in qcom_ddr_stats_print()
154 * (1) DDR LPM Stats in qcom_ddr_stats_print()
155 * (2) DDR Frequency Stats in qcom_ddr_stats_print()
157 * The name field have details like which type of DDR stat (bits 8:15) in qcom_ddr_stats_print()
160 * In case of DDR LPM stat, name field will be encoded as, in qcom_ddr_stats_print()
162 * 0:7 - DDR LPM name, can be of 0xd4, 0xd3, 0x11 and 0xd0. in qcom_ddr_stats_print()
166 * In case of DDR FREQ stats, name field will be encoded as, in qcom_ddr_stats_print()
168 * 0:4 - DDR Clock plan index (CP IDX) in qcom_ddr_stats_print()
175 seq_printf(s, "DDR LPM Stat Name:0x%lx\tcount:%u\tDuration (ticks):%llu\n", in qcom_ddr_stats_print()
183 seq_printf(s, "DDR Fre in qcom_ddr_stats_print()
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/linux/tools/perf/pmu-events/arch/x86/knightslanding/
H A Dmemory.json11 "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses from DDR (local and far)",
14 "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.DDR",
71 "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from DDR (local and far)",
74 "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.DDR",
181 "BriefDescription": "Counts any Read request that accounts for responses from DDR (local and far)",
184 "EventName": "OFFCORE_RESPONSE.ANY_READ.DDR",
241 "BriefDescription": "Counts any request that accounts for responses from DDR (local and far)",
244 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.DDR",
301 "BriefDescription": "Counts Demand cacheable data write requests that accounts for responses from DDR (local and far)",
304 "EventName": "OFFCORE_RESPONSE.ANY_RFO.DDR",
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/linux/drivers/irqchip/
H A Dirq-ath79-cpu.c27 * This array map the interrupt lines to the DDR write buffer channels.
63 node, "qca,ddr-wb-channels", "#qca,ddr-wb-channel-cells"); in ar79_cpu_intc_of_init()
70 node, "qca,ddr-wb-channel-interrupts", i, &irq); in ar79_cpu_intc_of_init()
75 node, "qca,ddr-wb-channels", in ar79_cpu_intc_of_init()
76 "#qca,ddr-wb-channel-cells", in ar79_cpu_intc_of_init()
/linux/Documentation/driver-api/thermal/
H A Dintel_dptf.rst228 DDR (Double Data Rate) and DLVR (Digital Linear Voltage Regulator)
249 DRAM devices of DDR IO interface and their power plane can generate EMI
251 mechanism by which DDR data rates can be changed if several conditions
252 are met: there is strong RFI interference because of DDR; CPU power
253 management has no other restriction in changing DDR data rates;
254 PC ODMs enable this feature (real time DDR RFI Mitigation referred to as
255 DDR-RFIM) for Wi-Fi from BIOS.
289 Request the restriction of specific DDR data rate and set this
297 Restricted DDR data rate for RFI protection: Lower Limit
300 Restricted DDR dat
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