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/linux/arch/arm/boot/dts/ti/omap/
H A Dam43xx-clocks.dtsi3 * Device Tree Source for AM43xx clock data
8 sys_clkin_ck: clock-sys-clkin-31@40 {
9 #clock-cells = <0>;
10 compatible = "ti,mux-clock";
11 clock-output-names = "sys_clkin_ck";
17 crystal_freq_sel_ck: clock-crystal-freq-sel-29@40 {
18 #clock-cells = <0>;
19 compatible = "ti,mux-clock";
20 clock-output-names = "crystal_freq_sel_ck";
26 sysboot_freq_sel_ck: clock-sysboot-freq-sel-22@44e10040 {
[all …]
H A Domap3xxx-clocks.dtsi3 * Device Tree Source for OMAP3 clock data
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-frequency = <16800000>;
15 #clock-cells = <0>;
16 compatible = "ti,mux-clock";
22 #clock-cells = <0>;
23 compatible = "ti,divider-clock";
32 #clock-cells = <0>;
33 compatible = "ti,gate-clock";
[all …]
H A Ddra7xx-clocks.dtsi3 * Device Tree Source for DRA7xx clock data
8 atl_clkin0_ck: clock-atl-clkin0 {
9 #clock-cells = <0>;
10 compatible = "ti,dra7-atl-clock";
11 clock-output-names = "atl_clkin0_ck";
15 atl_clkin1_ck: clock-atl-clkin1 {
16 #clock-cells = <0>;
17 compatible = "ti,dra7-atl-clock";
18 clock-output-names = "atl_clkin1_ck";
22 atl_clkin2_ck: clock-atl-clkin2 {
[all …]
H A Domap54xx-clocks.dtsi3 * Device Tree Source for OMAP5 clock data
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-output-names = "pad_clks_src_ck";
12 clock-frequency = <12000000>;
16 #clock-cells = <0>;
17 compatible = "ti,gate-clock";
18 clock-output-names = "pad_clks_ck";
25 #clock-cells = <0>;
26 compatible = "fixed-clock";
[all …]
H A Domap44xx-clocks.dtsi3 * Device Tree Source for OMAP4 clock data
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-output-names = "extalt_clkin_ck";
12 clock-frequency = <59000000>;
16 #clock-cells = <0>;
17 compatible = "fixed-clock";
18 clock-output-names = "pad_clks_src_ck";
19 clock-frequency = <12000000>;
23 #clock-cells = <0>;
[all …]
H A Domap24xx-clocks.dtsi3 * Device Tree Source for OMAP24xx clock data
9 #clock-cells = <0>;
10 compatible = "ti,composite-mux-clock";
17 #clock-cells = <0>;
18 compatible = "ti,composite-clock";
23 #clock-cells = <0>;
24 compatible = "ti,composite-mux-clock";
31 #clock-cells = <0>;
32 compatible = "ti,composite-clock";
39 #clock-cells = <0>;
[all …]
H A Ddm814x-clocks.dtsi10 #clock-cells = <1>;
11 compatible = "ti,dm814-adpll-s-clock";
14 clock-names = "clkinp", "clkinpulow", "clkinphif";
15 clock-output-names = "481c5040.adpll.dcoclkldo",
22 #clock-cells = <1>;
23 compatible = "ti,dm814-adpll-lj-clock";
26 clock-names = "clkinp", "clkinpulow";
27 clock-output-names = "481c5080.adpll.dcoclkldo",
33 #clock-cells = <1>;
34 compatible = "ti,dm814-adpll-lj-clock";
[all …]
H A Domap36xx-omap3430es2plus-clocks.dtsi3 * Device Tree Source for OMAP34xx/OMAP36xx clock data
8 clock@a00 {
11 #clock-cells = <2>;
15 ssi_ssr_gate_fck_3430es2: clock-ssi-ssr-gate-fck-3430es2@0 {
17 #clock-cells = <0>;
18 compatible = "ti,composite-no-wait-gate-clock";
19 clock-output-names = "ssi_ssr_gate_fck_3430es2";
24 clock@a40 {
27 #clock-cells = <2>;
31 ssi_ssr_div_fck_3430es2: clock-ssi-ssr-div-fck-3430es2@8 {
[all …]
H A Domap34xx-omap36xx-clocks.dtsi3 * Device Tree Source for OMAP34XX/OMAP36XX clock data
9 #clock-cells = <0>;
10 compatible = "fixed-factor-clock";
12 clock-mult = <1>;
13 clock-div = <1>;
16 clock@a14 {
19 #clock-cells = <2>;
23 aes1_ick: clock-aes1-ick@3 {
25 #clock-cells = <0>;
26 compatible = "ti,omap3-interface-clock";
[all …]
H A Domap36xx-am35xx-omap3430es2plus-clocks.dtsi3 * Device Tree Source for OMAP36xx/AM35xx/OMAP34xx clock data
9 #clock-cells = <0>;
10 compatible = "fixed-factor-clock";
12 clock-mult = <1>;
13 clock-div = <3>;
17 #clock-cells = <0>;
18 compatible = "fixed-factor-clock";
20 clock-mult = <1>;
21 clock-div = <5>;
26 #clock-cells = <0>;
[all …]
H A Domap3430es1-clocks.dtsi3 * Device Tree Source for OMAP3430 ES1 clock data
9 #clock-cells = <0>;
10 compatible = "ti,wait-gate-clock";
17 #clock-cells = <0>;
18 compatible = "ti,divider-clock";
26 #clock-cells = <0>;
27 compatible = "fixed-factor-clock";
29 clock-mult = <1>;
30 clock-div = <1>;
34 #clock-cells = <0>;
[all …]
/linux/arch/arm/boot/dts/ti/keystone/
H A Dkeystone-clocks.dtsi3 * Device Tree Source for Keystone 2 clock tree
14 #clock-cells = <0>;
15 compatible = "ti,keystone,pll-mux-clock";
20 clock-output-names = "mainmuxclk";
24 #clock-cells = <0>;
25 compatible = "fixed-factor-clock";
27 clock-div = <1>;
28 clock-mult = <1>;
29 clock-output-names = "chipclk1";
33 #clock-cells = <0>;
[all …]
H A Dkeystone-k2hk-clocks.dtsi3 * Keystone 2 Kepler/Hawking SoC clock nodes
10 #clock-cells = <0>;
11 compatible = "ti,keystone,pll-clock";
13 clock-output-names = "arm-pll-clk";
19 #clock-cells = <0>;
20 compatible = "ti,keystone,main-pll-clock";
27 #clock-cells = <0>;
28 compatible = "ti,keystone,pll-clock";
30 clock-output-names = "papllclk";
36 #clock-cells = <0>;
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dmarvell,mvebu-core-clock.yaml4 $id: http://devicetree.org/schemas/clock/marvell,mvebu-core-clock.yaml#
7 title: Marvell MVEBU SoC core clock
14 Marvell MVEBU SoCs usually allow to determine core clock frequencies by
15 reading the Sample-At-Reset (SAR) register. The core clock consumer should
16 specify the desired clock by having the clock ID in its "clocks" phandle cell.
18 The following is a list of provided IDs and clock names on Armada 370/XP:
19 0 = tclk (Internal Bus clock)
20 1 = cpuclk (CPU clock)
21 2 = nbclk (L2 Cache clock)
22 3 = hclk (DRAM control clock)
[all …]
H A Dsamsung,exynos5260-clock.yaml4 $id: http://devicetree.org/schemas/clock/samsung,exynos5260-clock.yaml#
7 title: Samsung Exynos5260 SoC clock controller
18 - "fin_pll" - PLL input clock from XXTI
19 - "xrtcxti" - input clock from XRTCXTI
20 - "ioclk_pcm_extclk" - pcm external operation clock
21 - "ioclk_spdif_extclk" - spdif external operation clock
22 - "ioclk_i2s_cdclk" - i2s0 codec clock
26 are fed into the clock controller and then routed to the hardware blocks.
28 - "phyclk_dptx_phy_ch3_txd_clk" - dp phy clock for channel 3
29 - "phyclk_dptx_phy_ch2_txd_clk" - dp phy clock for channel 2
[all …]
H A Dqcom,mmcc.yaml4 $id: http://devicetree.org/schemas/clock/qcom,mmcc.yaml#
7 title: Qualcomm Multimedia Clock & Reset Controller
14 Qualcomm multimedia clock control module provides the clocks, resets and
37 clock-names:
64 - description: PLL 3 clock
65 - description: PLL 3 Vote clock
66 - description: DSI phy instance 1 dsi clock
67 - description: DSI phy instance 1 byte clock
68 - description: DSI phy instance 2 dsi clock
69 - description: DSI phy instance 2 byte clock
[all …]
H A Dst,stm32mp25-rcc.yaml4 $id: http://devicetree.org/schemas/clock/st,stm32mp25-rcc.yaml#
7 title: STM32MP25 Reset Clock Controller
13 The RCC hardware block is both a reset and a clock controller.
17 include/dt-bindings/clock/st,stm32mp25-rcc.h
28 '#clock-cells':
42 - description: CK_SCMI_ICN_HS_MCU High Speed interconnect bus clock
43 - description: CK_SCMI_ICN_LS_MCU Low Speed interconnect bus clock
44 - description: CK_SCMI_ICN_SDMMC SDMMC interconnect bus clock
45 - description: CK_SCMI_ICN_DDR DDR interconnect bus clock
46 - description: CK_SCMI_ICN_DISPLAY Display interconnect bus clock
[all …]
H A Dtesla,fsd-clock.yaml4 $id: http://devicetree.org/schemas/clock/tesla,fsd-clock.yaml#
7 title: Tesla FSD (Full Self-Driving) SoC clock controller
14 FSD clock controller consist of several clock management unit
16 The root clock comes from external OSC clock (24 MHz).
19 'dt-bindings/clock/fsd-clk.h' header.
24 - tesla,fsd-clock-cmu
25 - tesla,fsd-clock-imem
26 - tesla,fsd-clock-peric
27 - tesla,fsd-clock-fsys0
28 - tesla,fsd-clock-fsys1
[all …]
H A Dsocionext,uniphier-clock.yaml4 $id: http://devicetree.org/schemas/clock/socionext,uniphier-clock.yaml#
7 title: UniPhier clock controller
15 - description: System clock
17 - socionext,uniphier-ld4-clock
18 - socionext,uniphier-pro4-clock
19 - socionext,uniphier-sld8-clock
20 - socionext,uniphier-pro5-clock
21 - socionext,uniphier-pxs2-clock
22 - socionext,uniphier-ld6b-clock
23 - socionext,uniphier-ld11-clock
[all …]
H A Dnxp,lpc1850-cgu.yaml4 $id: http://devicetree.org/schemas/clock/nxp,lpc1850-cgu.yaml#
7 title: NXP LPC1850 Clock Generation Unit (CGU)
11 peripheral blocks of the LPC18xx. Each independent clock is called
12 a base clock and itself is one of the inputs to the two Clock
16 The CGU selects the inputs to the clock generators from multiple
17 clock sources, controls the clock generation, and routes the outputs
18 of the clock generators through the clock source bus to the output
19 stages. Each output stage provides an independent clock source and
34 '#clock-cells':
41 0 BASE_SAFE_CLK Base safe clock (always on) for WWDT
[all …]
/linux/drivers/clk/qcom/
H A DKconfig11 tristate "Support for Qualcomm's clock controllers"
23 tristate "X1E80100 Camera Clock Controller"
27 Support for the camera clock controller on X1E80100 devices.
31 tristate "X1E80100 Display Clock Controller"
35 Support for the two display clock controllers on Qualcomm
41 tristate "X1E80100 Global Clock Controller"
45 Support for the global clock controller on Qualcomm Technologies, Inc
51 tristate "X1E80100 Graphics Clock Controller"
55 Support for the graphics clock controller on X1E80100 devices.
60 tristate "X1E80100 TCSR Clock Controller"
[all …]
/linux/drivers/net/phy/
H A Dmicrochip_rds_ptp.c6 static int mchp_rds_phy_read_mmd(struct mchp_rds_ptp_clock *clock, in mchp_rds_phy_read_mmd() argument
9 struct phy_device *phydev = clock->phydev; in mchp_rds_phy_read_mmd()
12 addr = (offset + ((base == MCHP_RDS_PTP_PORT) ? BASE_PORT(clock) : in mchp_rds_phy_read_mmd()
13 BASE_CLK(clock))); in mchp_rds_phy_read_mmd()
15 return phy_read_mmd(phydev, PTP_MMD(clock), addr); in mchp_rds_phy_read_mmd()
18 static int mchp_rds_phy_write_mmd(struct mchp_rds_ptp_clock *clock, in mchp_rds_phy_write_mmd() argument
22 struct phy_device *phydev = clock->phydev; in mchp_rds_phy_write_mmd()
25 addr = (offset + ((base == MCHP_RDS_PTP_PORT) ? BASE_PORT(clock) : in mchp_rds_phy_write_mmd()
26 BASE_CLK(clock))); in mchp_rds_phy_write_mmd()
28 return phy_write_mmd(phydev, PTP_MMD(clock), addr, val); in mchp_rds_phy_write_mmd()
[all …]
/linux/drivers/clk/mediatek/
H A DKconfig3 # MediaTek Clock Drivers
5 menu "Clock driver for MediaTek SoC"
12 MediaTek SoCs' clock support.
15 bool "clock driver for MediaTek FHCTL hardware control"
22 bool "Clock driver for MediaTek MT2701"
30 bool "Clock driver for MediaTek MT2701 mmsys"
36 bool "Clock driver for MediaTek MT2701 imgsys"
42 bool "Clock driver for MediaTek MT2701 vdecsys"
48 bool "Clock driver for MediaTek MT2701 hifsys"
54 bool "Clock driver for MediaTek MT2701 ethsys"
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Dexynos5420.dtsi14 #include <dt-bindings/clock/exynos5420.h>
15 #include <dt-bindings/clock/exynos-audss-clk.h>
39 clocks = <&clock CLK_DOUT_ACLK400_DISP1>;
40 clock-names = "bus";
46 clocks = <&clock CLK_DOUT_ACLK300_DISP1>;
47 clock-names = "bus";
53 clocks = <&clock CLK_DOUT_ACLK200_FSYS>;
54 clock-names = "bus";
60 clocks = <&clock CLK_DOUT_ACLK200_FSYS2>;
61 clock-names = "bus";
[all …]
H A Dexynos5410.dtsi14 #include <dt-bindings/clock/exynos5410.h>
15 #include <dt-bindings/clock/exynos-audss-clk.h>
37 clock-frequency = <1600000000>;
44 clock-frequency = <1600000000>;
51 clock-frequency = <1600000000>;
58 clock-frequency = <1600000000>;
71 clock-names = "clkout16";
73 #clock-cells = <1>;
76 clock: clock-controller@10010000 { label
77 compatible = "samsung,exynos5410-clock";
[all …]

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