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/linux/tools/perf/pmu-events/arch/x86/broadwellde/
H A D	uncore-memory.json	543 "BriefDescription": "RD_CAS Access to Rank 0; All Banks", 548 "PublicDescription": "RD_CAS Access to Rank 0 : All Banks", 553 "BriefDescription": "RD_CAS Access to Rank 0; Bank 0", 558 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0", 562 "BriefDescription": "RD_CAS Access to Rank 0; Bank 1", 567 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1", 572 "BriefDescription": "RD_CAS Access to Rank 0; Bank 10", 577 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 10", 582 "BriefDescription": "RD_CAS Access to Rank 0; Bank 11", 587 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 11", [all …]
/linux/tools/perf/pmu-events/arch/x86/broadwellx/
H A D	uncore-memory.json	581 "BriefDescription": "RD_CAS Access to Rank 0; All Banks", 586 "PublicDescription": "RD_CAS Access to Rank 0 : All Banks", 591 "BriefDescription": "RD_CAS Access to Rank 0; Bank 0", 596 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0", 600 "BriefDescription": "RD_CAS Access to Rank 0; Bank 1", 605 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1", 610 "BriefDescription": "RD_CAS Access to Rank 0; Bank 10", 615 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 10", 620 "BriefDescription": "RD_CAS Access to Rank 0; Bank 11", 625 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 11", [all …]
/linux/tools/perf/pmu-events/arch/x86/haswellx/
H A D	uncore-memory.json	572 "BriefDescription": "RD_CAS Access to Rank 0; All Banks", 577 "PublicDescription": "RD_CAS Access to Rank 0 : All Banks", 582 "BriefDescription": "RD_CAS Access to Rank 0; Bank 0", 587 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0", 591 "BriefDescription": "RD_CAS Access to Rank 0; Bank 1", 596 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1", 601 "BriefDescription": "RD_CAS Access to Rank 0; Bank 10", 606 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 10", 611 "BriefDescription": "RD_CAS Access to Rank 0; Bank 11", 616 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 11", [all …]
/linux/Documentation/devicetree/bindings/access-controllers/
H A D	access-controllers.yaml	4 $id: http://devicetree.org/schemas/access-controllers/access-controllers.yaml# 7 title: Generic Domain Access Controllers 13 Common access controllers properties 15 Access controllers are in charge of stating which of the hardware blocks under 18 or a group of hardware blocks. An access controller's domain is the set of 19 resources covered by the access controller. 21 This device tree binding can be used to bind devices to their access 22 controller provided by access-controllers property. In this case, the device 23 is a consumer and the access controller is the provider. 25 An access controller can be represented by any node in the device tree and [all …]
/linux/Documentation/mm/damon/
H A D	monitoring_intervals_tuning_example.rst	17 monitor and visualize access patterns on the physical address space of a system 23 Let's start by capturing the access pattern snapshot on the physical address 27 the capturing of the snapshot, to show a meaningful time-wise access patterns. 35 Then, list the DAMON-found regions of different access patterns, sorted by the 36 "access temperature". "Access temperature" is a metric representing the 37 access-hotness of a region. It is calculated as a weighted sum of the access 38 frequency and the age of the region. If the access frequency is 0 %, the 44 # damo report access --sort_regions_by temperature 45 0 addr 16.052 GiB size 5.985 GiB access 0 % age 5.900 s # coldest 46 1 addr 22.037 GiB size 6.029 GiB access 0 % age 5.300 s [all …]
/linux/Documentation/admin-guide/LSM/
H A D	Smack.rst	9 Smack is the Simplified Mandatory Access Control Kernel. 10 Smack is a kernel based implementation of mandatory access 13 Smack is not the only Mandatory Access Control scheme 14 available for Linux. Those new to Mandatory Access Control 33 access to systems that use them as Smack does. 50 load the Smack access rules 53 report if a process with one label has access 85 Used to make access control decisions. In almost all cases 95 label does not allow all of the access permitted to a process 102 the Smack rule (more below) that permitted the write access [all …]
/linux/tools/perf/pmu-events/arch/arm64/
H A D	recommended.json	3 "PublicDescription": "Attributable Level 1 data cache access, read", 6 "BriefDescription": "L1D cache access, read" 9 "PublicDescription": "Attributable Level 1 data cache access, write", 12 "BriefDescription": "L1D cache access, write" 69 "PublicDescription": "Attributable Level 1 data or unified TLB access, read", 72 "BriefDescription": "L1D tlb access, read" 75 "PublicDescription": "Attributable Level 1 data or unified TLB access, write", 78 "BriefDescription": "L1D tlb access, write" 81 "PublicDescription": "Attributable Level 2 data cache access, read", 84 "BriefDescription": "L2D cache access, read" [all …]
/linux/drivers/net/ethernet/mellanox/mlxsw/
H A D	reg.h	`45 * Access: RW 68 * Access: RW 89 * Access: RW 96 * Access: RW 106 * Access: Index 130 * Access: Index 139 * Access: RW 152 * The following register defines the access to the filtering database. 154 * The access is optimized for bulk updates in which case more than one 168 * Access: Index [all …]`
/linux/tools/perf/pmu-events/arch/x86/skylakex/
H A D	uncore-memory.json	8 …"PublicDescription": "Counts all CAS (Column Access Select) read commands issued to DRAM on a per … 52 … the DRAM devices so that it can be read or written to with a CAS (Column Access Select) command.", 102 …"PublicDescription": "Counts all CAS (Column Access Select) read commands issued to DRAM on a per … 122 …"PublicDescription": "Counts CAS (Column Access Select) regular read commands issued to DRAM on a … 142 …"PublicDescription": "Counts CAS (Column Access Select) underfill read commands issued to DRAM due… 643 "BriefDescription": "RD_CAS Access to Rank 0; All Banks", 653 "BriefDescription": "RD_CAS Access to Rank 0; Bank 0", 662 "BriefDescription": "RD_CAS Access to Rank 0; Bank 1", 672 "BriefDescription": "RD_CAS Access to Rank 0; Bank 10", 682 "BriefDescription": "RD_CAS Access to Rank 0; Bank 11", [all …]
/linux/drivers/iommu/iommufd/
H A D	device.c	1068 * a valid cur_ioas (access->ioas). A caller passing in a valid new_ioas should 1071 static int iommufd_access_change_ioas(struct iommufd_access access, in iommufd_access_change_ioas() argument 1074 u32 iopt_access_list_id = access->iopt_access_list_id; in iommufd_access_change_ioas() 1075 struct iommufd_ioas cur_ioas = access->ioas; in iommufd_access_change_ioas() 1078 lockdep_assert_held(&access->ioas_lock); in iommufd_access_change_ioas() 1081 if (cur_ioas != access->ioas_unpin) in iommufd_access_change_ioas() 1089 * iommufd_access_unpin_pages() can continue using access->ioas_unpin. in iommufd_access_change_ioas() 1091 access->ioas = NULL; in iommufd_access_change_ioas() 1094 rc = iopt_add_access(&new_ioas->iopt, access); in iommufd_access_change_ioas() 1096 access->ioas = cur_ioas; in iommufd_access_change_ioas() [all …]
/linux/security/landlock/
H A D	audit.c	15 #include "access.h" 89 const access_mask_t access) in log_blockers() argument 91 const unsigned long access_mask = access; in log_blockers() 95 for_each_set_bit(access_bit, &access_mask, BITS_PER_TYPE(access)) { in log_blockers() 188 for (ssize_t i = ARRAY_SIZE(masks->access) - 1; i >= 0; i--) { in get_denied_layer() 189 if (masks->access[i] & access_request) { in get_denied_layer() 190 access_request &= masks->access[i]; in get_denied_layer() 208 .access[0] = LANDLOCK_ACCESS_FS_EXECUTE \| in test_get_denied_layer() 210 .access[1] = LANDLOCK_ACCESS_FS_READ_FILE \| in test_get_denied_layer() 212 .access[2] = LANDLOCK_ACCESS_FS_REMOVE_DIR, in test_get_denied_layer() [all …]
H A D	access.h	3 * Landlock - Access types and helpers 21 * All access rights that are denied by default whether they are handled or not 23 * entries when we need to get the absolute handled access masks, see 39 /* Makes sure all filesystem access rights can be stored. / 41 / Makes sure all network access rights can be stored. / 48 / Ruleset access masks. / 65 struct layer_access_masks - A boolean matrix of layers and access rights 67 * This has a bit for each combination of layer numbers and access rights. 68 * During access checks, it is used to represent the access rights for each 69 * layer which still need to be fulfilled. When all bits are 0, the access [all …]
/linux/tools/perf/pmu-events/arch/x86/cascadelakex/
H A D	uncore-memory.json	8 …"PublicDescription": "Counts all CAS (Column Access Select) read commands issued to DRAM on a per … 52 … the DRAM devices so that it can be read or written to with a CAS (Column Access Select) command.", 102 …"PublicDescription": "Counts all CAS (Column Access Select) read commands issued to DRAM on a per … 122 …"PublicDescription": "Counts CAS (Column Access Select) regular read commands issued to DRAM on a … 142 …"PublicDescription": "Counts CAS (Column Access Select) underfill read commands issued to DRAM due… 1019 "BriefDescription": "RD_CAS Access to Rank 0; All Banks", 1029 "BriefDescription": "RD_CAS Access to Rank 0; Bank 0", 1038 "BriefDescription": "RD_CAS Access to Rank 0; Bank 1", 1048 "BriefDescription": "RD_CAS Access to Rank 0; Bank 10", 1058 "BriefDescription": "RD_CAS Access to Rank 0; Bank 11", [all …]
/linux/arch/mips/include/asm/octeon/
H A D	cvmx-fau.h	`123 * @reg: FAU atomic register to access. 0 <= reg < 2048. 124 * - Step by 2 for 16 bit access. 125 * - Step by 4 for 32 bit access. 126 * - Step by 8 for 64 bit access. 143 * @reg: FAU atomic register to access. 0 <= reg < 2048. 144 * - Step by 2 for 16 bit access. 145 * - Step by 4 for 32 bit access. 146 * - Step by 8 for 64 bit access. 148 * Note: When performing 32 and 64 bit access, only the low 164 * @reg: FAU atomic register to access. 0 <= reg < 2048. [all …]`
/linux/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/
H A D	l3_cache.json	4 …"BriefDescription": "This event counts operations that cause a cache access to the L3 cache, as de… 8 …"BriefDescription": "This event counts access counted by L3D_CACHE that is a Memory-read operation… 13 … "BriefDescription": "This event counts operations that cause a cache access to the L3 cache." 18 "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_CACHE caused by demand access." 23 … "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_CACHE caused by demand read access." 28 … "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_CACHE caused by demand write access." 48 "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS caused by demand access." 53 … "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS caused by demand read access." 58 … "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS caused by demand write access." 78 "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_HIT caused by demand access." [all …]
H A D	tlb.json	12 …"BriefDescription": "This event counts operations that cause a TLB access to the L1D TLB. See L1D_… 16 …"BriefDescription": "This event counts operations that cause a TLB access to the L1I TLB. See L1I_… 24 …"BriefDescription": "This event counts operations that cause a TLB access to the L2D TLB. See L2D_… 28 … "BriefDescription": "This event counts data TLB access with at least one translation table walk." 32 …"BriefDescription": "This event counts instruction TLB access with at least one translation table … 37 … "BriefDescription": "This event counts operations that cause a TLB access to the L1I in 4KB page." 42 …"BriefDescription": "This event counts operations that cause a TLB access to the L1I in 64KB page." 47 … "BriefDescription": "This event counts operations that cause a TLB access to the L1I in 2MB page." 52 …"BriefDescription": "This event counts operations that cause a TLB access to the L1I in 32MB page." 57 …"BriefDescription": "This event counts operations that cause a TLB access to the L1I in 512MB page… [all …]
H A D	l1d_cache.json	8 …"BriefDescription": "This event counts operations that cause a cache access to the L1D cache. See … 20 "BriefDescription": "This event counts L1D CACHE caused by read access." 24 "BriefDescription": "This event counts L1D CACHE caused by write access." 28 "BriefDescription": "This event counts L1D_CACHE_REFILL caused by read access." 32 "BriefDescription": "This event counts L1D_CACHE_REFILL caused by write access." 37 "BriefDescription": "This event counts L1D_CACHE caused by demand access." 42 "BriefDescription": "This event counts L1D_CACHE caused by demand read access." 47 "BriefDescription": "This event counts L1D_CACHE caused by demand write access." 52 "BriefDescription": "This event counts L1D_CACHE_REFILL caused by demand access." 57 "BriefDescription": "This event counts L1D_CACHE_REFILL caused by demand read access." [all …]
H A D	l2_cache.json	4 …"BriefDescription": "This event counts operations that cause a cache access to the L2 cache. See L… 20 …"BriefDescription": "This event counts operations that cause a TLB access to the L2I TLB. See L2I_… 24 "BriefDescription": "This event counts L2D_CACHE caused by read access." 28 "BriefDescription": "This event counts L2D_CACHE caused by write access." 32 "BriefDescription": "This event counts L2D_CACHE_REFILL caused by read access." 36 "BriefDescription": "This event counts L2D_CACHE_REFILL caused by write access." 45 "BriefDescription": "This event counts L2D_CACHE caused by demand access." 50 "BriefDescription": "This event counts L2D_CACHE caused by demand read access." 55 "BriefDescription": "This event counts L2D_CACHE caused by demand write access." 65 "BriefDescription": "This event counts L2D_CACHE_REFILL caused by demand access." [all …]
/linux/tools/testing/selftests/bpf/verifier/
H A D	direct_value_access.c	`2 "direct map access, write test 1", 14 "direct map access, write test 2", 26 "direct map access, write test 3", 38 "direct map access, write test 4", 50 "direct map access, write test 5", 62 "direct map access, write test 6", 75 "direct map access, write test 7", 84 .errstr = "invalid access to map value pointer, value_size=48 off=4294967295", 87 "direct map access, write test 8", 99 "direct map access, writ [all...]`
H A D	ctx_skb.c	`2 "access skb fields ok", 33 "access skb fields bad1", 38 .errstr = "invalid bpf_context access", 42 "access skb fields bad2", 63 "access skb fields bad3", 85 "access skb fields bad4", 108 "invalid access __sk_buff family", 114 .errstr = "invalid bpf_context access", 118 "invalid access __sk_buff remote_ip4", 124 .errstr = "invalid bpf_context access", [all …]`
/linux/tools/perf/pmu-events/arch/x86/broadwell/
H A D	uncore-cache.json	3 … "BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state", 8 … "PublicDescription": "L3 Lookup any request that access cache and found line in E or S-state.", 13 "BriefDescription": "L3 Lookup any request that access cache and found line in I-state", 18 "PublicDescription": "L3 Lookup any request that access cache and found line in I-state.", 23 "BriefDescription": "L3 Lookup any request that access cache and found line in M-state", 28 "PublicDescription": "L3 Lookup any request that access cache and found line in M-state.", 33 "BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state", 38 … "PublicDescription": "L3 Lookup any request that access cache and found line in MESI-state.", 43 … "BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state", 48 … "PublicDescription": "L3 Lookup read request that access cache and found line in E or S-state.", [all …]
/linux/include/linux/
H A D	instrumented.h	4 * This header provides generic wrappers for memory access instrumentation that 18 * instrument_read - instrument regular read access 19 * @v: address of access 20 * @size: size of access 22 * Instrument a regular read access. The instrumentation should be inserted 32 * instrument_write - instrument regular write access 33 * @v: address of access 34 * @size: size of access 36 * Instrument a regular write access. The instrumentation should be inserted 46 * instrument_read_write - instrument regular read-write access [all …]
H A D	kcsan-checks.h	3 * KCSAN access checks and modifiers. These can be used to explicitly check 16 /* Access types -- if KCSAN_ACCESS_WRITE is not set, the access is a read. / 17 #define KCSAN_ACCESS_WRITE (1 << 0) / Access is a write. / 19 #define KCSAN_ACCESS_ATOMIC (1 << 2) / Access is atomic. / 21 #define KCSAN_ACCESS_ASSERT (1 << 3) / Access is an assertion. / 22 #define KCSAN_ACCESS_SCOPED (1 << 4) / Access is a scoped access. / 27 to validate access to an address. Never use these in header files! 31 * __kcsan_check_access - check generic access for races 33 * @ptr: address of access 34 * @size: size of access [all …]
/linux/tools/perf/pmu-events/arch/x86/skylake/
H A D	uncore-cache.json	3 … "BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state", 8 … "PublicDescription": "L3 Lookup any request that access cache and found line in E or S-state.", 13 "BriefDescription": "L3 Lookup any request that access cache and found line in I-state", 18 "PublicDescription": "L3 Lookup any request that access cache and found line in I-state.", 23 "BriefDescription": "L3 Lookup any request that access cache and found line in M-state", 28 "PublicDescription": "L3 Lookup any request that access cache and found line in M-state.", 33 "BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state", 38 … "PublicDescription": "L3 Lookup any request that access cache and found line in MESI-state.", 43 … "BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state", 48 … "PublicDescription": "L3 Lookup read request that access cache and found line in E or S-state.", [all …]
/linux/tools/perf/pmu-events/arch/x86/ivytown/
H A D	uncore-memory.json	542 "BriefDescription": "RD_CAS Access to Rank 0; Bank 0", 551 "BriefDescription": "RD_CAS Access to Rank 0; Bank 1", 560 "BriefDescription": "RD_CAS Access to Rank 0; Bank 2", 569 "BriefDescription": "RD_CAS Access to Rank 0; Bank 3", 578 "BriefDescription": "RD_CAS Access to Rank 0; Bank 4", 587 "BriefDescription": "RD_CAS Access to Rank 0; Bank 5", 596 "BriefDescription": "RD_CAS Access to Rank 0; Bank 6", 605 "BriefDescription": "RD_CAS Access to Rank 0; Bank 7", 614 "BriefDescription": "RD_CAS Access to Rank 1; Bank 0", 623 "BriefDescription": "RD_CAS Access to Rank 1; Bank 1", [all …]

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