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/linux/drivers/iio/adc/
H A Dpalmas_gpadc.c3 * palmas-adc.c -- TI PALMAS GPADC.
131 static struct palmas_adc_event *palmas_gpadc_get_event(struct palmas_gpadc *adc, in palmas_gpadc_get_event() argument
135 if (adc_chan == adc->event0.channel && dir == adc->event0.direction) in palmas_gpadc_get_event()
136 return &adc->event0; in palmas_gpadc_get_event()
138 if (adc_chan == adc->event1.channel && dir == adc->event1.direction) in palmas_gpadc_get_event()
139 return &adc->event1; in palmas_gpadc_get_event()
144 static bool palmas_gpadc_channel_is_freerunning(struct palmas_gpadc *adc, in palmas_gpadc_channel_is_freerunning() argument
147 return palmas_gpadc_get_event(adc, adc_chan, IIO_EV_DIR_RISING) || in palmas_gpadc_channel_is_freerunning()
148 palmas_gpadc_get_event(adc, adc_chan, IIO_EV_DIR_FALLING); in palmas_gpadc_channel_is_freerunning()
175 static int palmas_disable_auto_conversion(struct palmas_gpadc *adc) in palmas_disable_auto_conversion() argument
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H A Dimx8qxp-adc.c3 * NXP i.MX8QXP ADC driver
30 #define ADC_DRIVER_NAME "imx8qxp-adc"
46 /* ADC bit shift */
75 /* ADC PARAMETER*/
97 /* Serialise ADC channel reads */
123 static void imx8qxp_adc_reset(struct imx8qxp_adc *adc) in imx8qxp_adc_reset() argument
128 ctrl = readl(adc->regs + IMX8QXP_ADR_ADC_CTRL); in imx8qxp_adc_reset()
130 writel(ctrl, adc->regs + IMX8QXP_ADR_ADC_CTRL); in imx8qxp_adc_reset()
133 writel(ctrl, adc->regs + IMX8QXP_ADR_ADC_CTRL); in imx8qxp_adc_reset()
137 writel(ctrl, adc->regs + IMX8QXP_ADR_ADC_CTRL); in imx8qxp_adc_reset()
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H A Drzg2l_adc.c14 #include <linux/iio/adc-helpers.h>
26 #define DRIVER_NAME "rzg2l-adc"
60 * struct rzg2l_adc_hw_params - ADC hardware specific parameters
61 * @default_adsmp: default ADC sampling period (see ADM3 register); index 0 is
63 * @adsmp_mask: ADC sampling period mask (see ADM3 register)
65 * @default_adcmp: default ADC cmp (see ADM3 register)
96 * struct rzg2l_adc_channel - ADC channel descriptor
97 * @name: ADC channel name
98 * @type: ADC channel type
117 static unsigned int rzg2l_adc_readl(struct rzg2l_adc *adc, u32 reg) in rzg2l_adc_readl() argument
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H A Dti-adc12138.c3 * ADC12130/ADC12132/ADC12138 12-bit plus sign ADC driver
52 * Maximum size needed: 16x 2 bytes ADC data + 8 bytes timestamp.
128 static int adc12138_mode_programming(struct adc12138 *adc, u8 mode, in adc12138_mode_programming() argument
132 .tx_buf = adc->tx_buf, in adc12138_mode_programming()
133 .rx_buf = adc->rx_buf, in adc12138_mode_programming()
139 if (adc->id != adc12138) in adc12138_mode_programming()
142 adc->tx_buf[0] = mode; in adc12138_mode_programming()
144 ret = spi_sync_transfer(adc->spi, &xfer, 1); in adc12138_mode_programming()
148 memcpy(rx_buf, adc->rx_buf, len); in adc12138_mode_programming()
153 static int adc12138_read_status(struct adc12138 *adc) in adc12138_read_status() argument
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H A Dingenic-adc.c3 * ADC driver for the Ingenic JZ47xx SoCs
6 * based on drivers/mfd/jz4740-adc.c
9 #include <dt-bindings/iio/adc/ingenic,adc.h>
102 int (*init_clk_div)(struct device *dev, struct ingenic_adc *adc);
116 struct ingenic_adc *adc = iio_priv(iio_dev); in ingenic_adc_set_adcmd() local
118 mutex_lock(&adc->lock); in ingenic_adc_set_adcmd()
121 readl(adc->base + JZ_ADC_REG_ADCMD); in ingenic_adc_set_adcmd()
128 adc->base + JZ_ADC_REG_ADCMD); in ingenic_adc_set_adcmd()
134 adc->base + JZ_ADC_REG_ADCMD); in ingenic_adc_set_adcmd()
142 adc->base + JZ_ADC_REG_ADCMD); in ingenic_adc_set_adcmd()
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H A Dstm32-dfsdm-adc.c3 * This file is the ADC part of the STM32 DFSDM driver
12 #include <linux/iio/adc/stm32-dfsdm-adc.h>
80 /* ADC specific */
319 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); in stm32_dfsdm_compute_all_osrs() local
320 struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[adc->fl_id]; in stm32_dfsdm_compute_all_osrs()
340 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); in stm32_dfsdm_start_channel() local
341 struct regmap *regmap = adc->dfsdm->regmap; in stm32_dfsdm_start_channel()
346 for_each_set_bit(bit, &adc->smask, sizeof(adc->smask) * BITS_PER_BYTE) { in stm32_dfsdm_start_channel()
360 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); in stm32_dfsdm_stop_channel() local
361 struct regmap *regmap = adc->dfsdm->regmap; in stm32_dfsdm_stop_channel()
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H A Dmcp3911.c110 int (*config)(struct mcp3911 *adc, bool external_vref);
111 int (*get_osr)(struct mcp3911 *adc, u32 *val);
112 int (*set_osr)(struct mcp3911 *adc, u32 val);
113 int (*enable_offset)(struct mcp3911 *adc, bool enable);
114 int (*get_offset)(struct mcp3911 *adc, int channel, int *val);
115 int (*set_offset)(struct mcp3911 *adc, int channel, int val);
116 int (*set_scale)(struct mcp3911 *adc, int channel, u32 val);
117 int (*get_raw)(struct mcp3911 *adc, int channel, int *val);
137 static int mcp3911_read(struct mcp3911 *adc, u8 reg, u32 *val, u8 len) in mcp3911_read() argument
141 reg = MCP3911_REG_READ(reg, adc->dev_addr); in mcp3911_read()
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H A Dqcom-spmi-adc5.c10 #include <linux/iio/adc/qcom-vadc-common.h>
104 * struct adc5_channel_prop - ADC channel property.
113 * @avg_samples: ability to provide single result from the ADC
133 * struct adc5_chip - ADC private structure.
136 * @base: base address for the ADC peripheral.
137 * @nchannels: number of ADC channels.
138 * @chan_props: array of ADC channel properties.
141 * @complete: ADC result notification after interrupt is received.
142 * @lock: ADC lock for access to the peripheral.
158 static int adc5_read(struct adc5_chip *adc, u16 offset, u8 *data, int len) in adc5_read() argument
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H A Dad7944.c3 * Analog Devices AD7944/85/86 PulSAR ADC family driver.
174 * is only one supported provider, namely the ADI PULSAR ADC HDL project,
185 static int ad7944_3wire_cs_mode_init_msg(struct device *dev, struct ad7944_adc *adc, in ad7944_3wire_cs_mode_init_msg() argument
188 unsigned int t_conv_ns = adc->always_turbo ? adc->timing_spec->turbo_conv_ns in ad7944_3wire_cs_mode_init_msg()
189 : adc->timing_spec->conv_ns; in ad7944_3wire_cs_mode_init_msg()
190 struct spi_transfer *xfers = adc->xfers; in ad7944_3wire_cs_mode_init_msg()
208 xfers[2].rx_buf = &adc->sample.raw; in ad7944_3wire_cs_mode_init_msg()
212 spi_message_init_with_transfers(&adc->msg, xfers, 3); in ad7944_3wire_cs_mode_init_msg()
214 return devm_spi_optimize_message(dev, adc->spi, &adc->msg); in ad7944_3wire_cs_mode_init_msg()
217 static int ad7944_4wire_mode_init_msg(struct device *dev, struct ad7944_adc *adc, in ad7944_4wire_mode_init_msg() argument
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H A Dti-adc084s021.c5 * Driver for Texas Instruments' ADC084S021 ADC chip.
68 * adc084s021_adc_conversion() - Read an ADC channel and return its value.
70 * @adc: The ADC SPI data.
73 static int adc084s021_adc_conversion(struct adc084s021 *adc, __be16 *data) in adc084s021_adc_conversion() argument
75 int n_words = (adc->spi_trans.len >> 1) - 1; /* Discard first word */ in adc084s021_adc_conversion()
79 ret = spi_sync(adc->spi, &adc->message); in adc084s021_adc_conversion()
84 *(data + i) = adc->rx_buf[i + 1]; in adc084s021_adc_conversion()
93 struct adc084s021 *adc = iio_priv(indio_dev); in adc084s021_read_raw() local
102 ret = regulator_enable(adc->reg); in adc084s021_read_raw()
108 adc->tx_buf[0] = channel->channel << 3; in adc084s021_read_raw()
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H A Dlpc18xx_adc.c3 * IIO ADC driver for NXP LPC18xx ADC
26 /* LPC18XX ADC registers and bits */
69 static int lpc18xx_adc_read_chan(struct lpc18xx_adc *adc, unsigned int ch) in lpc18xx_adc_read_chan() argument
74 reg = adc->cr_reg | BIT(ch) | LPC18XX_ADC_CR_START_NOW; in lpc18xx_adc_read_chan()
75 writel(reg, adc->base + LPC18XX_ADC_CR); in lpc18xx_adc_read_chan()
77 ret = readl_poll_timeout(adc->base + LPC18XX_ADC_GDR, reg, in lpc18xx_adc_read_chan()
80 dev_warn(adc->dev, "adc read timed out\n"); in lpc18xx_adc_read_chan()
91 struct lpc18xx_adc *adc = iio_priv(indio_dev); in lpc18xx_adc_read_raw() local
95 mutex_lock(&adc->lock); in lpc18xx_adc_read_raw()
96 *val = lpc18xx_adc_read_chan(adc, chan->channel); in lpc18xx_adc_read_raw()
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H A Dmcp3564.c3 * IIO driver for MCP356X/MCP356XR and MCP346X/MCP346XR series ADC chip family
14 …MCP3461-2-4-Two-Four-Eight-Channel-153.6-ksps-Low-Noise-16-Bit-Delta-Sigma-ADC-Data-Sheet-20006180…
64 * ADC Output Data Format 32-bit (25-bit right justified data + Channel ID):
65 * CHID[3:0] + SGN extension (4 bits) + 24-bit ADC data.
70 * ADC Output Data Format 32-bit (25-bit right justified data):
71 * SGN extension (8-bit) + 24-bit ADC data.
76 * ADC Output Data Format 32-bit (24-bit left justified data):
77 * 24-bit ADC data + 0x00 (8-bit).
78 * It does not allow overrange (ADC code locked to 0xFFFFFF or 0x800000).
82 * ADC Output Data Format 24-bit (default ADC coding):
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H A Dti-adc0832.c3 * ADC0831/ADC0832/ADC0834/ADC0838 8-bit ADC driver
33 * Max size needed: 16x 1 byte ADC data + 8 bytes timestamp
120 static int adc0831_adc_conversion(struct adc0832 *adc) in adc0831_adc_conversion() argument
122 struct spi_device *spi = adc->spi; in adc0831_adc_conversion()
125 ret = spi_read(spi, &adc->rx_buf, 2); in adc0831_adc_conversion()
132 return (adc->rx_buf[0] << 2 & 0xff) | (adc->rx_buf[1] >> 6); in adc0831_adc_conversion()
135 static int adc0832_adc_conversion(struct adc0832 *adc, int channel, in adc0832_adc_conversion() argument
138 struct spi_device *spi = adc->spi; in adc0832_adc_conversion()
140 .tx_buf = adc->tx_buf, in adc0832_adc_conversion()
141 .rx_buf = adc->rx_buf, in adc0832_adc_conversion()
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H A Dmxs-lradc-adc.c3 * Freescale MXS LRADC ADC driver
134 struct mxs_lradc_adc *adc = iio_priv(iio_dev); in mxs_lradc_adc_read_single() local
135 struct mxs_lradc *lradc = adc->lradc; in mxs_lradc_adc_read_single()
147 reinit_completion(&adc->completion); in mxs_lradc_adc_read_single()
156 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_read_single()
157 writel(0x1, adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_read_single()
160 if (test_bit(chan, &adc->is_divided)) in mxs_lradc_adc_read_single()
162 adc->base + LRADC_CTRL2 + STMP_OFFSET_REG_SET); in mxs_lradc_adc_read_single()
165 adc->base + LRADC_CTRL2 + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_read_single()
169 adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_read_single()
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H A Dmax1241.c3 * MAX1241 low-power, 12-bit serial ADC
41 static int max1241_read(struct max1241 *adc) in max1241_read() argument
57 .rx_buf = &adc->data, in max1241_read()
62 return spi_sync_transfer(adc->spi, xfers, ARRAY_SIZE(xfers)); in max1241_read()
70 struct max1241 *adc = iio_priv(indio_dev); in max1241_read_raw() local
74 mutex_lock(&adc->lock); in max1241_read_raw()
76 if (adc->shutdown) { in max1241_read_raw()
77 gpiod_set_value(adc->shutdown, 0); in max1241_read_raw()
79 ret = max1241_read(adc); in max1241_read_raw()
80 gpiod_set_value(adc->shutdown, 1); in max1241_read_raw()
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H A Dmcp320x.c8 * Driver for following ADC chips from Microchip Technology's:
72 * struct mcp320x - Microchip SPI ADC instance
74 * @msg: SPI message to select a channel and receive a value from the ADC
80 * @chip_info: ADC properties
120 static int mcp320x_adc_conversion(struct mcp320x *adc, u8 channel, in mcp320x_adc_conversion() argument
125 if (adc->chip_info->conv_time) { in mcp320x_adc_conversion()
126 ret = spi_sync(adc->spi, &adc->start_conv_msg); in mcp320x_adc_conversion()
130 usleep_range(adc->chip_info->conv_time, in mcp320x_adc_conversion()
131 adc->chip_info->conv_time + 100); in mcp320x_adc_conversion()
134 memset(&adc->rx_buf, 0, sizeof(adc->rx_buf)); in mcp320x_adc_conversion()
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H A Drn5t618-adc.c3 * ADC driver for the RICOH RN5T618 power management chip family
83 struct rn5t618_adc_data *adc = data; in rn5t618_adc_irq() local
88 regmap_write(adc->rn5t618->regmap, RN5T618_IR_ADC1, 0); in rn5t618_adc_irq()
89 regmap_write(adc->rn5t618->regmap, RN5T618_IR_ADC2, 0); in rn5t618_adc_irq()
91 ret = regmap_read(adc->rn5t618->regmap, RN5T618_IR_ADC3, &r); in rn5t618_adc_irq()
93 dev_err(adc->dev, "failed to read IRQ status: %d\n", ret); in rn5t618_adc_irq()
95 regmap_write(adc->rn5t618->regmap, RN5T618_IR_ADC3, 0); in rn5t618_adc_irq()
98 complete(&adc->conv_completion); in rn5t618_adc_irq()
107 struct rn5t618_adc_data *adc = iio_priv(iio_dev); in rn5t618_adc_read() local
120 ret = regmap_update_bits(adc->rn5t618->regmap, RN5T618_ADCCNT3, in rn5t618_adc_read()
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H A Dti-ads8344.c3 * ADS8344 16-bit 8-Channel ADC driver
26 * Lock protecting access to adc->tx_buff and rx_buff,
76 static int ads8344_adc_conversion(struct ads8344 *adc, int channel, in ads8344_adc_conversion() argument
79 struct spi_device *spi = adc->spi; in ads8344_adc_conversion()
82 adc->tx_buf = ADS8344_START; in ads8344_adc_conversion()
84 adc->tx_buf |= ADS8344_SINGLE_END; in ads8344_adc_conversion()
85 adc->tx_buf |= ADS8344_CHANNEL(channel); in ads8344_adc_conversion()
86 adc->tx_buf |= ADS8344_CLOCK_INTERNAL; in ads8344_adc_conversion()
88 ret = spi_write(spi, &adc->tx_buf, 1); in ads8344_adc_conversion()
94 ret = spi_read(spi, adc->rx_buf, sizeof(adc->rx_buf)); in ads8344_adc_conversion()
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H A Dqcom-pm8xxx-xoadc.c7 * specific-purpose and general purpose ADC converters and channels.
13 #include <linux/iio/adc/qcom-vadc-common.h>
27 * Qualcomm tree. Their kernel has two out-of-tree drivers for the ADC:
29 * drivers/hwmon/pm8xxx-adc.c
57 /* Proper ADC registers */
99 * On a later ADC the decimation factors are defined as
167 * ADC code to the value that IIO expects, in uV or millicelsius
309 * include/linux/mfd/pm8xxx/pm8xxx-adc.h
371 * struct pm8xxx_chan_info - ADC channel information
418 struct pm8xxx_xoadc *adc = iio_priv(indio_dev); in pm8xxx_eoc_irq() local
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H A Dmcp3422.c95 static int mcp3422_update_config(struct mcp3422 *adc, u8 newconfig) in mcp3422_update_config() argument
99 ret = i2c_master_send(adc->i2c, &newconfig, 1); in mcp3422_update_config()
101 adc->config = newconfig; in mcp3422_update_config()
108 static int mcp3422_read(struct mcp3422 *adc, int *value, u8 *config) in mcp3422_read() argument
111 u8 sample_rate = MCP3422_SAMPLE_RATE(adc->config); in mcp3422_read()
116 ret = i2c_master_recv(adc->i2c, buf, 4); in mcp3422_read()
120 ret = i2c_master_recv(adc->i2c, buf, 3); in mcp3422_read()
130 static int mcp3422_read_channel(struct mcp3422 *adc, in mcp3422_read_channel() argument
137 mutex_lock(&adc->lock); in mcp3422_read_channel()
139 if (req_channel != MCP3422_CHANNEL(adc->config)) { in mcp3422_read_channel()
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/linux/Documentation/devicetree/bindings/iio/adc/
H A Dst,stm32-adc.yaml4 $id: http://devicetree.org/schemas/iio/adc/st,stm32-adc.yaml#
7 title: STMicroelectronics STM32 ADC
10 STM32 ADC is a successive approximation analog-to-digital converter.
12 in single, continuous, scan or discontinuous mode. Result of the ADC is
19 Each STM32 ADC block can have up to 3 ADC instances.
27 - st,stm32f4-adc-core
28 - st,stm32h7-adc-core
29 - st,stm32mp1-adc-core
30 - st,stm32mp13-adc-core
37 One or more interrupts for ADC block, depending on part used:
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H A Dqcom,pm8018-adc.yaml4 $id: http://devicetree.org/schemas/iio/adc/qcom,pm8018-adc.yaml#
13 The Qualcomm PM8xxx PMICs contain a HK/XO ADC (Housekeeping/Crystal
14 oscillator ADC) encompassing PM8018, PM8038, PM8058 and PM8921.
19 - qcom,pm8018-adc
20 - qcom,pm8038-adc
21 - qcom,pm8058-adc
22 - qcom,pm8921-adc
27 ADC base address in the PMIC, typically 0x197.
62 - adc-channel@c
63 - adc-channel@d
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H A Dti,am3359-adc.yaml4 $id: http://devicetree.org/schemas/iio/adc/ti,am3359-adc.yaml#
7 title: TI AM3359 ADC
16 - ti,am3359-adc
17 - ti,am4372-adc
20 - ti,am654-adc
21 - const: ti,am3359-adc
26 ti,adc-channels:
27 description: List of analog inputs available for ADC. AIN0 = 0, AIN1 = 1 and
34 description: List of open delays for each channel of ADC in the order of
35 ti,adc-channels. The value corresponds to the number of ADC clock cycles
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H A Dingenic,adc.yaml5 $id: http://devicetree.org/schemas/iio/adc/ingenic,adc.yaml#
8 title: Ingenic JZ47xx ADC controller IIO
14 Industrial I/O subsystem bindings for ADC controller found in
17 ADC clients must use the format described in
19 giving a phandle and IIO specifier pair ("io-channels") to the ADC controller.
24 - ingenic,jz4725b-adc
25 - ingenic,jz4740-adc
26 - ingenic,jz4760-adc
27 - ingenic,jz4760b-adc
28 - ingenic,jz4770-adc
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/linux/drivers/hwmon/
H A Dadcxx.c11 * ADC<bb><c>S<sss>, where
18 * http://www.national.com/ds/DC/ADC<bb><c>S<sss>.pdf
52 struct adcxx *adc = spi_get_drvdata(spi); in adcxx_show() local
58 if (mutex_lock_interruptible(&adc->lock)) in adcxx_show()
61 if (adc->channels == 1) { in adcxx_show()
77 value = value * adc->reference >> 12; in adcxx_show()
80 mutex_unlock(&adc->lock); in adcxx_show()
95 struct adcxx *adc = spi_get_drvdata(spi); in adcxx_max_show() local
98 if (mutex_lock_interruptible(&adc->lock)) in adcxx_max_show()
101 reference = adc->reference; in adcxx_max_show()
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