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/linux/drivers/video/logo/
H A Dlogo_linux_mono.pbm4 1 1 1 1 1 1 1 1 1 1
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H A Dlogo_superh_mono.pbm4 1 1 1 1 1 1 1 1 1 1
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/linux/arch/mips/include/asm/octeon/
H A Dcvmx-fpa-defs.h36 #define CVMX_FPA_FPF1_MARKS CVMX_FPA_FPFX_MARKS(1)
45 #define CVMX_FPA_FPFX_MARKS(offset) (CVMX_ADD_IO_SEG(0x0001180028000008ull) + ((offset) & 7) * 8 - 8*1)
46 #define CVMX_FPA_FPFX_SIZE(offset) (CVMX_ADD_IO_SEG(0x0001180028000060ull) + ((offset) & 7) * 8 - 8*1)
54 #define CVMX_FPA_QUE1_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(1)
91 uint64_t frd:1;
92 uint64_t fpf0:1;
93 uint64_t fpf1:1;
94 uint64_t ffr:1;
95 uint64_t fdr:1;
97 uint64_t fdr:1;
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H A Dcvmx-npi-defs.h32 #define CVMX_NPI_BASE_ADDR_INPUT1 CVMX_NPI_BASE_ADDR_INPUTX(1)
37 #define CVMX_NPI_BASE_ADDR_OUTPUT1 CVMX_NPI_BASE_ADDR_OUTPUTX(1)
43 #define CVMX_NPI_BUFF_SIZE_OUTPUT1 CVMX_NPI_BUFF_SIZE_OUTPUTX(1)
70 #define CVMX_NPI_NUM_DESC_OUTPUT1 CVMX_NPI_NUM_DESC_OUTPUTX(1)
79 #define CVMX_NPI_P1_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(1)
80 #define CVMX_NPI_P1_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(1)
81 #define CVMX_NPI_P1_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(1)
82 #define CVMX_NPI_P1_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(1)
146 #define CVMX_NPI_SIZE_INPUT1 CVMX_NPI_SIZE_INPUTX(1)
183 uint64_t csr_bs:1;
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H A Dcvmx-npei-defs.h146 uint32_t ca:1;
148 uint32_t addr_v:1;
150 uint32_t addr_v:1;
152 uint32_t ca:1;
163 uint64_t pkt_rdf:1;
165 uint64_t pcr_gim:1;
166 uint64_t pkt_pif:1;
167 uint64_t pcsr_int:1;
168 uint64_t pcsr_im:1;
169 uint64_t pcsr_cnt:1;
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H A Dcvmx-pci-defs.h67 #define CVMX_PCI_DMA_CNT1 CVMX_PCI_DMA_CNTX(1)
68 #define CVMX_PCI_DMA_CNTX(offset) (0x00000000000000A0ull + ((offset) & 1) * 8)
70 #define CVMX_PCI_DMA_INT_LEV1 CVMX_PCI_DMA_INT_LEVX(1)
71 #define CVMX_PCI_DMA_INT_LEVX(offset) (0x00000000000000A4ull + ((offset) & 1) * 8)
73 #define CVMX_PCI_DMA_TIME1 CVMX_PCI_DMA_TIMEX(1)
74 #define CVMX_PCI_DMA_TIMEX(offset) (0x00000000000000B0ull + ((offset) & 1) * 4)
76 #define CVMX_PCI_INSTR_COUNT1 CVMX_PCI_INSTR_COUNTX(1)
86 #define CVMX_PCI_PKTS_SENT1 CVMX_PCI_PKTS_SENTX(1)
91 #define CVMX_PCI_PKTS_SENT_INT_LEV1 CVMX_PCI_PKTS_SENT_INT_LEVX(1)
96 #define CVMX_PCI_PKTS_SENT_TIME1 CVMX_PCI_PKTS_SENT_TIMEX(1)
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/linux/drivers/gpu/drm/amd/include/asic_reg/mmhub/
H A Dmmhub_9_4_1_offset.h29 #define mmDAGB0_RDCLI0_BASE_IDX 1
31 #define mmDAGB0_RDCLI1_BASE_IDX 1
33 #define mmDAGB0_RDCLI2_BASE_IDX 1
35 #define mmDAGB0_RDCLI3_BASE_IDX 1
37 #define mmDAGB0_RDCLI4_BASE_IDX 1
39 #define mmDAGB0_RDCLI5_BASE_IDX 1
41 #define mmDAGB0_RDCLI6_BASE_IDX 1
43 #define mmDAGB0_RDCLI7_BASE_IDX 1
45 #define mmDAGB0_RDCLI8_BASE_IDX 1
47 #define mmDAGB0_RDCLI9_BASE_IDX 1
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H A Dmmhub_2_3_0_offset.h29 #define mmDAGB0_RDCLI0_BASE_IDX 1
31 #define mmDAGB0_RDCLI1_BASE_IDX 1
33 #define mmDAGB0_RDCLI2_BASE_IDX 1
35 #define mmDAGB0_RDCLI3_BASE_IDX 1
37 #define mmDAGB0_RDCLI4_BASE_IDX 1
39 #define mmDAGB0_RDCLI5_BASE_IDX 1
41 #define mmDAGB0_RDCLI6_BASE_IDX 1
43 #define mmDAGB0_RDCLI7_BASE_IDX 1
45 #define mmDAGB0_RDCLI8_BASE_IDX 1
47 #define mmDAGB0_RDCLI9_BASE_IDX 1
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H A Dmmhub_3_0_1_offset.h31 #define regDAGB0_RDCLI0_BASE_IDX 1
33 #define regDAGB0_RDCLI1_BASE_IDX 1
35 #define regDAGB0_RDCLI2_BASE_IDX 1
37 #define regDAGB0_RDCLI3_BASE_IDX 1
39 #define regDAGB0_RDCLI4_BASE_IDX 1
41 #define regDAGB0_RDCLI5_BASE_IDX 1
43 #define regDAGB0_RDCLI6_BASE_IDX 1
45 #define regDAGB0_RDCLI7_BASE_IDX 1
47 #define regDAGB0_RDCLI8_BASE_IDX 1
49 #define regDAGB0_RDCLI9_BASE_IDX 1
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H A Dmmhub_3_3_0_offset.h31 #define regDAGB0_RDCLI0_BASE_IDX 1
33 #define regDAGB0_RDCLI1_BASE_IDX 1
35 #define regDAGB0_RDCLI2_BASE_IDX 1
37 #define regDAGB0_RDCLI3_BASE_IDX 1
39 #define regDAGB0_RDCLI4_BASE_IDX 1
41 #define regDAGB0_RDCLI5_BASE_IDX 1
43 #define regDAGB0_RDCLI6_BASE_IDX 1
45 #define regDAGB0_RDCLI7_BASE_IDX 1
47 #define regDAGB0_RDCLI8_BASE_IDX 1
49 #define regDAGB0_RDCLI9_BASE_IDX 1
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/linux/drivers/gpu/drm/amd/display/dc/dml/
H A Ddc_features.h29 #define DC__PRESENT 1
30 #define DC__PRESENT__1 1
40 #define DC__NUM_DPP__4 1
41 #define DC__NUM_DPP__0_PRESENT 1
42 #define DC__NUM_DPP__1_PRESENT 1
43 #define DC__NUM_DPP__2_PRESENT 1
44 #define DC__NUM_DPP__3_PRESENT 1
46 #define DC__NUM_DPP__MAX__8 1
48 #define DC__PIPE_10BIT__0 1
49 #define DC__PIPE_10BIT__MAX 1
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/linux/include/uapi/linux/
H A Dmap_to_7segment.h58 #define BIT_SEG7_B 1
97 _SEG7('!',0,0,0,0,1,1,0), _SEG7('"',0,1,0,0,0,1,0), _SEG7('#',0,1,1,0,1,1,0),\
98 _SEG7('$',1,
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H A Dmap_to_14segment.h65 #define BIT_SEG14_B 1
120 _SEG14('!', 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0), \
121 _SEG14('"', 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0), \
122 _SEG14('#', 0, 1, 1, 1, 0, 0, 1, 1,
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/linux/drivers/pinctrl/mvebu/
H A Dpinctrl-kirkwood.c20 ((f6180 << 0) | (f6190 << 1) | (f6192 << 2) | \
25 VARIANT_MV88F6180 = V(1, 0, 0, 0, 0, 0, 0),
26 VARIANT_MV88F6190 = V(0, 1, 0, 0, 0, 0, 0),
27 VARIANT_MV88F6192 = V(0, 0, 1, 0, 0, 0, 0),
28 VARIANT_MV88F6281 = V(0, 0, 0, 1, 0, 0, 0),
29 VARIANT_MV88F6282 = V(0, 0, 0, 0, 1, 0, 0),
30 VARIANT_MV98DX4122 = V(0, 0, 0, 0, 0, 1, 0),
31 VARIANT_MV98DX1135 = V(0, 0, 0, 0, 0, 0, 1),
36 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1,
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/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_4_0_0_offset.h31 #define regUVD_TOP_CTRL_BASE_IDX 1
33 #define regUVD_CGC_GATE_BASE_IDX 1
35 #define regUVD_CGC_CTRL_BASE_IDX 1
37 #define regAVM_SUVD_CGC_GATE_BASE_IDX 1
39 #define regCDEFE_SUVD_CGC_GATE_BASE_IDX 1
41 #define regEFC_SUVD_CGC_GATE_BASE_IDX 1
43 #define regENT_SUVD_CGC_GATE_BASE_IDX 1
45 #define regIME_SUVD_CGC_GATE_BASE_IDX 1
47 #define regPPU_SUVD_CGC_GATE_BASE_IDX 1
49 #define regSAOE_SUVD_CGC_GATE_BASE_IDX 1
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H A Dvcn_4_0_5_offset.h32 #define regUVD_CGC_GATE_BASE_IDX 1
34 #define regUVD_CGC_CTRL_BASE_IDX 1
36 #define regAVM_SUVD_CGC_GATE_BASE_IDX 1
38 #define regCDEFE_SUVD_CGC_GATE_BASE_IDX 1
40 #define regEFC_SUVD_CGC_GATE_BASE_IDX 1
42 #define regENT_SUVD_CGC_GATE_BASE_IDX 1
44 #define regIME_SUVD_CGC_GATE_BASE_IDX 1
46 #define regPPU_SUVD_CGC_GATE_BASE_IDX 1
48 #define regSAOE_SUVD_CGC_GATE_BASE_IDX 1
50 #define regSCM_SUVD_CGC_GATE_BASE_IDX 1
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H A Dvcn_5_0_0_offset.h31 #define regUVD_TOP_CTRL_BASE_IDX 1
33 #define regUVD_CGC_GATE_BASE_IDX 1
35 #define regUVD_CGC_CTRL_BASE_IDX 1
37 #define regAVM_SUVD_CGC_GATE_BASE_IDX 1
39 #define regEFC_SUVD_CGC_GATE_BASE_IDX 1
41 #define regENT_SUVD_CGC_GATE_BASE_IDX 1
43 #define regIME_SUVD_CGC_GATE_BASE_IDX 1
45 #define regPPU_SUVD_CGC_GATE_BASE_IDX 1
47 #define regSAOE_SUVD_CGC_GATE_BASE_IDX 1
49 #define regSCM_SUVD_CGC_GATE_BASE_IDX 1
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/linux/arch/arm/mach-orion5x/
H A Dmpp.h16 #define MPP_F5181_MASK MPP(0, 0x0, 0, 0, 1, 0, 0)
17 #define MPP_F5182_MASK MPP(0, 0x0, 0, 0, 0, 1, 0)
18 #define MPP_F5281_MASK MPP(0, 0x0, 0, 0, 0, 0, 1)
20 #define MPP0_UNUSED MPP(0, 0x3, 0, 0, 1, 1, 1)
21 #define MPP0_GPIO MPP(0, 0x3, 1, 1, 1, 1,
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/linux/drivers/gpu/drm/amd/include/asic_reg/sdma7/
H A Dsdma7_4_2_2_offset.h29 #define mmSDMA7_UCODE_ADDR_BASE_IDX 1
31 #define mmSDMA7_UCODE_DATA_BASE_IDX 1
33 #define mmSDMA7_VM_CNTL_BASE_IDX 1
35 #define mmSDMA7_VM_CTX_LO_BASE_IDX 1
37 #define mmSDMA7_VM_CTX_HI_BASE_IDX 1
39 #define mmSDMA7_ACTIVE_FCN_ID_BASE_IDX 1
41 #define mmSDMA7_VM_CTX_CNTL_BASE_IDX 1
43 #define mmSDMA7_VIRT_RESET_REQ_BASE_IDX 1
45 #define mmSDMA7_VF_ENABLE_BASE_IDX 1
47 #define mmSDMA7_CONTEXT_REG_TYPE0_BASE_IDX 1
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/linux/drivers/gpu/drm/amd/include/asic_reg/sdma5/
H A Dsdma5_4_2_2_offset.h29 #define mmSDMA5_UCODE_ADDR_BASE_IDX 1
31 #define mmSDMA5_UCODE_DATA_BASE_IDX 1
33 #define mmSDMA5_VM_CNTL_BASE_IDX 1
35 #define mmSDMA5_VM_CTX_LO_BASE_IDX 1
37 #define mmSDMA5_VM_CTX_HI_BASE_IDX 1
39 #define mmSDMA5_ACTIVE_FCN_ID_BASE_IDX 1
41 #define mmSDMA5_VM_CTX_CNTL_BASE_IDX 1
43 #define mmSDMA5_VIRT_RESET_REQ_BASE_IDX 1
45 #define mmSDMA5_VF_ENABLE_BASE_IDX 1
47 #define mmSDMA5_CONTEXT_REG_TYPE0_BASE_IDX 1
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/linux/drivers/gpu/drm/amd/include/asic_reg/sdma6/
H A Dsdma6_4_2_2_offset.h29 #define mmSDMA6_UCODE_ADDR_BASE_IDX 1
31 #define mmSDMA6_UCODE_DATA_BASE_IDX 1
33 #define mmSDMA6_VM_CNTL_BASE_IDX 1
35 #define mmSDMA6_VM_CTX_LO_BASE_IDX 1
37 #define mmSDMA6_VM_CTX_HI_BASE_IDX 1
39 #define mmSDMA6_ACTIVE_FCN_ID_BASE_IDX 1
41 #define mmSDMA6_VM_CTX_CNTL_BASE_IDX 1
43 #define mmSDMA6_VIRT_RESET_REQ_BASE_IDX 1
45 #define mmSDMA6_VF_ENABLE_BASE_IDX 1
47 #define mmSDMA6_CONTEXT_REG_TYPE0_BASE_IDX 1
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/linux/drivers/gpu/drm/amd/include/asic_reg/sdma4/
H A Dsdma4_4_2_2_offset.h29 #define mmSDMA4_UCODE_ADDR_BASE_IDX 1
31 #define mmSDMA4_UCODE_DATA_BASE_IDX 1
33 #define mmSDMA4_VM_CNTL_BASE_IDX 1
35 #define mmSDMA4_VM_CTX_LO_BASE_IDX 1
37 #define mmSDMA4_VM_CTX_HI_BASE_IDX 1
39 #define mmSDMA4_ACTIVE_FCN_ID_BASE_IDX 1
41 #define mmSDMA4_VM_CTX_CNTL_BASE_IDX 1
43 #define mmSDMA4_VIRT_RESET_REQ_BASE_IDX 1
45 #define mmSDMA4_VF_ENABLE_BASE_IDX 1
47 #define mmSDMA4_CONTEXT_REG_TYPE0_BASE_IDX 1
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/linux/drivers/gpu/drm/amd/include/asic_reg/sdma2/
H A Dsdma2_4_2_2_offset.h29 #define mmSDMA2_UCODE_ADDR_BASE_IDX 1
31 #define mmSDMA2_UCODE_DATA_BASE_IDX 1
33 #define mmSDMA2_VM_CNTL_BASE_IDX 1
35 #define mmSDMA2_VM_CTX_LO_BASE_IDX 1
37 #define mmSDMA2_VM_CTX_HI_BASE_IDX 1
39 #define mmSDMA2_ACTIVE_FCN_ID_BASE_IDX 1
41 #define mmSDMA2_VM_CTX_CNTL_BASE_IDX 1
43 #define mmSDMA2_VIRT_RESET_REQ_BASE_IDX 1
45 #define mmSDMA2_VF_ENABLE_BASE_IDX 1
47 #define mmSDMA2_CONTEXT_REG_TYPE0_BASE_IDX 1
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/linux/drivers/gpu/drm/amd/include/asic_reg/sdma3/
H A Dsdma3_4_2_2_offset.h29 #define mmSDMA3_UCODE_ADDR_BASE_IDX 1
31 #define mmSDMA3_UCODE_DATA_BASE_IDX 1
33 #define mmSDMA3_VM_CNTL_BASE_IDX 1
35 #define mmSDMA3_VM_CTX_LO_BASE_IDX 1
37 #define mmSDMA3_VM_CTX_HI_BASE_IDX 1
39 #define mmSDMA3_ACTIVE_FCN_ID_BASE_IDX 1
41 #define mmSDMA3_VM_CTX_CNTL_BASE_IDX 1
43 #define mmSDMA3_VIRT_RESET_REQ_BASE_IDX 1
45 #define mmSDMA3_VF_ENABLE_BASE_IDX 1
47 #define mmSDMA3_CONTEXT_REG_TYPE0_BASE_IDX 1
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/linux/drivers/gpu/drm/amd/include/asic_reg/umc/
H A Dumc_6_7_0_offset.h389 #define regUMCCH4_0_BaseAddrCS0_BASE_IDX 1
391 #define regUMCCH4_0_AddrMaskCS01_BASE_IDX 1
393 #define regUMCCH4_0_AddrSelCS01_BASE_IDX 1
395 #define regUMCCH4_0_AddrHashBank0_BASE_IDX 1
397 #define regUMCCH4_0_AddrHashBank1_BASE_IDX 1
399 #define regUMCCH4_0_AddrHashBank2_BASE_IDX 1
401 #define regUMCCH4_0_AddrHashBank3_BASE_IDX 1
403 #define regUMCCH4_0_AddrHashBank4_BASE_IDX 1
405 #define regUMCCH4_0_AddrHashBank5_BASE_IDX 1
407 #define regUMCCH4_0_EccErrCntSel_BASE_IDX 1
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