Searched +full:0 +full:xff400000 (Results 1 – 13 of 13) sorted by relevance
/linux/Documentation/devicetree/bindings/fpga/ |
H A D | altr,socfpga-hps2fpga-bridge.yaml | 45 reg = <0xff400000 0x100000>; 46 bridge-enable = <0>;
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/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/ |
H A D | ctxnv40.h | 45 ctx->ctxprog_reg = (reg - 0x00400000) >> 2; in cp_ctx() 52 length = 0; in cp_ctx() 68 for (i = 0; i < ctx->ctxprog_len; i++) { in cp_name() 69 if ((ctxprog[i] & 0xfff00000) != 0xff400000) in cp_name() 73 ctxprog[i] = (ctxprog[i] & 0x00ff00ff) | in cp_name() 81 int ip = 0; in _cp_bra() 85 if (ip == 0) in _cp_bra() 86 ip = 0xff00000 in _cp_bra() [all...] |
/linux/arch/mips/boot/dts/brcm/ |
H A D | bcm6358.dtsi | 13 #size-cells = <0>; 16 brcm,bmips-cbr-reg = <0xff400000>; 18 cpu@0 { 21 reg = <0>; 34 #clock-cells = <0>; 48 #address-cells = <0>; 64 reg = <0xfffe0004 0x4>; 70 reg = <0xfffe000 [all...] |
H A D | bcm6368.dtsi | 13 #size-cells = <0>; 16 brcm,bmips-cbr-reg = <0xff400000>; 18 cpu@0 { 21 reg = <0>; 34 #clock-cells = <0>; 49 #address-cells = <0>; 65 reg = <0x10000004 0x4>; 71 reg = <0x1000000 [all...] |
/linux/Documentation/devicetree/bindings/usb/ |
H A D | amlogic,meson-g12a-usb-ctrl.yaml | 81 "^usb@[0-9a-f]+$": 202 reg = <0xffe09000 0xa0>; 218 reg = <0xff400000 0x40000>; 231 reg = <0xff500000 0x100000>; 235 snps,quirk-frame-length-adjustment = <0x20>;
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/linux/arch/mips/kernel/ |
H A D | bmips_vec.S | 35 * it to resume execution at 0x8000_0200 (!BEV IV vector) when it is 37 * it to a more convenient place: BMIPS_WARM_RESTART_VEC @ 0x8000_0380. 54 /* set up CPU1 CBR; move BASE to 0xa000_0000 */ 55 li k0, 0xff400000 60 andi k1, 0x8000 63 li k1, 0xa0080000 64 sw k1, 0(k0) 78 * entire function gets copied to 0x8000_0000. 100 /* if we're not on core 0, thi [all...] |
/linux/drivers/mtd/maps/ |
H A D | ichxrom.c | 30 #define BIOS_CNTL 0x4e 31 #define FWH_DEC_EN1 0xE3 32 #define FWH_DEC_EN2 0xF0 33 #define FWH_SEL1 0xE8 34 #define FWH_SEL2 0xEE 83 window->phys = 0; in ichxrom_cleanup() 84 window->size = 0; in ichxrom_cleanup() 113 window->phys = 0; in ichxrom_init_one() 115 if (byte == 0xff) { in ichxrom_init_one() 116 window->phys = 0xffc0000 in ichxrom_init_one() [all...] |
H A D | esb2rom.c | 34 #define BIOS_CNTL 0xDC 35 #define BIOS_LOCK_ENABLE 0x02 36 #define BIOS_WRITE_ENABLE 0x01 39 #define FWH_DEC_EN1 0xD8 40 #define FWH_F8_EN 0x8000 41 #define FWH_F0_EN 0x4000 42 #define FWH_E8_EN 0x2000 43 #define FWH_E0_EN 0x1000 44 #define FWH_D8_EN 0x0800 45 #define FWH_D0_EN 0x040 [all...] |
/linux/arch/powerpc/platforms/83xx/ |
H A D | suspend-asm.S | 14 #define SS_MEMSAVE 0x00 /* First 8 bytes of RAM */ 15 #define SS_HID 0x08 /* 3 HIDs */ 16 #define SS_IABR 0x14 /* 2 IABRs */ 17 #define SS_IBCR 0x1c 18 #define SS_DABR 0x20 /* 2 DABRs */ 19 #define SS_DBCR 0x28 20 #define SS_SP 0x2c 21 #define SS_SR 0x30 /* 16 segment registers */ 22 #define SS_R2 0x70 23 #define SS_MSR 0x7 [all...] |
/linux/arch/m68k/include/asm/ |
H A D | io_mm.h | 45 #define q40_isa_io_base 0xff400000 46 #define q40_isa_mem_base 0xff800000 53 #define MULTI_ISA 0 63 #define MULTI_ISA 0 72 #define enec_isa_read_base 0xfffa0000 73 #define enec_isa_write_base 0xfffb0000 75 #define ENEC_ISA_IO_B(ioaddr) (enec_isa_read_base+((((unsigned long)(ioaddr))&0x7F)<<9)) 76 #define ENEC_ISA_IO_W(ioaddr) (enec_isa_read_base+((((unsigned long)(ioaddr))&0x7F)<<9)) 77 #define ENEC_ISA_MEM_B(madr) (enec_isa_read_base+((((unsigned long)(madr))&0x7 [all...] |
/linux/arch/arm64/boot/dts/amlogic/ |
H A D | meson-a1.dtsi | 23 #size-cells = <0>; 25 cpu0: cpu@0 { 28 reg = <0x0 0x0>; 37 reg = <0x0 0x1>; 72 size = <0x0 0x800000>; 73 alignment = <0x0 0x40000 [all...] |
/linux/arch/arm/probes/ |
H A D | decode-thumb.c | 20 DECODE_REJECT (0xfe4f0000, 0xe80f0000), 24 DECODE_REJECT (0xffc00000, 0xe8000000), 27 DECODE_REJECT (0xffc00000, 0xe9800000), 30 DECODE_REJECT (0xfe508000, 0xe8008000), 32 DECODE_REJECT (0xfe50c000, 0xe810c00 [all...] |
/linux/arch/arm64/boot/dts/rockchip/ |
H A D | rk3308.dtsi | 44 #size-cells = <0>; 46 cpu0: cpu@0 { 49 reg = <0x0 0x0>; 62 reg = <0x0 0x1>; 72 reg = <0x0 0x2>; 82 reg = <0x0 0x [all...] |