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/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
H A Dfsl,qe.yaml106 reg = <0xe0100000 0x480>;
107 ranges = <0 0xe0100000 0x00100000>;
110 brg-frequency = <0>;
111 bus-frequency = <0x179a7b00>;
113 0x0
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/linux/Documentation/devicetree/bindings/crypto/
H A Damd,ccp-seattle-v1a.yaml35 reg = <0xe0100000 0x10000>;
36 interrupts = <0 3 4>;
/linux/Documentation/devicetree/bindings/clock/
H A Dsamsung,s5pv210-clock.yaml59 xxti: clock-0 {
61 clock-frequency = <0>;
63 #clock-cells = <0>;
68 clock-frequency = <0>;
70 #clock-cells = <0>;
75 reg = <0xe0100000 0x10000>;
/linux/arch/arm/mach-spear/
H A Dspear.h18 #define SPEAR_ICM1_2_BASE UL(0xD0000000)
19 #define VA_SPEAR_ICM1_2_BASE IOMEM(0xFD000000)
20 #define SPEAR_ICM1_UART_BASE UL(0xD0000000)
22 #define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000)
25 #define SPEAR_ICM3_ML1_2_BASE UL(0xF0000000)
26 #define VA_SPEAR6XX_ML_CPU_BASE IOMEM(0xF0000000)
29 #define SPEAR_ICM3_SMI_CTRL_BASE UL(0xFC000000)
30 #define VA_SPEAR_ICM3_SMI_CTRL_BASE IOMEM(0xFC000000)
31 #define SPEAR_ICM3_DMA_BASE UL(0xFC400000)
32 #define SPEAR_ICM3_SYS_CTRL_BASE UL(0xFCA0000
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/linux/Documentation/devicetree/bindings/gpio/
H A Dgpio-mmio.yaml40 of GPIOs is set by the width, with bit 0 corresponding to GPIO 0, unless
55 actively writing the line with 0.
83 to the first 0 .. ngpios lines. This is useful when the GPIO MMIO register
105 reg = <0x1f300010 0x4>;
114 reg = <0xe0100000 0x1>;
123 reg = <0xfffe040
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/linux/arch/powerpc/boot/dts/
H A Dmpc832x_rdb.dts26 #size-cells = <0>;
28 PowerPC,8323@0 {
30 reg = <0x0>;
31 d-cache-line-size = <0x20>; // 32 bytes
32 i-cache-line-size = <0x20>; // 32 bytes
35 timebase-frequency = <0>;
36 bus-frequency = <0>;
37 clock-frequency = <0>;
43 reg = <0x00000000 0x04000000>;
51 ranges = <0x0 0xe0000000 0x00100000>;
[all …]
H A Dac14xx.dts25 PowerPC,5121@0 {
33 reg = <0x00000000 0x10000000>; /* 256MB at 0 */
41 ranges = <0x0 0x0 0xfc000000 0x04000000 /* CS0: NOR flash */
42 0x1 0x
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H A Dsequoia.dts22 dcr-parent = <&{/cpus/cpu@0}>;
35 #size-cells = <0>;
37 cpu@0 {
40 reg = <0x00000000>;
41 clock-frequency = <0>; /* Filled in by zImage */
42 timebase-frequency = <0>; /* Filled in by zImage */
54 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by zImage */
60 cell-index = <0>;
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/linux/arch/arm/boot/dts/st/
H A Dspear13xx.dtsi15 #size-cells = <0>;
17 cpu@0 {
20 reg = <0>;
36 reg = < 0xec801000 0x1000 >,
37 < 0xec800100 0x0100 >;
42 interrupts = <0 6 0x04>,
43 <0
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/linux/arch/arm64/boot/dts/amd/
H A Damd-seattle-soc.dtsi22 reg = <0x0 0xe1110000 0 0x1000>,
23 <0x0 0xe112f000 0 0x2000>,
24 <0x0 0xe114000
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/linux/Documentation/devicetree/bindings/mmc/
H A Darasan,sdhci.yaml157 enum: [0, 1]
178 enum: [0, 1, 2]
179 default: 0
205 reg = <0xe0100000 0x1000>;
209 interrupts = <0 24 4>;
215 reg = <0xe2800000 0x1000>;
219 interrupts = <0 2
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/linux/arch/arm/boot/dts/xilinx/
H A Dzynq-7000.dtsi14 bootscr-address = /bits/ 64 <0x3000000>;
20 #size-cells = <0>;
22 cpu0: cpu@0 {
25 reg = <0>;
54 interrupts = <0 5 4>, <0 6 4>;
56 reg = <0xf8891000 0x1000>,
57 <0xf8893000 0x100
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/linux/arch/arm/boot/dts/samsung/
H A Ds5pv210.dtsi46 #size-cells = <0>;
48 cpu@0 {
51 reg = <0>;
55 xxti: oscillator-0 {
57 clock-frequency = <0>;
59 #clock-cells = <0>;
64 clock-frequency = <0>;
66 #clock-cells = <0>;
77 reg = <0xb0600000 0x200
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