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/linux/arch/arm64/boot/dts/marvell/
H A Darmada-7040-db.dts20 memory@0 {
22 reg = <0x0 0x0 0x0 0x80000000>;
33 regulator-name = "cp0-usb3-0-current-regulator";
38 states = <500000 0x0
39 900000 0x1>;
41 gpios-states = <0>;
51 states = <500000 0x
[all...]
H A Dcn9130-db.dtsi28 memory@0 {
30 reg = <0x0 0x0 0x0 0x80000000>;
39 states = <1800000 0x1 3300000 0x0>;
48 gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
76 states = <1800000 0x1
77 3300000 0x
[all...]
H A Dcn9131-db.dtsi24 pinctrl-0 = <&cp1_xhci0_vbus_pins>;
45 pinctrl-0 = <&cp1_sfp_pins>;
61 #define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
62 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
90 phys = <&cp1_comphy4 0>;
106 pinctrl-0 = <&cp1_i2c0_pins>;
113 pinctrl-0 = <&cp1_pcie_reset_pins>;
116 marvell,reset-gpio = <&cp1_gpio1 0 GPIO_ACTIVE_HIGH>;
119 phys = <&cp1_comphy0 0
[all...]
H A Darmada-8040-db.dts20 memory@0 {
22 reg = <0x0 0x0 0x0 0x80000000>;
34 cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus {
40 gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
52 cp0_usb3_0_phy: cp0-usb3-0-phy {
57 cp1_reg_usb3_0_vbus: cp1-usb3-0-vbus {
63 gpio = <&expander1 0 GPIO_ACTIVE_HIG
[all...]
H A Dcn9130-crb.dtsi24 memory@0 {
26 reg = <0x0 0x0 0x0 0x80000000>;
35 states = <1800000 0x1
36 3300000 0x0>;
63 states = <1800000 0x1
64 3300000 0x0>;
105 cp0_i2c0_pins: cp0-i2c-pins-0 {
[all...]
/linux/Documentation/devicetree/bindings/mtd/partitions/
H A Dnvmem-cells.yaml45 reg = <0x1200000 0x0140000>;
51 macaddr_gmac1: macaddr_gmac1@0 {
52 reg = <0x0 0x6>;
56 reg = <0x6 0x6>;
60 reg = <0x1000 0x2f20>;
64 reg = <0x500
[all...]
H A Dfixed-partitions.yaml51 "@[0-9a-f]+$":
77 partition@0 {
79 reg = <0x0000000 0x100000>;
84 reg = <0x0100000 0x200000>;
96 partition@0 {
98 reg = <0x00000000 0x1 0x0000000
[all...]
/linux/Documentation/devicetree/bindings/remoteproc/
H A Dti,k3-m4f-rproc.yaml92 reg = <0x00 0x9cb00000 0x00 0x100000>;
98 reg = <0x00 0x9cc00000 0x00 0xe00000>;
107 mailbox0_cluster0: mailbox-0 {
[all...]
/linux/arch/arm/boot/dts/marvell/
H A Dkirkwood-dir665.dts18 reg = <0x00000000 0x8000000>; /* 128 MB */
28 pinctrl-0 =< &pmx_led_usb
81 flash@0 {
86 reg = <0>;
88 partition@0 {
90 reg = <0x0 0x30000>;
96 reg = <0x30000 0x1000
[all...]
/linux/drivers/accel/habanalabs/include/goya/asic_reg/
H A Dgoya_masks.h180 ) & 0x7FFFFF)
191 #define GOYA_IRQ_HBW_ID_MASK 0x1FFF
192 #define GOYA_IRQ_HBW_ID_SHIFT 0
193 #define GOYA_IRQ_HBW_INTERNAL_ID_MASK 0xE000
195 #define GOYA_IRQ_HBW_AGENT_ID_MASK 0x1F0000
197 #define GOYA_IRQ_HBW_Y_MASK 0xE00000
199 #define GOYA_IRQ_HBW_X_MASK 0x7000000
201 #define GOYA_IRQ_LBW_ID_MASK 0xFF
202 #define GOYA_IRQ_LBW_ID_SHIFT 0
[all...]
/linux/Documentation/devicetree/bindings/soc/mobileye/
H A Dmobileye,eyeq5-olb.yaml85 pattern: '^(P(A|B)1?[0-9]|PA2[0-8]|PB2[0-2])$'
332 reg = <0 0xe00000 0x0 0x400>;
346 reg = <0x0 0xd200300
[all...]
/linux/arch/arm/boot/dts/intel/ixp/
H A Dintel-ixp43x-gateworks-gw2358.dts16 memory@0 {
19 reg = <0x00000000 0x8000000>;
35 gpios = <&pld1 0 GPIO_ACTIVE_LOW>;
47 #size-cells = <0>;
51 reg = <0x28>;
55 reg = <0x68>;
59 reg = <0x51>;
66 reg = <0x56>;
73 reg = <0x5
[all...]
/linux/arch/mips/boot/dts/mobileye/
H A Deyeq5.dtsi15 #size-cells = <0>;
16 cpu@0 {
19 reg = <0>;
34 reg = <0x8 0x04000000 0x0 0x1000000>;
37 reg = <0x8 0x05000000 0x
[all...]
/linux/arch/m68k/include/asm/
H A Dm5307sim.h27 #define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status reg */
28 #define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */
29 #define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */
30 #define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog service*/
31 #define MCFSIM_PAR (MCF_MBAR + 0x04) /* Pin Assignment */
32 #define MCFSIM_IRQPAR (MCF_MBAR + 0x06) /* Itr Assignment */
33 #define MCFSIM_PLLCR (MCF_MBAR + 0x08) /* PLL Ctrl Reg */
34 #define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */
35 #define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pend */
36 #define MCFSIM_IMR (MCF_MBAR + 0x4
[all...]
/linux/arch/csky/kernel/probes/
H A Dsimulate-insn.c18 *ptr = *(&regs->exregs[0] + index - 16); in csky_insn_reg_get_val()
47 *(&regs->exregs[0] + index - 16) = val; in csky_insn_reg_set_val()
72 addr + sign_extend32((opcode & 0x3ff) << 1, 9)); in simulate_br16()
79 addr + sign_extend32((opcode & 0xffff0000) >> 15, 15)); in simulate_br32()
87 addr + sign_extend32((opcode & 0x3ff) << 1, 9)); in simulate_bt16()
97 addr + sign_extend32((opcode & 0xffff0000) >> 15, 15)); in simulate_bt32()
107 addr + sign_extend32((opcode & 0x3ff) << 1, 9)); in simulate_bf16()
117 addr + sign_extend32((opcode & 0xffff0000) >> 15, 15)); in simulate_bf32()
125 unsigned long tmp = (opcode >> 2) & 0xf; in simulate_jmp16()
129 instruction_pointer_set(regs, tmp & 0xfffffff in simulate_jmp16()
[all...]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-am62-phycore-som.dtsi31 reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
42 reg = <0x00 0x9c700000 0x00 0x00100000>;
43 record-size = <0x8000>;
44 console-size = <0x800
[all...]
H A Dk3-am62-pocketbeagle2.dts39 reg = <0x00000000 0x80000000 0x00000000 0x20000000>;
53 size = <0x00 0x8000000>;
59 reg = <0x00 0x9cb00000 0x00 0x10000
[all...]
H A Dk3-am62x-sk-common.dtsi36 reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
46 reg = <0x00 0x9ca00000 0x00 0x00100000>;
47 record-size = <0x8000>;
48 console-size = <0x800
[all...]
/linux/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_7_0_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MC_RD_ENABLE_MASK 0x30
36 #define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x
[all...]
H A Dgmc_7_1_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x
[all...]
H A Dgmc_8_1_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x
[all...]
H A Dgmc_8_2_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x
[all...]
/linux/net/ipv6/
H A Dioam6_iptunnel.c25 #define IOAM6_MASK_SHORT_FIELDS 0xff100000
26 #define IOAM6_MASK_WIDE_FIELDS 0xe00000
96 trace->nodelen = 0; in ioam6_validate_trace_hdr()
126 if (err < 0) in ioam6_build_state()
189 atomic_set(&ilwt->pkt_cnt, 0); in ioam6_build_state()
222 tuninfo->pad[0] = IPV6_TLV_PADN; in ioam6_build_state()
240 return 0; in ioam6_build_state()
261 return 0; in ioam6_do_fill()
418 memset(&fl6, 0, sizeo in ioam6_output()
[all...]
/linux/arch/mips/lantiq/xway/
H A Dsysctrl.c21 #define CGU_IFCCR 0x0018
22 #define CGU_IFCCR_VR9 0x0024
24 #define CGU_SYS 0x0010
26 #define CGU_PCICR 0x0034
27 #define CGU_PCICR_VR9 0x0038
29 #define CGU_EPHY 0x10
33 #define PMU_PWDCR 0x1C
35 #define PMU_PWDSR 0x20
37 #define PMU_PWDCR1 0x24
39 #define PMU_PWDSR1 0x2
[all...]
/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8
36 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x
[all...]

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