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/linux/Documentation/devicetree/bindings/dsp/ !
H A Dfsl,dsp.yaml199 reg = <0x596e8000 0x88000>;
207 mboxes = <&lsio_mu13 2 0>, <&lsio_mu13 2 1>, <&lsio_mu13 3 0>, <&lsio_mu13 3 1>;
214 reg = <0x92400000 0x1000000>;
218 reg = <0x942f0000 0x8000>;
222 reg = <0x942f8000 0x8000>;
227 reg = <0x94300000 0x100000>;
233 reg = <0x3b6e8000 0x88000>;
242 mboxes = <&mu2 0 0>,
243 <&mu2 1 0>,
244 <&mu2 3 0>;
/linux/arch/arm64/boot/dts/freescale/ !
H A Dqoriq-fman3-0-1g-0.dtsi3 * QorIQ FMan v3 1g port #0 device tree
11 cell-index = <0x8>;
13 reg = <0x88000 0x1000>;
17 cell-index = <0x28>;
19 reg = <0xa8000 0x1000>;
23 cell-index = <0>;
25 reg = <0xe000
[all...]
H A Dimx8qm.dtsi38 #size-cells = <0>;
66 A53_0: cpu@0 {
69 reg = <0x0 0x0>;
72 i-cache-size = <0x8000>;
75 d-cache-size = <0x8000>;
86 reg = <0x0 0x1>;
89 i-cache-size = <0x8000>;
92 d-cache-size = <0x800
[all...]
H A Dimx8-ss-audio.dtsi14 #clock-cells = <0>;
21 #clock-cells = <0>;
22 clock-frequency = <0>;
28 #clock-cells = <0>;
29 clock-frequency = <0>;
35 #clock-cells = <0>;
36 clock-frequency = <0>;
42 #clock-cells = <0>;
43 clock-frequency = <0>;
49 #clock-cells = <0>;
[all...]
/linux/arch/powerpc/boot/dts/fsl/ !
H A Dqoriq-fman3-0-10g-2.dtsi3 * QorIQ FMan v3 10g port #2 device tree stub [ controller @ offset 0x400000 ]
11 cell-index = <0x8>;
13 reg = <0x88000 0x1000>;
18 cell-index = <0x28>;
20 reg = <0xa8000 0x1000>;
25 cell-index = <0>;
27 reg = <0xe000
[all...]
H A Dqoriq-fman-0-1g-0.dtsi2 * QorIQ FMan 1g port #0 device tree stub [ controller @ offset 0x400000 ]
37 cell-index = <0x8>;
39 reg = <0x88000 0x1000>;
43 cell-index = <0x28>;
45 reg = <0xa8000 0x1000>;
49 cell-index = <0>;
[all...]
H A Dqoriq-fman3-1-1g-0.dtsi2 * QorIQ FMan v3 1g port #0 device tree stub [ controller @ offset 0x500000 ]
37 cell-index = <0x8>;
39 reg = <0x88000 0x1000>;
43 cell-index = <0x28>;
45 reg = <0xa8000 0x1000>;
49 cell-index = <0>;
[all...]
H A Dqoriq-fman3-0-1g-0.dtsi2 * QorIQ FMan v3 1g port #0 device tree stub [ controller @ offset 0x400000 ]
37 cell-index = <0x8>;
39 reg = <0x88000 0x1000>;
43 cell-index = <0x28>;
45 reg = <0xa8000 0x1000>;
49 cell-index = <0>;
[all...]
H A Dqoriq-fman-1-1g-0.dtsi2 * QorIQ FMan 1g port #0 device tree stub [ controller @ offset 0x500000 ]
37 cell-index = <0x8>;
39 reg = <0x88000 0x1000>;
43 cell-index = <0x28>;
45 reg = <0xa8000 0x1000>;
49 cell-index = <0>;
[all...]
H A Dqoriq-fman3-0-10g-0-best-effort.dtsi2 * QorIQ FMan v3 1g port #0 device tree stub [ controller @ offset 0x400000 ]
37 cell-index = <0x8>;
39 reg = <0x88000 0x1000>;
45 cell-index = <0x28>;
47 reg = <0xa8000 0x1000>;
53 cell-index = <0>;
[all...]
H A Dp1023si-post.dtsi37 alloc-ranges = <0 0 0x10 0>;
42 alloc-ranges = <0 0 0x10 0>;
47 alloc-ranges = <0 0
[all...]
/linux/arch/arm/boot/dts/marvell/ !
H A Darmada-xp-mv78260.dtsi27 #size-cells = <0>;
30 cpu@0 {
33 reg = <0>;
34 clocks = <&cpuclk 0>;
49 * MV78260 has 3 PCIe units Gen2.0: Two units can be
62 bus-range = <0x00 0xff>;
65 <0x82000000 0 0x4000
[all...]
H A Darmada-xp-mv78460.dtsi28 #size-cells = <0>;
31 cpu@0 {
34 reg = <0>;
35 clocks = <&cpuclk 0>;
66 * MV78460 has 4 PCIe units Gen2.0: Two units can be
79 bus-range = <0x00 0xff>;
82 <0x82000000 0 0x4000
[all...]
/linux/Documentation/devicetree/bindings/pci/ !
H A Dmarvell,kirkwood-pcie.yaml28 0x82000000 0 r MBUS_ID(0xf0, 0x01) r 0 s
36 This range entry translates the '0x82000000 0 r' PCI address into the
37 'MBUS_ID(0xf0, 0x01) r' CPU address, which is part of the internal
38 register window (as identified by MBUS_ID(0xf
[all...]
/linux/arch/arm/mach-mv78xx0/ !
H A Dmv78xx0.h17 * f0800000 PCIe #0 I/O space
29 * fee00000 f0800000 64K PCIe #0 I/O space
39 #define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000
40 #define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000
41 #define MV78XX0_CORE_REGS_VIRT_BASE IOMEM(0xfe400000)
42 #define MV78XX0_CORE_REGS_PHYS_BASE 0xfe400000
45 #define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20))
48 #define MV78XX0_REGS_PHYS_BASE 0xf1000000
49 #define MV78XX0_REGS_VIRT_BASE IOMEM(0xfec00000)
52 #define MV78XX0_SRAM_PHYS_BASE (0xf220000
[all...]
/linux/Documentation/devicetree/bindings/net/ !
H A Dfsl,fman.yaml22 FMan block. The offset is 0xc4 from the beginning of the
23 Frame Processing Manager memory map (0xc3000 from the
38 DEVDISR[1] 1 0
43 DCFG_DEVDISR2[6] 1 0
50 DCFG_CCSR_DEVDISR2[24] 1 0
156 reg = <0x400000 0x100000>;
157 ranges = <0 0x400000 0x10000
[all...]
/linux/Documentation/devicetree/bindings/mailbox/ !
H A Darm,mhuv2.yaml74 version MHUv2.0, but the later versions do have it.
96 The first field of a tuple signifies the transfer protocol, 0 is reserved
114 arm,mhuv2-protocols = <0 2>, <1 1>, <1 5>, <1 7>;
126 - enum: [ 0, 1 ]
127 - minimum: 0
136 relevant in doorbell protocol, should be 0 otherwise) represents the
142 mboxes = <&mhu 0 5>; // Channel Window Group 0, doorbell 5.
144 mboxes = <&mhu 2 0>; // Channel Window Group 2, data transfer protocol with 1 window.
145 mboxes = <&mhu 3 0>; // Channe
[all...]
/linux/arch/powerpc/boot/dts/ !
H A Dksi8560.dts33 #size-cells = <0>;
35 PowerPC,8560@0 {
37 reg = <0>;
40 d-cache-size = <0x8000>; /* L1, 32K */
41 i-cache-size = <0x8000>; /* L1, 32K */
42 timebase-frequency = <0>; /* From U-boot */
43 bus-frequency = <0>; /* From U-boot */
44 clock-frequency = <0>; /* From U-boot */
51 reg = <0x00000000 0x1000000
[all...]
H A Dtqm8560.dts30 #size-cells = <0>;
32 PowerPC,8560@0 {
34 reg = <0>;
39 timebase-frequency = <0>;
40 bus-frequency = <0>;
41 clock-frequency = <0>;
48 reg = <0x00000000 0x10000000>;
55 ranges = <0x0 0xe000000
[all...]
/linux/drivers/soc/tegra/cbb/ !
H A Dtegra234-cbb.c8 * Error types supported by CBB2.0 are:
27 #define FABRIC_EN_CFG_INTERRUPT_ENABLE_0_0 0x0
28 #define FABRIC_EN_CFG_STATUS_0_0 0x40
29 #define FABRIC_EN_CFG_ADDR_INDEX_0_0 0x60
30 #define FABRIC_EN_CFG_ADDR_LOW_0 0x80
31 #define FABRIC_EN_CFG_ADDR_HI_0 0x84
33 #define FABRIC_EN_CFG_TARGET_NODE_ADDR_INDEX_0_0 0x100
34 #define FABRIC_EN_CFG_TARGET_NODE_ADDR_LOW_0 0x140
35 #define FABRIC_EN_CFG_TARGET_NODE_ADDR_HI_0 0x144
37 #define FABRIC_MN_INITIATOR_ERR_EN_0 0x20
[all...]
/linux/drivers/clk/qcom/ !
H A Dgcc-sdx65.c36 .offset = 0x0,
39 .enable_reg = 0x6d000,
40 .enable_mask = BIT(0),
53 { 0x1, 2 },
58 .offset = 0x0,
73 { P_BI_TCXO, 0 },
91 { P_BI_TCXO, 0 },
105 { P_BI_TCXO, 0 },
119 { P_PCIE_PIPE_CLK, 0 },
129 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
[all...]
/linux/arch/arm64/boot/dts/amlogic/ !
H A Damlogic-c3.dtsi19 #size-cells = <0>;
21 cpu0: cpu@0 {
24 reg = <0x0 0x0>;
31 reg = <0x0 0x1>;
53 #clock-cells = <0>;
67 reg = <0x0 0x07f50e00 0x
[all...]
/linux/drivers/gpu/drm/msm/registers/display/ !
H A Dmdp4.xml11 <value name="VG1" value="0"/>
21 <value name="MIXER0" value="0"/>
30 LCDC_RGB_INTF, /* 0 */
31 DTV_INTF = LCDC_RGB_INTF, /* 0 */
44 <value name="INTF_LCDC_DTV" value="0"/> <!-- LCDC RGB or DTV (external) -->
54 <value name="FRAME_LINEAR" value="0"/>
59 <value name="SCALE_FIR" value="0"/>
66 <bitfield name="PIPE0" low="0" high="2" type="mdp_mixer_stage_id"/>
85 <bitfield name="OVERLAY0_DONE" pos="0" type="boolean"/>
102 <reg32 offset="0x0000
[all...]
/linux/arch/arm64/boot/dts/apple/ !
H A Ds8001-pmgr.dtsi11 reg = <0x80000 4>;
12 #power-domain-cells = <0>;
13 #reset-cells = <0>;
20 reg = <0x80008 4>;
21 #power-domain-cells = <0>;
22 #reset-cells = <0>;
29 reg = <0x80040 4>;
30 #power-domain-cells = <0>;
31 #reset-cells = <0>;
38 reg = <0x8014
[all...]
H A Dt8011-pmgr.dtsi11 reg = <0x80000 4>;
12 #power-domain-cells = <0>;
13 #reset-cells = <0>;
20 reg = <0x80008 4>;
21 #power-domain-cells = <0>;
22 #reset-cells = <0>;
29 reg = <0x80010 4>;
30 #power-domain-cells = <0>;
31 #reset-cells = <0>;
38 reg = <0x8004
[all...]

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