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Searched +full:0 +full:x80004000 (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/dma/bestcomm/
H A Dbcom_fec_rx_task.c27 0x4243544b,
28 0x18060709,
29 0x00000000,
30 0x00000000,
33 0x808220e3, /* LCD: idx0 = var1, idx1 = var4; idx1 <= var3; idx0 += inc4, idx1 += inc3 */
34 0x10601010, /* DRD1A: var4 = var2; FN=0 MORE init=3 WS=0 RS=0 */
35 0xb880026
[all...]
H A Dbcom_fec_tx_task.c27 0x4243544b,
28 0x2407070d,
29 0x00000000,
30 0x00000000,
33 0x8018001b, /* LCD: idx0 = var0; idx0 <= var0; idx0 += inc3 */
34 0x60000005, /* DRD2A: EU0=0 EU1=0 EU2=0 EU3=5 EXT init=0 W
[all...]
/linux/Documentation/devicetree/bindings/i2c/
H A Dst,nomadik-i2c.yaml114 reg = <0x80004000 0x1000>;
118 #size-cells = <0>;
129 reg = <0x101f8000 0x1000>;
134 #size-cells = <0>;
142 reg = <0x300000 0x1000>;
147 #size-cells = <0>;
[all...]
/linux/drivers/gpu/drm/i915/gt/
H A Dgen9_renderstate.c11 0x000007a8,
12 0x000007b4,
13 0x000007bc,
14 0x000007cc,
19 0x7a000004,
20 0x01000000,
21 0x00000000,
22 0x00000000,
23 0x00000000,
24 0x0000000
[all...]
H A Dgen8_renderstate.c11 0x00000798,
12 0x000007a4,
13 0x000007ac,
14 0x000007bc,
19 0x7a000004,
20 0x01000000,
21 0x00000000,
22 0x00000000,
23 0x00000000,
24 0x0000000
[all...]
/linux/arch/arm/boot/dts/nxp/mxs/
H A Dimx23.dtsi32 #size-cells = <0>;
34 cpu@0 {
37 reg = <0>;
45 reg = <0x80000000 0x80000>;
52 reg = <0x80000000 0x40000>;
59 reg = <0x80000000 0x2000>;
64 reg = <0x8000400
[all...]
H A Dimx28.dtsi43 #size-cells = <0>;
45 cpu@0 {
48 reg = <0>;
56 reg = <0x80000000 0x80000>;
63 reg = <0x80000000 0x3c900>;
70 reg = <0x80000000 0x2000>;
74 reg = <0x8000200
[all...]
/linux/drivers/video/fbdev/
H A Dcg14.c51 #define CG14_MCR_INTENABLE_MASK 0x80
53 #define CG14_MCR_VIDENABLE_MASK 0x40
55 #define CG14_MCR_PIXMODE_MASK 0x30
57 #define CG14_MCR_TMR_MASK 0x0c
59 #define CG14_MCR_TMENABLE_MASK 0x02
60 #define CG14_MCR_RESET_SHIFT 0
61 #define CG14_MCR_RESET_MASK 0x01
63 #define CG14_REV_REVISION_MASK 0xf0
64 #define CG14_REV_IMPL_SHIFT 0
65 #define CG14_REV_IMPL_MASK 0x0
[all...]
/linux/drivers/gpu/drm/amd/amdgpu/
H A Djpeg_v4_0_3.c37 (offset & 0x1FFFF)
40 UVD_PGFSM_STATUS__UVDJ_PWR_ON = 0,
63 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_POWER_STATUS),
64 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_INT_STAT),
65 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_SYS_INT_STATUS),
66 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_RPTR),
67 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_WPTR),
68 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_STATUS),
69 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_ADDR_MODE),
70 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFI
[all...]