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/linux/arch/arm64/boot/dts/ti/
H A Dk3-am65.dtsi54 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
55 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
56 <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
57 <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
58 <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
59 <0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* MSMC SRAM */
60 <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
62 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
63 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
64 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
[all …]
H A Dk3-j7200.dtsi25 #size-cells = <0>;
39 cpu0: cpu@0 {
41 reg = <0x000>;
44 i-cache-size = <0xc000>;
47 d-cache-size = <0x8000>;
55 reg = <0x001>;
58 i-cache-size = <0xc000>;
61 d-cache-size = <0x8000>;
72 cache-size = <0x100000>;
113 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
[all …]
H A Dk3-j784s4-j742s2-common.dtsi27 cache-size = <0x200000>;
37 cache-size = <0x200000>;
80 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
81 <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
82 <0x00 0x00700000 0x00 0x00700000 0x00 0x00001000>, /* ESM */
83 <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */
84 <0x00 0x04210000 0x00 0x04210000 0x00 0x00010000>, /* VPU0 */
85 <0x00 0x04220000 0x00 0x04220000 0x00 0x00010000>, /* VPU1 */
86 <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIe0 Core*/
87 <0x00 0x0d800000 0x00 0x0d800000 0x00 0x00800000>, /* PCIe1 Core*/
[all …]
H A Dk3-j721e-mcu-wakeup.dtsi19 reg = <0x00 0x44083000 0x0 0x1000>;
44 ranges = <0x0 0x0 0x40f00000 0x20000>;
48 reg = <0x200 0x8>;
53 reg = <0x4040 0x4>;
62 ranges = <0x0 0x00 0x43000000 0x20000>;
66 reg = <0x14 0x4>;
73 /* Proxy 0 addressing */
74 reg = <0x00 0x4301c000 0x00 0x178>;
77 pinctrl-single,function-mask = <0xffffffff>;
83 reg = <0x00 0x40f04200 0x00 0x28>;
[all …]
H A Dk3-j7200-mcu-wakeup.dtsi19 reg = <0x00 0x44083000 0x00 0x1000>;
43 reg = <0x00 0x40400000 0x00 0x400>;
57 reg = <0x00 0x40410000 0x00 0x400>;
61 assigned-clocks = <&k3_clks 71 1>, <&k3_clks 308 0>;
70 reg = <0x00 0x40420000 0x00 0x400>;
83 reg = <0x00 0x40430000 0x00 0x400>;
87 assigned-clocks = <&k3_clks 73 1>, <&k3_clks 309 0>;
96 reg = <0x00 0x40440000 0x00 0x400>;
109 reg = <0x00 0x40450000 0x00 0x400>;
113 assigned-clocks = <&k3_clks 75 1>, <&k3_clks 310 0>;
[all …]
H A Dk3-j784s4-j742s2-mcu-wakeup-common.dtsi19 reg = <0x00 0x44083000 0x00 0x1000>;
44 ranges = <0x0 0x00 0x43000000 0x20000>;
49 reg = <0x14 0x4>;
57 reg = <0x00 0x43600000 0x00 0x10000>,
58 <0x00 0x44880000 0x00 0x20000>,
59 <0x00 0x44860000 0x00 0x20000>;
72 reg = <0x00 0x41c00000 0x00 0x100000>;
73 ranges = <0x00 0x00 0x41c00000 0x100000>;
80 /* Proxy 0 addressing */
81 reg = <0x00 0x4301c000 0x00 0x034>;
[all …]
H A Dk3-j721s2-mcu-wakeup.dtsi19 reg = <0x00 0x44083000 0x00 0x1000>;
44 ranges = <0x0 0x00 0x43000000 0x20000>;
48 reg = <0x14 0x4>;
57 reg = <0x00 0x43600000 0x00 0x10000>,
58 <0x00 0x44880000 0x00 0x20000>,
59 <0x00 0x44860000 0x00 0x20000>;
72 reg = <0x00 0x41c00000 0x00 0x100000>;
73 ranges = <0x00 0x00 0x41c00000 0x100000>;
80 /* Proxy 0 addressing */
81 reg = <0x00 0x4301c000 0x00 0x034>;
[all …]
/linux/Documentation/devicetree/bindings/virtio/
H A Dpci-iommu.yaml61 reg = <0x0 0x40000000 0x0 0x1000000>;
62 ranges = <0x02000000 0x0 0x41000000 0x0 0x41000000 0x0 0x0f000000>;
68 iommu-map = <0x0 &iommu0 0x0 0x8
69 0x9 &iommu0 0x9 0xfff7>;
72 iommu0: iommu@1,0 {
74 reg = <0x800 0 0 0 0>;
83 reg = <0x0 0x50000000 0x0 0x1000000>;
84 ranges = <0x02000000 0x0 0x51000000 0x0 0x51000000 0x0 0x0f000000>;
88 * with endpoint IDs 0x10000 - 0x1ffff
90 iommu-map = <0x0 &iommu0 0x10000 0x10000>;
[all …]
/linux/Documentation/devicetree/bindings/iommu/
H A Driscv,iommu.yaml85 reg = <0x1bccd000 0x1000>;
94 /* Device with two IOMMU device IDs, 0 and 7 */
96 iommus = <&iommu1 0>, <&iommu1 7>;
105 reg = <0x1bccd000 0x1000>;
115 reg = <0x1bccd000 0x1000>;
130 reg = <0x0 0x30000000 0x0 0x1000000>;
131 ranges = <0x02000000 0x0 0x41000000 0x0 0x41000000 0x0 0x0f000000>;
137 iommu-map = <0x0 &iommu0 0x0 0x8>,
138 <0x9 &iommu0 0x9 0xfff7>;
141 iommu0: iommu@1,0 {
[all …]
/linux/Documentation/devicetree/bindings/pci/
H A Dhost-generic-pci.yaml94 property. If no "bus-range" is specified, this will be bus 0 (the
160 bus-range = <0x0 0x1>;
163 reg = <0x0 0x40000000 0x0 0x1000000>;
166 ranges = <0x01000000 0x0 0x01000000 0x0 0x01000000 0x0 0x00010000>,
167 <0x02000000 0x0 0x41000000 0x0 0x41000000 0x0 0x3f000000>;
169 #interrupt-cells = <0x1>;
172 interrupt-map = < 0x0 0x0 0x0 0x1 &gic 0x0 0x4 0x1>,
173 < 0x800 0x0 0x0 0x1 &gic 0x0 0x5 0x1>,
174 <0x1000 0x0 0x0 0x1 &gic 0x0 0x6 0x1>,
175 <0x1800 0x0 0x0 0x1 &gic 0x0 0x7 0x1>;
[all …]
H A Dcdns,cdns-pcie-host.yaml44 bus-range = <0x0 0xff>;
45 linux,pci-domain = <0>;
46 vendor-id = <0x17cd>;
47 device-id = <0x0200>;
49 reg = <0x0 0xfb000000 0x0 0x01000000>,
50 <0x0 0x41000000 0x0 0x00001000>;
53 ranges = <0x02000000 0x0 0x42000000 0x0 0x42000000 0x0 0x1000000>,
54 <0x01000000 0x0 0x43000000 0x0 0x43000000 0x0 0x0010000>;
55 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x1 0x00000000>;
57 #interrupt-cells = <0x1>;
[all …]
/linux/Documentation/devicetree/bindings/sound/
H A Dmrvl,pxa-ssp.txt22 reg = <0x41000000 0x40>;
24 clock-names = "pxa27x-ssp.0";
29 ssp_dai0: ssp_dai@0 {
32 #sound-dai-cells = <0>;
/linux/Documentation/devicetree/bindings/watchdog/
H A Dfaraday,ftwdt010.yaml56 reg = <0x41000000 0x1000>;
63 reg = <0x98500000 0x10>;
/linux/Documentation/devicetree/bindings/pwm/
H A Dmicrochip,corepwm.yaml52 default: 0
66 default: 0
79 microchip,sync-update-mask = /bits/ 32 <0>;
81 reg = <0x41000000 0xF0>;
/linux/arch/arm/boot/dts/arm/
H A Dversatile-pb.dts11 clear-mask = <0xffffffff>;
16 valid-mask = <0x7fe003ff>;
21 reg = <0x101e6000 0x1000>;
33 reg = <0x101e7000 0x1000>;
46 reg = <0x10001000 0x1000
47 0x41000000 0x10000
48 0x42000000 0x100000>;
49 bus-range = <0 0xff>;
54 ranges = <0x01000000 0 0x00000000 0x43000000 0 0x00010000 /* downstream I/O */
55 0x02000000 0 0x50000000 0x50000000 0 0x10000000 /* non-prefetchable memory */
[all …]
/linux/arch/arm/include/asm/hardware/
H A Ddec21285.h9 #define DC21285_PCI_IACK 0x79000000
10 #define DC21285_ARMCSR_BASE 0x42000000
11 #define DC21285_PCI_TYPE_0_CONFIG 0x7b000000
12 #define DC21285_PCI_TYPE_1_CONFIG 0x7a000000
13 #define DC21285_OUTBOUND_WRITE_FLUSH 0x78000000
14 #define DC21285_FLASH 0x41000000
15 #define DC21285_PCI_IO 0x7c000000
16 #define DC21285_PCI_MEM 0x80000000
26 * The footbridge is programmed to expose the system RAM at 0xe0000000.
27 * The requirement is that the RAM isn't placed at bus address 0, which
[all …]
/linux/arch/arm/mach-pxa/
H A Ddevices.c52 [0] = {
53 .start = 0x41100000,
54 .end = 0x41100fff,
69 .id = 0, in pxa_set_mci_info()
74 .dma_mask = 0xffffffffUL, in pxa_set_mci_info()
91 [0] = {
92 .start = 0x40600000,
93 .end = 0x4060ffff,
103 static u64 udc_dma_mask = ~(u32)0;
128 [0] = {
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Ddra74x.dtsi49 reg = <0x41500000 0x100>;
55 reg = <0x41501000 0x4>,
56 <0x41501010 0x4>,
57 <0x41501014 0x4>;
65 clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>;
69 ranges = <0x0 0x41501000 0x1000>;
73 mmu0_dsp2: mmu@0 {
75 reg = <0x0 0x100>;
77 #iommu-cells = <0>;
78 ti,syscon-mmuconfig = <&dsp2_system 0x0>;
[all …]
/linux/arch/arm/mach-footbridge/
H A Dcommon.c100 return 0; in dc21285_get_irq()
122 mem_fclk_21285 = simple_strtoul(arg, NULL, 0); in early_fclk()
123 return 0; in early_fclk()
131 return 0; in parse_tag_memclk()
141 IRQ_MASK_UART_RX, /* 0 */
189 for (irq = _DC21285_IRQ(0); irq < _DC21285_IRQ(20); irq++) { in __fb_init_irq()
259 soft_restart(0x41000000); in footbridge_restart()
276 *CSR_TIMER4_LOAD = 0x2; in footbridge_restart()
277 *CSR_TIMER4_CLR = 0; in footbridge_restart()
/linux/arch/arm/kernel/
H A Dhead.S30 * the least significant 16 bits to be 0x8000, but we could probably
31 * relax this restriction to KERNEL_RAM_VADDR >= PAGE_OFFSET + 0x4000.
34 #if (KERNEL_RAM_VADDR & 0xffff) != 0x8000
35 #error KERNEL_RAM_VADDR must start at 0xXXXX8000
40 #define PG_DIR_SIZE 0x5000
43 #define PG_DIR_SIZE 0x4000
60 .long 0
61 .long 0
63 .long 0
64 .long 0
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Dexynos4210-origen.dts27 reg = <0x40000000 0x10000000
28 0x50000000 0x10000000
29 0x60000000 0x10000000
30 0x70000000 0x10000000>;
39 bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M init=/linuxrc";
57 gpios = <&gpx2 0 GPIO_ACTIVE_LOW>;
103 clock-frequency = <0>;
114 #clock-cells = <0>;
157 pinctrl-0 = <&lcd_en &lcd_clk &lcd_data24 &pwm0_out>;
178 pinctrl-0 = <&i2c0_bus>;
[all …]
H A Dexynos5250-smdk5250.dts26 reg = <0x40000000 0x80000000>;
30 bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M init=/linuxrc";
73 #clock-cells = <0>;
84 samsung,color-space = <0>;
86 samsung,link-rate = <0x0a>;
90 pinctrl-0 = <&dp_hpd>;
135 reg = <0x50>;
140 reg = <0x09>;
144 pinctrl-0 = <&max77686_irq>;
150 regulator-name = "P1.0V_LDO_OUT1";
[all …]
/linux/arch/arm/boot/dts/intel/pxa/
H A Dpxa3xx.dtsi6 ((gpio <= 2) ? (0x00b4 + 4 * gpio) : \
7 (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \
8 (gpio <= 98) ? (0x0400 + 4 * (gpio - 27)) : \
9 (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \
10 0)
12 ((gpio <= 1) ? (0x674 + 4 * gpio) : \
13 (gpio <= 6) ? (0x2dc + 4 * gpio) : \
14 0)
17 ((gpio <= 2) ? (0x00b4 + 4 * gpio) : \
18 (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \
[all …]
/linux/arch/mips/include/asm/
H A Dmipsmtregs.h19 #define read_c0_mvpcontrol() __read_32bit_c0_register($0, 1)
20 #define write_c0_mvpcontrol(val) __write_32bit_c0_register($0, 1, val)
22 #define read_c0_mvpconf0() __read_32bit_c0_register($0, 2)
23 #define read_c0_mvpconf1() __read_32bit_c0_register($0, 3)
49 #define CP0_MVPCONTROL $0, 1
50 #define CP0_MVPCONF0 $0, 2
51 #define CP0_MVPCONF1 $0, 3
84 #define MVPCONF0_PTC_SHIFT 0
85 #define MVPCONF0_PTC ( _ULCAST_(0xff))
87 #define MVPCONF0_PVPE ( _ULCAST_(0xf) << MVPCONF0_PVPE_SHIFT)
[all …]
/linux/arch/arm/boot/dts/gemini/
H A Dgemini.dtsi23 pinctrl-0 = <&pflash_default_pins>;
31 reg = <0x40000000 0x1000>;
39 offset = <0x0c>;
41 mask = <0xC0000000>;
49 pinctrl-0 = <&dram_default_pins>, <&system_default_pins>,
159 reg = <0x41000000 0x1000>;
168 reg = <0x42000000 0x100>;
173 pinctrl-0 = <&uart_default_pins>;
179 reg = <0x43000000 0x1000>;
193 reg = <0x45000000 0x100>;
[all …]

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