Home
last modified time | relevance | path

Searched +full:0 +full:x40030000 (Results 1 – 14 of 14) sorted by relevance

/linux/arch/m68k/fpsp040/
H A Dstan.S27 | k = N mod 2, so in particular, k = 0 or 1.
62 BOUNDS1: .long 0x3FD78000,0x4004BC7E
63 TWOBYPI: .long 0x3FE45F30,0x6DC9C883
65 TANQ4: .long 0x3EA0B759,0xF50F8688
66 TANP3: .long 0xBEF2BAA5,0xA8924F04
68 TANQ3: .long 0xBF346F5
[all...]
/linux/include/linux/soc/qcom/
H A Dubwc.h15 /* Can be read from MDSS_BASE + 0x58 */
26 #define UBWC_SWIZZLE_ENABLE_LVL1 BIT(0)
43 * 8-channel macrotiling mode introduced in UBWC 3.1. 0 is
49 #define UBWC_1_0 0x10000000
50 #define UBWC_2_0 0x20000000
51 #define UBWC_3_0 0x30000000
52 #define UBWC_4_0 0x40000000
53 #define UBWC_4_3 0x40030000
54 #define UBWC_5_0 0x5000000
[all...]
/linux/Documentation/devicetree/bindings/spi/
H A Dsprd,spi-adi.yaml72 triggered by hardware automatically, channel id 0-1 are for software
95 reg = <0 0x40030000 0 0x10000>;
96 hwlocks = <&hwlock1 0>;
99 #size-cells = <0>;
100 sprd,hw-channels = <30 0x8c20>;
/linux/Documentation/devicetree/bindings/dma/xilinx/
H A Dxilinx_dma.txt56 0-255. Setting this value to zero disables the delay timer interrupt.
93 reg = < 0x40030000 0x10000 >;
94 dma-ranges = <0x00000000 0x00000000 0x40000000>;
95 xlnx,num-fstores = <0x8>;
96 xlnx,flush-fsync = <0x1>;
97 xlnx,addrwidth = <0x2
[all...]
/linux/arch/arm64/boot/dts/sprd/
H A Dwhale2.dtsi23 reg = <0 0x20210000 0 0x10000>;
28 reg = <0 0x402b0000 0 0x10000>;
33 reg = <0 0x402e000
[all...]
/linux/arch/arm/boot/dts/nxp/lpc/
H A Dlpc32xx.dtsi20 #size-cells = <0>;
22 cpu@0 {
25 reg = <0x0>;
32 #clock-cells = <0>;
39 #clock-cells = <0>;
49 ranges = <0x00000000 0x00000000 0x10000000>,
50 <0x20000000 0x2000000
[all...]
/linux/arch/m68k/ifpsp060/
H A Dfpsp.sa1 .long 0x60ff0000,0x17400000,0x60ff0000,0x15f40000
2 .long 0x60ff0000,0x02b60000,0x60ff0000,0x04700000
3 .long 0x60ff0000,0x1b10000
[all...]
/linux/arch/arm/boot/dts/renesas/
H A Dr9a06g032.dtsi19 #size-cells = <0>;
21 cpu@0 {
24 reg = <0>;
34 cpu-release-addr = <0 0x4000c204>;
39 #clock-cells = <0>;
41 clock-frequency = <0>;
45 #clock-cells = <0>;
51 #clock-cells = <0>;
53 clock-frequency = <0>;
[all...]
/linux/arch/arm/mach-lpc32xx/
H A Dlpc32xx.h17 * AHB 0 physical base addresses
19 #define LPC32XX_SLC_BASE 0x20020000
20 #define LPC32XX_SSP0_BASE 0x20084000
21 #define LPC32XX_SPI1_BASE 0x20088000
22 #define LPC32XX_SSP1_BASE 0x2008C000
23 #define LPC32XX_SPI2_BASE 0x20090000
24 #define LPC32XX_I2S0_BASE 0x20094000
25 #define LPC32XX_SD_BASE 0x20098000
26 #define LPC32XX_I2S1_BASE 0x2009C000
27 #define LPC32XX_MLC_BASE 0x200A800
[all...]
/linux/arch/arm/boot/dts/nxp/vf/
H A Dvfxxx.dtsi33 #clock-cells = <0>;
39 #clock-cells = <0>;
46 offset = <0x0>;
47 mask = <0x1000>;
66 reg = <0x40000000 0x00070000>;
71 reg = <0x40001000 0x800>;
76 reg = <0x40001800 0x40
[all...]
/linux/arch/m68k/ifpsp060/src/
H A Dfplsp.S37 short 0x0000
39 short 0x0000
41 short 0x0000
44 short 0x0000
46 short 0x0000
48 short 0x0000
51 short 0x0000
53 short 0x0000
55 short 0x0000
58 short 0x000
[all...]
H A Dfpsp.S43 set _off_bsun, 0x00
44 set _off_snan, 0x04
45 set _off_operr, 0x08
46 set _off_ovfl, 0x0c
47 set _off_unfl, 0x10
48 set _off_dz, 0x14
49 set _off_inex, 0x18
50 set _off_fline, 0x1c
51 set _off_fpu_dis, 0x20
52 set _off_trap, 0x2
[all...]
/linux/arch/arm64/boot/dts/st/
H A Dstm32mp251.dtsi18 #size-cells = <0>;
20 cpu0: cpu@0 {
23 reg = <0>;
39 arm,smc-id = <0xb200005a>;
45 #clock-cells = <0>;
47 clock-frequency = <0>;
51 #clock-cells = <0>;
68 #size-cells = <0>;
69 linaro,optee-channel-id = <0>;
72 reg = <0x1
[all...]
/linux/drivers/net/wireless/realtek/rtw88/
H A Drtw8822c_table.c16 0x83000000, 0x00000000, 0x40000000, 0x00000000,
17 0x1D90, 0x300001FF,
18 0x1D90, 0x300101FE,
19 0x1D90, 0x300201F
[all...]