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/linux/Documentation/devicetree/bindings/display/
H A Dapple,h7-display-pipe-mipi.yaml36 port@0:
45 - port@0
59 reg = <0x28200000 0xc000>;
64 #size-cells = <0>;
66 port@0 {
67 reg = <0>;
H A Dapple,h7-display-pipe.yaml72 reg = <0x28200000 0xc000>,
73 <0x28400000 0x4000>;
80 iommus = <&displaydfr_dart 0>;
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt7988a.dtsi46 #size-cells = <0>;
48 cpu0: cpu@0 {
50 reg = <0x0>;
62 reg = <0x1>;
74 reg = <0x2>;
86 reg = <0x3>;
96 cluster0_opp: opp-table-0 {
122 #clock-cells = <0>;
144 reg = <0 0x4300000
[all...]
/linux/arch/arm64/boot/dts/toshiba/
H A Dtmpv7708.dtsi14 /memreserve/ 0x81000000 0x00300000; /* cpu-release-addr */
23 #size-cells = <0>;
57 cpu0: cpu@0 {
61 cpu-release-addr = <0x0 0x81100000>;
62 reg = <0x00>;
69 cpu-release-addr = <0x0 0x81100000>;
70 reg = <0x0
[all...]
/linux/arch/arm64/boot/dts/apple/
H A Dt8103.dtsi28 #size-cells = <0>;
62 cpu_e0: cpu@0 {
65 reg = <0x0 0x0>;
67 cpu-release-addr = <0 0>; /* To be filled by loader */
72 i-cache-size = <0x20000>;
73 d-cache-size = <0x10000>;
79 reg = <0x0 0x
[all...]
H A Dt8112.dtsi28 #size-cells = <0>;
62 cpu_e0: cpu@0 {
65 reg = <0x0 0x0>;
67 cpu-release-addr = <0 0>; /* To be filled by loader */
72 i-cache-size = <0x20000>;
73 d-cache-size = <0x10000>;
79 reg = <0x0 0x
[all...]
/linux/arch/arm64/boot/dts/qcom/
H A Dipq9574.dtsi26 #clock-cells = <0>;
31 #clock-cells = <0>;
37 #clock-cells = <0>;
42 #clock-cells = <0>;
48 #size-cells = <0>;
50 cpu0: cpu@0 {
53 reg = <0x0>;
66 reg = <0x1>;
79 reg = <0x2>;
92 reg = <0x
[all...]
/linux/arch/powerpc/include/asm/
H A Dppc-opcode.h13 #define __REG_R0 0
46 #define __REGA0_0 0
80 #define _R0 0
113 #define IMM_L(i) ((uintptr_t)(i) & 0xffff)
114 #define IMM_DS(i) ((uintptr_t)(i) & 0xfffc)
115 #define IMM_DQ(i) ((uintptr_t)(i) & 0xfff0)
116 #define IMM_D0(i) (((uintptr_t)(i) >> 16) & 0x3ffff)
122 * top half to negate the effect (i.e. 0xffff + 1 = 0x(1)0000).
128 (((uintptr_t)(i) & 0x800
[all...]
/linux/drivers/video/fbdev/
H A Di740fb.c120 #define REG_DDC_DRIVE 0x62
121 #define REG_DDC_STATE 0x63
130 i740outreg_mask(par, XRX, REG_DDC_STATE, val ? DDC_SCL : 0, DDC_SCL); in i740fb_ddc_setscl()
138 i740outreg_mask(par, XRX, REG_DDC_STATE, val ? DDC_SDA : 0, DDC_SDA); in i740fb_ddc_setsda()
145 i740outreg_mask(par, XRX, REG_DDC_DRIVE, 0, DDC_SCL); in i740fb_ddc_getscl()
154 i740outreg_mask(par, XRX, REG_DDC_DRIVE, 0, DDC_SDA); in i740fb_ddc_getsda()
189 return 0; in i740fb_open()
197 if (par->ref_count == 0) { in i740fb_release()
206 return 0; in i740fb_release()
224 wm = 0x1812000 in i740_calc_fifo()
[all...]
/linux/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dpolaris10_pwrvirus.h27 #define mmCP_HYP_MEC1_UCODE_ADDR 0xf81a
28 #define mmCP_HYP_MEC1_UCODE_DATA 0xf81b
29 #define mmCP_HYP_MEC2_UCODE_ADDR 0xf81c
30 #define mmCP_HYP_MEC2_UCODE_DATA 0xf81d
49 { 0x00000000, mmRLC_CNTL },
50 { 0x00000002, mmRLC_SRM_CNTL },
51 { 0x15000000, mmCP_ME_CNTL },
52 { 0x50000000, mmCP_MEC_CNTL },
53 { 0x80000004, mmCP_DFY_CNTL },
54 { 0x0840800
[all...]