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/linux/tools/perf/pmu-events/arch/x86/amdzen5/
H A Dinst-cache.json4 "EventCode": "0x82",
9 "EventCode": "0x83",
14 "EventCode": "0x188",
16 "UMask": "0x02"
20 "EventCode": "0x188",
22 "UMask": "0x04"
26 "EventCode": "0x188",
2 { global() object
[all...]
/linux/drivers/media/platform/chips-media/coda/
H A Dcoda_regs.h14 #define CODA_REG_BIT_CODE_RUN 0x000
15 #define CODA_REG_RUN_ENABLE (1 << 0)
16 #define CODA_REG_BIT_CODE_DOWN 0x004
17 #define CODA_DOWN_ADDRESS_SET(x) (((x) & 0xffff) << 16)
18 #define CODA_DOWN_DATA_SET(x) ((x) & 0xffff)
19 #define CODA_REG_BIT_HOST_IN_REQ 0x008
20 #define CODA_REG_BIT_INT_CLEAR 0x00c
21 #define CODA_REG_BIT_INT_CLEAR_SET 0x1
22 #define CODA_REG_BIT_INT_STATUS 0x010
23 #define CODA_REG_BIT_CODE_RESET 0x01
[all...]
/linux/arch/powerpc/boot/dts/
H A Dadder875-redboot.dts24 #size-cells = <0>;
26 PowerPC,875@0 {
28 reg = <0>;
33 timebase-frequency = <0>;
34 bus-frequency = <0>;
35 clock-frequency = <0>;
43 reg = <0 0x01000000>;
51 reg = <0xfa200100 0x4
[all...]
H A Dadder875-uboot.dts24 #size-cells = <0>;
26 PowerPC,875@0 {
28 reg = <0>;
33 timebase-frequency = <0>;
34 bus-frequency = <0>;
35 clock-frequency = <0>;
43 reg = <0 0x01000000>;
51 reg = <0xff000100 0x4
[all...]
H A Dep88xc.dts19 #size-cells = <0>;
21 PowerPC,885@0 {
23 reg = <0x0>;
28 timebase-frequency = <0>;
29 bus-frequency = <0>;
30 clock-frequency = <0>;
38 reg = <0x0 0x0>;
45 reg = <0xfa200100 0x4
[all...]
H A Dmpc885ads.dts19 #size-cells = <0>;
21 PowerPC,885@0 {
23 reg = <0x0>;
28 timebase-frequency = <0>;
29 bus-frequency = <0>;
30 clock-frequency = <0>;
38 reg = <0x0 0x0>;
45 reg = <0xff000100 0x4
[all...]
H A Dmpc866ads.dts19 #size-cells = <0>;
21 PowerPC,866@0 {
23 reg = <0x0>;
26 d-cache-size = <0x2000>; // L1, 8K
27 i-cache-size = <0x4000>; // L1, 16K
28 timebase-frequency = <0>;
29 bus-frequency = <0>;
30 clock-frequency = <0>;
38 reg = <0x0 0x80000
[all...]
H A Dtqm8xx.dts26 #size-cells = <0>;
28 PowerPC,860@0 {
30 reg = <0x0>;
33 d-cache-size = <0x1000>; // L1, 4K
34 i-cache-size = <0x1000>; // L1, 4K
35 timebase-frequency = <0>;
36 bus-frequency = <0>;
37 clock-frequency = <0>;
45 reg = <0x0 0x200000
[all...]
/linux/drivers/clk/hisilicon/
H A Dcrg-hi3798cv200.c45 { HISTB_OSC_CLK, "clk_osc", NULL, 0, 24000000, },
46 { HISTB_APB_CLK, "clk_apb", NULL, 0, 100000000, },
47 { HISTB_AHB_CLK, "clk_ahb", NULL, 0, 200000000, },
48 { HI3798CV200_FIXED_12M, "12m", NULL, 0, 12000000, },
49 { HI3798CV200_FIXED_24M, "24m", NULL, 0, 24000000, },
50 { HI3798CV200_FIXED_25M, "25m", NULL, 0, 25000000, },
51 { HI3798CV200_FIXED_48M, "48m", NULL, 0, 48000000, },
52 { HI3798CV200_FIXED_50M, "50m", NULL, 0, 50000000, },
53 { HI3798CV200_FIXED_60M, "60m", NULL, 0, 60000000, },
54 { HI3798CV200_FIXED_75M, "75m", NULL, 0, 7500000
[all...]
/linux/drivers/gpu/drm/nouveau/nvkm/falcon/
H A Dv1.c38 reg = start | BIT(24) | (secure ? BIT(28) : 0); in nvkm_falcon_v1_load_imem()
39 nvkm_falcon_wr32(falcon, 0x180 + (port * 16), reg); in nvkm_falcon_v1_load_imem()
40 for (i = 0; i < size / 4; i++) { in nvkm_falcon_v1_load_imem()
42 if ((i & 0x3f) == 0) in nvkm_falcon_v1_load_imem()
43 nvkm_falcon_wr32(falcon, 0x188 + (port * 16), tag++); in nvkm_falcon_v1_load_imem()
44 nvkm_falcon_wr32(falcon, 0x184 + (port * 16), ((u32 *)data)[i]); in nvkm_falcon_v1_load_imem()
55 if ((i & 0x3f) == 0) in nvkm_falcon_v1_load_imem()
[all...]
/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_doorbell.h100 AMDGPU_DOORBELL_KIQ = 0x000,
101 AMDGPU_DOORBELL_HIQ = 0x001,
102 AMDGPU_DOORBELL_DIQ = 0x002,
103 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
104 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
105 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
106 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
107 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
108 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
109 AMDGPU_DOORBELL_MEC_RING6 = 0x01
[all...]
/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp-pcs-v4_20.h10 #define QPHY_V4_20_PCS_RX_SIGDET_LVL 0x188
11 #define QPHY_V4_20_PCS_EQ_CONFIG2 0x1d8
12 #define QPHY_V4_20_PCS_EQ_CONFIG4 0x1e0
13 #define QPHY_V4_20_PCS_EQ_CONFIG5 0x1e4
H A Dphy-qcom-qmp-pcs-v5_20.h9 #define QPHY_V5_20_PCS_INSIG_SW_CTRL7 0x060
10 #define QPHY_V5_20_PCS_INSIG_MX_CTRL7 0x07c
11 #define QPHY_V5_20_PCS_LOCK_DETECT_CONFIG1 0x0c4
12 #define QPHY_V5_20_PCS_LOCK_DETECT_CONFIG2 0x0c8
13 #define QPHY_V5_20_PCS_G3S2_PRE_GAIN 0x170
14 #define QPHY_V5_20_PCS_RX_SIGDET_LVL 0x188
15 #define QPHY_V5_20_PCS_ALIGN_DETECT_CONFIG1 0x1b8
16 #define QPHY_V5_20_PCS_ALIGN_DETECT_CONFIG2 0x1bc
17 #define QPHY_V5_20_PCS_EQ_CONFIG2 0x1d
[all...]
H A Dphy-qcom-qmp-pcs-v6.h10 #define QPHY_V6_PCS_SW_RESET 0x000
11 #define QPHY_V6_PCS_PCS_STATUS1 0x014
12 #define QPHY_V6_PCS_POWER_DOWN_CONTROL 0x040
13 #define QPHY_V6_PCS_START_CONTROL 0x044
14 #define QPHY_V6_PCS_POWER_STATE_CONFIG1 0x090
15 #define QPHY_V6_PCS_LOCK_DETECT_CONFIG1 0x0c4
16 #define QPHY_V6_PCS_LOCK_DETECT_CONFIG2 0x0c8
17 #define QPHY_V6_PCS_LOCK_DETECT_CONFIG3 0x0cc
18 #define QPHY_V6_PCS_LOCK_DETECT_CONFIG6 0x0d8
19 #define QPHY_V6_PCS_REFGEN_REQ_CONFIG1 0x0d
[all...]
H A Dphy-qcom-qmp-pcs-v8.h10 #define QPHY_V8_PCS_SW_RESET 0x000
11 #define QPHY_V8_PCS_PCS_STATUS1 0x014
12 #define QPHY_V8_PCS_POWER_DOWN_CONTROL 0x040
13 #define QPHY_V8_PCS_START_CONTROL 0x044
14 #define QPHY_V8_PCS_POWER_STATE_CONFIG1 0x090
15 #define QPHY_V8_PCS_LOCK_DETECT_CONFIG1 0x0c4
16 #define QPHY_V8_PCS_LOCK_DETECT_CONFIG2 0x0c8
17 #define QPHY_V8_PCS_LOCK_DETECT_CONFIG3 0x0cc
18 #define QPHY_V8_PCS_LOCK_DETECT_CONFIG6 0x0d8
19 #define QPHY_V8_PCS_REFGEN_REQ_CONFIG1 0x0d
[all...]
H A Dphy-qcom-qmp-pcs-v6-n4.h10 #define QPHY_V6_N4_PCS_SW_RESET 0x000
11 #define QPHY_V6_N4_PCS_PCS_STATUS1 0x014
12 #define QPHY_V6_N4_PCS_POWER_DOWN_CONTROL 0x040
13 #define QPHY_V6_N4_PCS_START_CONTROL 0x044
14 #define QPHY_V6_N4_PCS_POWER_STATE_CONFIG1 0x090
15 #define QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG1 0x0c4
16 #define QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG2 0x0c8
17 #define QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG3 0x0cc
18 #define QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG6 0x0d8
19 #define QPHY_V6_N4_PCS_REFGEN_REQ_CONFIG1 0x0d
[all...]
H A Dphy-qcom-qmp-pcs-v7.h10 #define QPHY_V7_PCS_SW_RESET 0x000
11 #define QPHY_V7_PCS_PCS_STATUS1 0x014
12 #define QPHY_V7_PCS_POWER_DOWN_CONTROL 0x040
13 #define QPHY_V7_PCS_START_CONTROL 0x044
14 #define QPHY_V7_PCS_POWER_STATE_CONFIG1 0x090
15 #define QPHY_V7_PCS_LOCK_DETECT_CONFIG1 0x0c4
16 #define QPHY_V7_PCS_LOCK_DETECT_CONFIG2 0x0c8
17 #define QPHY_V7_PCS_LOCK_DETECT_CONFIG3 0x0cc
18 #define QPHY_V7_PCS_LOCK_DETECT_CONFIG6 0x0d8
19 #define QPHY_V7_PCS_REFGEN_REQ_CONFIG1 0x0d
[all...]
H A Dphy-qcom-qmp-pcs-v5.h10 #define QPHY_V5_PCS_SW_RESET 0x000
11 #define QPHY_V5_PCS_PCS_STATUS1 0x014
12 #define QPHY_V5_PCS_POWER_DOWN_CONTROL 0x040
13 #define QPHY_V5_PCS_START_CONTROL 0x044
14 #define QPHY_V5_PCS_LOCK_DETECT_CONFIG1 0x0c4
15 #define QPHY_V5_PCS_LOCK_DETECT_CONFIG2 0x0c8
16 #define QPHY_V5_PCS_LOCK_DETECT_CONFIG3 0x0cc
17 #define QPHY_V5_PCS_LOCK_DETECT_CONFIG6 0x0d8
18 #define QPHY_V5_PCS_REFGEN_REQ_CONFIG1 0x0dc
19 #define QPHY_V5_PCS_G3S2_PRE_GAIN 0x17
[all...]
H A Dphy-qcom-qmp-qserdes-txrx-v6_20.h9 #define QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX 0x30
10 #define QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX 0x34
11 #define QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN 0xac
12 #define QSERDES_V6_20_TX_LANE_MODE_1 0x78
13 #define QSERDES_V6_20_TX_LANE_MODE_2 0x7c
14 #define QSERDES_V6_20_TX_LANE_MODE_3 0x80
16 #define QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2 0x08
17 #define QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3 0x0c
18 #define QSERDES_V6_20_RX_UCDR_SO_GAIN_RATE_2 0x18
19 #define QSERDES_V6_20_RX_UCDR_PI_CONTROLS 0x2
[all...]
H A Dphy-qcom-qmp-qserdes-txrx-v7.h9 #define QSERDES_V7_TX_CLKBUF_ENABLE 0x08
10 #define QSERDES_V7_TX_RESET_TSYNC_EN 0x1c
11 #define QSERDES_V7_TX_PRE_STALL_LDO_BOOST_EN 0x20
12 #define QSERDES_V7_TX_TX_BAND 0x24
13 #define QSERDES_V7_TX_INTERFACE_SELECT 0x2c
14 #define QSERDES_V7_TX_RES_CODE_LANE_TX 0x34
15 #define QSERDES_V7_TX_RES_CODE_LANE_RX 0x38
16 #define QSERDES_V7_TX_RES_CODE_LANE_OFFSET_TX 0x3c
17 #define QSERDES_V7_TX_RES_CODE_LANE_OFFSET_RX 0x40
18 #define QSERDES_V7_TX_PARRATE_REC_DETECT_IDLE_EN 0x6
[all...]
/linux/drivers/gpu/drm/omapdrm/dss/
H A Dhdmi4_core.h15 #define HDMI_CORE_SYS_VND_IDL 0x0
16 #define HDMI_CORE_SYS_DEV_IDL 0x8
17 #define HDMI_CORE_SYS_DEV_IDH 0xC
18 #define HDMI_CORE_SYS_DEV_REV 0x10
19 #define HDMI_CORE_SYS_SRST 0x14
20 #define HDMI_CORE_SYS_SYS_CTRL1 0x20
21 #define HDMI_CORE_SYS_SYS_STAT 0x24
22 #define HDMI_CORE_SYS_SYS_CTRL3 0x28
23 #define HDMI_CORE_SYS_DCTL 0x34
24 #define HDMI_CORE_SYS_DE_DLY 0xC
[all...]
/linux/drivers/video/fbdev/omap2/omapfb/dss/
H A Dhdmi4_core.h15 #define HDMI_CORE_SYS_VND_IDL 0x0
16 #define HDMI_CORE_SYS_DEV_IDL 0x8
17 #define HDMI_CORE_SYS_DEV_IDH 0xC
18 #define HDMI_CORE_SYS_DEV_REV 0x10
19 #define HDMI_CORE_SYS_SRST 0x14
20 #define HDMI_CORE_SYS_SYS_CTRL1 0x20
21 #define HDMI_CORE_SYS_SYS_STAT 0x24
22 #define HDMI_CORE_SYS_SYS_CTRL3 0x28
23 #define HDMI_CORE_SYS_DCTL 0x34
24 #define HDMI_CORE_SYS_DE_DLY 0xC
[all...]
/linux/include/dt-bindings/clock/
H A Ddm816.h8 #define DM816_CLKCTRL_OFFSET 0x0
12 #define DM816_USB_OTG_HS_CLKCTRL DM816_CLKCTRL_INDEX(0x58)
15 #define DM816_UART1_CLKCTRL DM816_CLKCTRL_INDEX(0x150)
16 #define DM816_UART2_CLKCTRL DM816_CLKCTRL_INDEX(0x154)
17 #define DM816_UART3_CLKCTRL DM816_CLKCTRL_INDEX(0x158)
18 #define DM816_GPIO1_CLKCTRL DM816_CLKCTRL_INDEX(0x15c)
19 #define DM816_GPIO2_CLKCTRL DM816_CLKCTRL_INDEX(0x160)
20 #define DM816_I2C1_CLKCTRL DM816_CLKCTRL_INDEX(0x164)
21 #define DM816_I2C2_CLKCTRL DM816_CLKCTRL_INDEX(0x168)
22 #define DM816_TIMER1_CLKCTRL DM816_CLKCTRL_INDEX(0x17
[all...]
/linux/Documentation/devicetree/bindings/arm/hisilicon/controller/
H A Dhi3798cv200-perictrl.yaml48 reg = <0x8a20000 0x1000>;
51 ranges = <0x0 0x8a20000 0x1000>;
55 reg = <0x850 0x8>;
58 resets = <&crg 0x188 4>;
/linux/arch/xtensa/include/asm/
H A Dmxregs.h20 * 00nn 0...0p..p Interrupt Routing, route IRQ n to processor p
21 * 01pp 0...0d..d 16 bits (d) 'ored' as single IPI to processor p
22 * 0180 0...0m..m Clear enable specified by mask (m)
23 * 0184 0...0m..m Set enable specified by mask (m)
24 * 0190 0...0
[all...]

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