Home
last modified time | relevance | path

Searched +full:0 +full:x133 (Results 1 – 25 of 53) sorted by relevance

123

/linux/drivers/char/hw_random/
H A Dn2rng.h11 #define RNG_v1_CTL_WAIT 0x0000000001fffe00ULL /* Minimum wait time */
13 #define RNG_v1_CTL_BYPASS 0x0000000000000100ULL /* VCO voltage source */
14 #define RNG_v1_CTL_VCO 0x00000000000000c0ULL /* VCO rate control */
16 #define RNG_v1_CTL_ASEL 0x0000000000000030ULL /* Analog MUX select */
21 #define RNG_CTL_LFSR 0x0000000000000008ULL /* Use LFSR or plain shift */
22 #define RNG_CTL_ES3 0x0000000000000004ULL /* Enable entropy source 3 */
23 #define RNG_CTL_ES2 0x0000000000000002ULL /* Enable entropy source 2 */
24 #define RNG_CTL_ES1 0x0000000000000001ULL /* Enable entropy source 1 */
27 #define RNG_v2_CTL_WAIT 0x0000000007fff800ULL /* Minimum wait time */
29 #define RNG_v2_CTL_BYPASS 0x0000000000000400UL
[all...]
/linux/arch/arm/boot/dts/qcom/
H A Dpm8058.dtsi9 #size-cells = <0>;
13 reg = <0x1c>;
22 reg = <0x48>;
28 reg = <0x4a>;
34 reg = <0x50>;
37 gpio-ranges = <&pm8058_mpps 0 0 12>;
44 reg = <0x131>;
50 reg = <0x132>;
56 reg = <0x13
[all...]
/linux/sound/soc/codecs/
H A Dtas2764-quirks.h10 #define ENABLED_APPLE_QUIRKS 0x3f
15 #define TAS2764_NOISE_GATE_DISABLE BIT(0)
18 REG_SEQ0(TAS2764_REG(0x0, 0x35), 0xb0)
27 REG_SEQ0(TAS2764_REG(0x0, 0x6b), 0x41)
36 REG_SEQ0(TAS2764_REG(0x0, 0x7
[all...]
/linux/drivers/scsi/qla2xxx/
H A Dqla_devtbl.h2 #define QLA_MODEL_NAMES 0x5C
8 "QLA2340", "133MHz PCI-X to 2Gb FC, Single Channel", /* 0x100 */
9 "QLA2342", "133MHz PCI-X to 2Gb FC, Dual Channel", /* 0x101 */
10 "QLA2344", "133MHz PCI-X to 2Gb FC, Quad Channel", /* 0x102 */
11 "QCP2342", "cPCI to 2Gb FC, Dual Channel", /* 0x103 */
12 "QSB2340", "SBUS to 2Gb FC, Single Channel", /* 0x104 */
13 "QSB2342", "SBUS to 2Gb FC, Dual Channel", /* 0x105 */
14 "QLA2310", "Sun 66MHz PCI-X to 2Gb FC, Single Channel", /* 0x106 */
15 "QLA2332", "Sun 66MHz PCI-X to 2Gb FC, Single Channel", /* 0x107 */
16 "QCP2332", "Sun cPCI to 2Gb FC, Dual Channel", /* 0x10
[all...]
/linux/drivers/gpu/drm/radeon/
H A Dppsmc.h28 #define PPSMC_SWSTATE_FLAG_DC 0x01
29 #define PPSMC_SWSTATE_FLAG_UVD 0x02
30 #define PPSMC_SWSTATE_FLAG_VCE 0x04
31 #define PPSMC_SWSTATE_FLAG_PCIE_X1 0x08
33 #define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00
34 #define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01
35 #define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff
37 #define PPSMC_SYSTEMFLAG_GPIO_DC 0x01
38 #define PPSMC_SYSTEMFLAG_STEPVDDC 0x02
39 #define PPSMC_SYSTEMFLAG_GDDR5 0x0
[all...]
/linux/drivers/media/pci/intel/ipu6/
H A Dipu6-isys-dwc-phy.c17 #define IPU6_DWC_DPHY_BASE(i) (0x238038 + 0x34 * (i))
18 #define IPU6_DWC_DPHY_RSTZ 0x00
19 #define IPU6_DWC_DPHY_SHUTDOWNZ 0x04
20 #define IPU6_DWC_DPHY_HSFREQRANGE 0x08
21 #define IPU6_DWC_DPHY_CFGCLKFREQRANGE 0x0c
22 #define IPU6_DWC_DPHY_TEST_IFC_ACCESS_MODE 0x10
23 #define IPU6_DWC_DPHY_TEST_IFC_REQ 0x14
24 #define IPU6_DWC_DPHY_TEST_IFC_REQ_COMPLETION 0x18
25 #define IPU6_DWC_DPHY_DFT_CTRL0 0x2
[all...]
/linux/drivers/gpu/drm/amd/pm/legacy-dpm/
H A Dppsmc.h28 #define PPSMC_SWSTATE_FLAG_DC 0x01
29 #define PPSMC_SWSTATE_FLAG_UVD 0x02
30 #define PPSMC_SWSTATE_FLAG_VCE 0x04
31 #define PPSMC_SWSTATE_FLAG_PCIE_X1 0x08
33 #define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00
34 #define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01
35 #define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff
37 #define PPSMC_SYSTEMFLAG_GPIO_DC 0x01
38 #define PPSMC_SYSTEMFLAG_STEPVDDC 0x02
39 #define PPSMC_SYSTEMFLAG_GDDR5 0x0
[all...]
/linux/Documentation/devicetree/bindings/opp/
H A Dopp-v2-kryo-cpu.yaml43 '^opp-?[0-9]+$':
58 0: MSM8996, speedbin 0
65 0-3: unused
66 4: MSM8996SG, speedbin 0
72 0: IPQ8062
84 '^opp-microvolt-speed[0-9]+-pvs[0-9]+$': true
97 '^opp-?[0-9]+$':
113 #size-cells = <0>;
[all...]
/linux/include/linux/mfd/da9062/
H A Dregisters.h9 #define DA9062_PMIC_DEVICE_ID 0x62
10 #define DA9062_PMIC_VARIANT_MRC_AA 0x01
11 #define DA9062_PMIC_VARIANT_VRC_DA9061 0x01
12 #define DA9062_PMIC_VARIANT_VRC_DA9062 0x02
20 #define DA9062AA_PAGE_CON 0x000
21 #define DA9062AA_STATUS_A 0x001
22 #define DA9062AA_STATUS_B 0x002
23 #define DA9062AA_STATUS_D 0x004
24 #define DA9062AA_FAULT_LOG 0x005
25 #define DA9062AA_EVENT_A 0x00
[all...]
/linux/drivers/net/wireless/broadcom/b43/
H A Dradio_2057.h9 #define R2057_DACBUF_VINCM_CORE0 0x000
10 #define R2057_IDCODE 0x001
11 #define R2057_RCCAL_MASTER 0x002
12 #define R2057_RCCAL_CAP_SIZE 0x003
13 #define R2057_RCAL_CONFIG 0x004
14 #define R2057_GPAIO_CONFIG 0x005
15 #define R2057_GPAIO_SEL1 0x006
16 #define R2057_GPAIO_SEL0 0x007
17 #define R2057_CLPO_CONFIG 0x008
18 #define R2057_BANDGAP_CONFIG 0x00
[all...]
/linux/arch/sparc/kernel/
H A Dttable_64.S17 tl0_resv000: BOOT_KERNEL BTRAP(0x1) BTRAP(0x2) BTRAP(0x3)
18 tl0_resv004: BTRAP(0x4) BTRAP(0x5) BTRAP(0x6) BTRAP(0x7)
24 tl0_resv00b: BTRAP(0xb) BTRAP(0xc) BTRAP(0x
[all...]
/linux/arch/x86/math-emu/
H A Dget_address.c30 #define FPU_WRITE_BIT 0x10
71 /* Decode the SIB byte. This function assumes mod != 0 */
86 if ((mod == 0) && (base == 5)) in sib()
87 offset = 0; /* No base register */ in sib()
109 } else if (mod == 2 || base == 5) { /* The second condition also has mod==0 */ in sib()
128 EXCEPTION(EX_INTERNAL | 0x130); in vm86_segment()
146 /* segment is unsigned, so this also detects if segment was 0: */ in pm_address()
148 EXCEPTION(EX_INTERNAL | 0x132); in pm_address()
169 limit = 0xffffffff; in pm_address()
173 seg_top = 0xfffffff in pm_address()
[all...]
H A Derrors.c37 #if 0
49 if ((byte1 & 0xf8) == 0xd8)
58 printk("%02x (%02x+%d)\n", FPU_modrm, FPU_modrm & 0xf8,
71 #endif /* 0 */
96 for (i = 0; i < MAX_PRINTED_BYTES; i++) { in FPU_printall()
98 if ((byte1 & 0xf8) == 0xd8) { in FPU_printall()
112 FPU_modrm & 0xf8, FPU_modrm & 7); in FPU_printall()
134 printk("SW: condition bit 0\ in FPU_printall()
[all...]
/linux/sound/drivers/opl4/
H A Dyrw801.c40 snd_opl4_read_memory(opl4, buf, 0x001200, 15); in snd_yrw801_detect()
43 snd_opl4_read_memory(opl4, buf, 0x1ffffe, 2); in snd_yrw801_detect()
44 if (buf[0] != 0x01) in snd_yrw801_detect()
46 dev_dbg(opl4->card->dev, "YRW801 ROM version %02x.%02x\n", buf[0], buf[1]); in snd_yrw801_detect()
47 return 0; in snd_yrw801_detect()
58 {0x14, 0x27, {0x12c,7474,100, 0,
[all...]
/linux/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dsmu7_ppsmc.h30 #define PPSMC_MSG_SetGBDroopSettings ((uint16_t) 0x305)
32 #define PPSMC_SWSTATE_FLAG_DC 0x01
33 #define PPSMC_SWSTATE_FLAG_UVD 0x02
34 #define PPSMC_SWSTATE_FLAG_VCE 0x04
36 #define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00
37 #define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01
38 #define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff
40 #define PPSMC_SYSTEMFLAG_GPIO_DC 0x01
41 #define PPSMC_SYSTEMFLAG_STEPVDDC 0x02
42 #define PPSMC_SYSTEMFLAG_GDDR5 0x0
[all...]
H A Dtonga_ppsmc.h29 #define PPSMC_SWSTATE_FLAG_DC 0x01
30 #define PPSMC_SWSTATE_FLAG_UVD 0x02
31 #define PPSMC_SWSTATE_FLAG_VCE 0x04
32 #define PPSMC_SWSTATE_FLAG_PCIE_X1 0x08
34 #define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00
35 #define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01
36 #define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff
38 #define PPSMC_SYSTEMFLAG_GPIO_DC 0x01
39 #define PPSMC_SYSTEMFLAG_STEPVDDC 0x02
40 #define PPSMC_SYSTEMFLAG_GDDR5 0x0
[all...]
H A Dfiji_ppsmc.h30 #define PPSMC_SWSTATE_FLAG_DC 0x01
31 #define PPSMC_SWSTATE_FLAG_UVD 0x02
32 #define PPSMC_SWSTATE_FLAG_VCE 0x04
34 #define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00
35 #define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01
36 #define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff
38 #define PPSMC_SYSTEMFLAG_GPIO_DC 0x01
39 #define PPSMC_SYSTEMFLAG_STEPVDDC 0x02
40 #define PPSMC_SYSTEMFLAG_GDDR5 0x04
42 #define PPSMC_SYSTEMFLAG_DISABLE_BABYSTEP 0x0
[all...]
/linux/drivers/media/dvb-frontends/
H A Ddrxd_map_firm.h18 #define HI_COMM_EXEC__A 0x400000
19 #define HI_COMM_MB__A 0x400002
20 #define HI_CT_REG_COMM_STATE__A 0x410001
21 #define HI_RA_RAM_SRV_RES__A 0x420031
22 #define HI_RA_RAM_SRV_CMD__A 0x420032
23 #define HI_RA_RAM_SRV_CMD_RESET 0x2
24 #define HI_RA_RAM_SRV_CMD_CONFIG 0x3
25 #define HI_RA_RAM_SRV_CMD_EXECUTE 0x6
26 #define HI_RA_RAM_SRV_RST_KEY__A 0x420033
27 #define HI_RA_RAM_SRV_RST_KEY_ACT 0x397
[all...]
/linux/include/linux/mfd/da9063/
H A Dregisters.h18 /* Page 0 : I2C access 0x000 - 0x0FF SPI access 0x000 - 0x07F */
19 /* Page 1 : SPI access 0x080 - 0x0FF */
20 /* Page 2 : I2C access 0x100 - 0x1FF SPI access 0x10
[all...]
/linux/include/uapi/linux/
H A Dinput-event-codes.h23 #define INPUT_PROP_POINTER 0x00 /* needs a pointer */
24 #define INPUT_PROP_DIRECT 0x01 /* direct input devices */
25 #define INPUT_PROP_BUTTONPAD 0x02 /* has button(s) under pad */
26 #define INPUT_PROP_SEMI_MT 0x03 /* touch rectangle only */
27 #define INPUT_PROP_TOPBUTTONPAD 0x04 /* softbuttons at top of pad */
28 #define INPUT_PROP_POINTING_STICK 0x05 /* is a pointing stick */
29 #define INPUT_PROP_ACCELEROMETER 0x06 /* has accelerometer */
31 #define INPUT_PROP_MAX 0x1f
38 #define EV_SYN 0x00
39 #define EV_KEY 0x0
[all...]
/linux/include/dt-bindings/input/
H A Dlinux-event-codes.h23 #define INPUT_PROP_POINTER 0x00 /* needs a pointer */
24 #define INPUT_PROP_DIRECT 0x01 /* direct input devices */
25 #define INPUT_PROP_BUTTONPAD 0x02 /* has button(s) under pad */
26 #define INPUT_PROP_SEMI_MT 0x03 /* touch rectangle only */
27 #define INPUT_PROP_TOPBUTTONPAD 0x04 /* softbuttons at top of pad */
28 #define INPUT_PROP_POINTING_STICK 0x05 /* is a pointing stick */
29 #define INPUT_PROP_ACCELEROMETER 0x06 /* has accelerometer */
31 #define INPUT_PROP_MAX 0x1f
38 #define EV_SYN 0x00
39 #define EV_KEY 0x0
[all...]
/linux/arch/powerpc/include/asm/
H A Dreg_booke.h23 #define MSR_CM_LG 31 /* Computation Mode (0=32-bit, 1=64-bit) */
48 #define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */
49 #define SPRN_IVPR 0x03F /* Interrupt Vector Prefix Register */
50 #define SPRN_USPRG0 0x100 /* User Special Purpose Register General 0 */
51 #define SPRN_SPRG3R 0x103 /* Special Purpose Register General 3 Read */
52 #define SPRN_SPRG4R 0x104 /* Special Purpose Register General 4 Read */
53 #define SPRN_SPRG5R 0x105 /* Special Purpose Register General 5 Read */
54 #define SPRN_SPRG6R 0x106 /* Special Purpose Register General 6 Read */
55 #define SPRN_SPRG7R 0x10
[all...]
/linux/drivers/gpu/drm/amd/include/
H A Dv12_structs.h28 uint32_t shadow_base_lo; // offset: 0 (0x0)
29 uint32_t shadow_base_hi; // offset: 1 (0x1)
30 uint32_t reserved_2; // offset: 2 (0x2)
31 uint32_t reserved_3; // offset: 3 (0x3)
32 uint32_t fw_work_area_base_lo; // offset: 4 (0x4)
33 uint32_t fw_work_area_base_hi; // offset: 5 (0x5)
34 uint32_t shadow_initialized; // offset: 6 (0x6)
35 uint32_t ib_vmid; // offset: 7 (0x7)
36 uint32_t reserved_8; // offset: 8 (0x
[all...]
H A Dv11_structs.h28 uint32_t shadow_base_lo; // offset: 0 (0x0)
29 uint32_t shadow_base_hi; // offset: 1 (0x1)
30 uint32_t gds_bkup_base_lo; // offset: 2 (0x2)
31 uint32_t gds_bkup_base_hi; // offset: 3 (0x3)
32 uint32_t fw_work_area_base_lo; // offset: 4 (0x4)
33 uint32_t fw_work_area_base_hi; // offset: 5 (0x5)
34 uint32_t shadow_initialized; // offset: 6 (0x6)
35 uint32_t ib_vmid; // offset: 7 (0x7)
36 uint32_t reserved_8; // offset: 8 (0x
[all...]
/linux/drivers/power/supply/
H A Dbd99954-charger.h13 #define BD99954_ID 0x346
14 #define BD99955_ID 0x221
15 #define BD99956_ID 0x331
18 #define CHARGING_CURRENT 0x14
19 #define CHARGING_VOLTAGE 0x15
20 #define PROTECT_SET 0x3E
21 #define MAP_SET 0x3F
24 #define CHGSTM_STATUS 0x100
25 #define VBAT_VSYS_STATUS 0x101
26 #define VBUS_VCC_STATUS 0x10
[all...]

123