Home
last modified time | relevance | path

Searched +full:0 +full:x1294 (Results 1 – 25 of 28) sorted by relevance

12

/linux/Documentation/devicetree/bindings/gpu/
H A Dsamsung-scaler.yaml88 reg = <0x12800000 0x1294>;
/linux/arch/arm/boot/dts/samsung/
H A Dexynos5420.dtsi153 cluster_a15_opp_table: opp-table-0 {
270 reg = <0x10d20000 0x1000>;
271 ranges = <0x0 0x10d20000 0x6000>;
276 reg = <0x4000 0x1000>;
281 reg = <0x5000 0x100
[all...]
/linux/drivers/clk/stm32/
H A Dstm32mp25_rcc.h10 #define RCC_SECCFGR0 0x0
11 #define RCC_SECCFGR1 0x4
12 #define RCC_SECCFGR2 0x8
13 #define RCC_SECCFGR3 0xC
14 #define RCC_PRIVCFGR0 0x10
15 #define RCC_PRIVCFGR1 0x14
16 #define RCC_PRIVCFGR2 0x18
17 #define RCC_PRIVCFGR3 0x1C
18 #define RCC_RCFGLOCKR0 0x20
19 #define RCC_RCFGLOCKR1 0x2
[all...]
/linux/arch/arm64/boot/dts/exynos/
H A Dexynos5433.dtsi48 #clock-cells = <0>;
53 #size-cells = <0>;
91 reg = <0x100>;
96 i-cache-size = <0x8000>;
99 d-cache-size = <0x8000>;
109 reg = <0x101>;
112 i-cache-size = <0x8000>;
115 d-cache-size = <0x8000>;
125 reg = <0x102>;
128 i-cache-size = <0x800
[all...]
/linux/drivers/net/ethernet/renesas/
H A Drswitch.h18 for (i = 0; i < RSWITCH_NUM_PORTS; i++) \
24 for (; i-- > 0; ) \
45 #define RSWITCH_TOP_OFFSET 0x00008000
46 #define RSWITCH_COMA_OFFSET 0x00009000
47 #define RSWITCH_ETHA_OFFSET 0x0000a000 /* with RMAC */
48 #define RSWITCH_ETHA_SIZE 0x00002000 /* with RMAC */
49 #define RSWITCH_GWCA0_OFFSET 0x00010000
50 #define RSWITCH_GWCA1_OFFSET 0x00012000
56 #define GWCA_INDEX 0
58 #define GWCA_IPV_NUM 0
[all...]
/linux/drivers/net/ethernet/microchip/
H A Dlan743x_main.h16 #define ID_REV (0x00)
17 #define ID_REV_ID_MASK_ (0xFFFF0000)
18 #define ID_REV_ID_LAN7430_ (0x74300000)
19 #define ID_REV_ID_LAN7431_ (0x74310000)
20 #define ID_REV_ID_LAN743X_ (0x74300000)
21 #define ID_REV_ID_A011_ (0xA0110000) // PCI11010
22 #define ID_REV_ID_A041_ (0xA0410000) // PCI11414
23 #define ID_REV_ID_A0X1_ (0xA0010000)
25 ((((id_rev) & 0xFFF00000) == ID_REV_ID_LAN743X_) || \
26 (((id_rev) & 0xFF0F000
[all...]
/linux/drivers/gpu/drm/amd/include/asic_reg/dpcs/
H A Ddpcs_3_1_4_offset.h31 // base address: 0x0
32 #define ixDPCSSYS_CR0_SUP_DIG_IDCODE_LO 0x0000
33 #define ixDPCSSYS_CR0_SUP_DIG_IDCODE_HI 0x0001
34 #define ixDPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN 0x0002
35 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN 0x0003
36 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN 0x0004
37 #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN 0x0005
38 #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN 0x0006
39 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0 0x0007
40 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_1 0x000
[all...]
H A Ddpcs_4_2_0_offset.h27 // base address: 0x0
28 #define regDPCSSYS_CR0_DPCSSYS_CR_ADDR 0x2934
30 #define regDPCSSYS_CR0_DPCSSYS_CR_DATA 0x2935
35 // base address: 0x360
36 #define regDPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c
38 #define regDPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d
43 // base address: 0x6c0
44 #define regDPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae4
46 #define regDPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae5
51 // base address: 0xa2
[all...]
H A Ddpcs_4_2_2_offset.h14 // base address: 0x0
15 #define regDPCSSYS_CR0_DPCSSYS_CR_ADDR 0x2934
17 #define regDPCSSYS_CR0_DPCSSYS_CR_DATA 0x2935
22 // base address: 0x360
23 #define regDPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c
25 #define regDPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d
30 // base address: 0x6c0
31 #define regDPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae4
33 #define regDPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae5
38 // base address: 0xa2
[all...]
H A Ddpcs_4_2_3_offset.h31 // base address: 0x0
32 #define regDPCSSYS_CR0_DPCSSYS_CR_ADDR 0x2934
34 #define regDPCSSYS_CR0_DPCSSYS_CR_DATA 0x2935
39 // base address: 0x360
40 #define regDPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c
42 #define regDPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d
47 // base address: 0x6c0
48 #define regDPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae4
50 #define regDPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae5
55 // base address: 0xa2
[all...]
/linux/sound/soc/mediatek/mt8195/
H A Dmt8195-reg.h13 #define AFE_SRAM_BASE (0x10880000)
14 #define AFE_SRAM_SIZE (0x10000)
16 #define AUDIO_TOP_CON0 (0x0000)
17 #define AUDIO_TOP_CON1 (0x0004)
18 #define AUDIO_TOP_CON2 (0x0008)
19 #define AUDIO_TOP_CON3 (0x000c)
20 #define AUDIO_TOP_CON4 (0x0010)
21 #define AUDIO_TOP_CON5 (0x0014)
22 #define AUDIO_TOP_CON6 (0x0018)
23 #define AFE_MAS_HADDR_MSB (0x002
[all...]
/linux/sound/soc/mediatek/mt8188/
H A Dmt8188-reg.h14 #define AUDIO_TOP_CON0 (0x0000)
15 #define AUDIO_TOP_CON1 (0x0004)
16 #define AUDIO_TOP_CON2 (0x0008)
17 #define AUDIO_TOP_CON3 (0x000c)
18 #define AUDIO_TOP_CON4 (0x0010)
19 #define AUDIO_TOP_CON5 (0x0014)
20 #define AUDIO_TOP_CON6 (0x0018)
21 #define AFE_MAS_HADDR_MSB (0x0020)
22 #define AFE_MEMIF_ONE_HEART (0x0024)
23 #define AFE_MUX_SEL_CFG (0x004
[all...]
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_1_offset.h27 // base address: 0x0
28 #define mmPHYPLLA_PIXCLK_RESYNC_CNTL 0x0040
30 #define mmPHYPLLB_PIXCLK_RESYNC_CNTL 0x0041
32 #define mmDP_DTO_DBUF_EN 0x0044
34 #define mmDPREFCLK_CGTT_BLK_CTRL_REG 0x0048
36 #define mmREFCLK_CNTL 0x0049
38 #define mmREFCLK_CGTT_BLK_CTRL_REG 0x004b
40 #define mmDCCG_PERFMON_CNTL2 0x004e
42 #define mmDCCG_DS_DTO_INCR 0x0053
44 #define mmDCCG_DS_DTO_MODULO 0x005
[all...]
H A Ddcn_2_1_0_offset.h27 // base address: 0x48
28 #define mmVGA_MEM_WRITE_PAGE_ADDR 0x0000
29 #define mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
30 #define mmVGA_MEM_READ_PAGE_ADDR 0x0001
31 #define mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
35 // base address: 0x3b4
36 #define mmCRTC8_IDX 0x002d
38 #define mmCRTC8_DATA 0x002d
40 #define mmGENFC_WT 0x002e
42 #define mmGENS1 0x002
[all...]
H A Ddcn_3_0_2_offset.h27 // base address: 0x0
28 #define mmVGA_MEM_WRITE_PAGE_ADDR 0x0000
29 #define mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
30 #define mmVGA_MEM_READ_PAGE_ADDR 0x0001
31 #define mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
32 #define mmVGA_RENDER_CONTROL 0x0000
34 #define mmVGA_SEQUENCER_RESET_CONTROL 0x0001
36 #define mmVGA_MODE_CONTROL 0x0002
38 #define mmVGA_SURFACE_PITCH_SELECT 0x0003
40 #define mmVGA_MEMORY_BASE_ADDRESS 0x000
[all...]
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_2_offset.h29 // base address: 0x0
30 #define ixDIDT_SQ_CTRL0 0x0000
31 #define ixDIDT_SQ_CTRL2 0x0002
32 #define ixDIDT_SQ_STALL_CTRL 0x0004
33 #define ixDIDT_SQ_TUNING_CTRL 0x0005
34 #define ixDIDT_SQ_STALL_AUTO_RELEASE_CTRL 0x0006
35 #define ixDIDT_SQ_CTRL3 0x0007
36 #define ixDIDT_SQ_STALL_PATTERN_1_2 0x0008
37 #define ixDIDT_SQ_STALL_PATTERN_3_4 0x0009
38 #define ixDIDT_SQ_STALL_PATTERN_5_6 0x000
[all...]
H A Dgc_9_1_offset.h24 #define mmSQ_DEBUG_STS_GLOBAL 0x0309
25 #define mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0
26 #define mmSQ_DEBUG_STS_GLOBAL2 0x0310
27 #define mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0
28 #define mmSQ_DEBUG_STS_GLOBAL3 0x0311
29 #define mmSQ_DEBUG_STS_GLOBAL3_BASE_IDX 0
32 // base address: 0x8000
33 #define mmGRBM_CNTL 0x0000
34 #define mmGRBM_CNTL_BASE_IDX 0
35 #define mmGRBM_SKEW_CNTL 0x000
[all...]
H A Dgc_9_2_1_offset.h24 #define mmSQ_DEBUG_STS_GLOBAL 0x0309
25 #define mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0
26 #define mmSQ_DEBUG_STS_GLOBAL2 0x0310
27 #define mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0
28 #define mmSQ_DEBUG_STS_GLOBAL3 0x0311
29 #define mmSQ_DEBUG_STS_GLOBAL3_BASE_IDX 0
32 // base address: 0x8000
33 #define mmGRBM_CNTL 0x0000
34 #define mmGRBM_CNTL_BASE_IDX 0
35 #define mmGRBM_SKEW_CNTL 0x000
[all...]
H A Dgc_9_0_offset.h24 #define mmSQ_DEBUG_STS_GLOBAL 0x0309
25 #define mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0
26 #define mmSQ_DEBUG_STS_GLOBAL2 0x0310
27 #define mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0
28 #define mmSQ_DEBUG_STS_GLOBAL3 0x0311
29 #define mmSQ_DEBUG_STS_GLOBAL3_BASE_IDX 0
32 // base address: 0x8000
33 #define mmGRBM_CNTL 0x0000
34 #define mmGRBM_CNTL_BASE_IDX 0
35 #define mmGRBM_SKEW_CNTL 0x000
[all...]
H A Dgc_10_1_0_offset.h24 #define mmSQ_DEBUG_STS_GLOBAL 0x10A9
25 #define mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0
26 #define mmSQ_DEBUG_STS_GLOBAL2 0x10B0
27 #define mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0
30 // base address: 0x4980
31 #define mmSDMA0_DEC_START 0x0000
32 #define mmSDMA0_DEC_START_BASE_IDX 0
33 #define mmSDMA0_PG_CNTL 0x0016
34 #define mmSDMA0_PG_CNTL_BASE_IDX 0
35 #define mmSDMA0_PG_CTX_LO 0x001
[all...]
H A Dgc_11_0_0_offset.h29 // base address: 0x4980
30 #define regSDMA0_DEC_START 0x0000
31 #define regSDMA0_DEC_START_BASE_IDX 0
32 #define regSDMA0_F32_MISC_CNTL 0x000b
33 #define regSDMA0_F32_MISC_CNTL_BASE_IDX 0
34 #define regSDMA0_GLOBAL_TIMESTAMP_LO 0x000f
35 #define regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX 0
36 #define regSDMA0_GLOBAL_TIMESTAMP_HI 0x0010
37 #define regSDMA0_GLOBAL_TIMESTAMP_HI_BASE_IDX 0
38 #define regSDMA0_POWER_CNTL 0x001
[all...]
H A Dgc_12_0_0_offset.h29 // base address: 0x4980
30 #define regSDMA0_DEC_START 0x0000
31 #define regSDMA0_DEC_START_BASE_IDX 0
32 #define regSDMA0_MCU_MISC_CNTL 0x0001
33 #define regSDMA0_MCU_MISC_CNTL_BASE_IDX 0
34 #define regSDMA0_UCODE_REV 0x0003
35 #define regSDMA0_UCODE_REV_BASE_IDX 0
36 #define regSDMA0_GLOBAL_TIMESTAMP_LO 0x0005
37 #define regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX 0
38 #define regSDMA0_GLOBAL_TIMESTAMP_HI 0x000
[all...]
H A Dgc_11_0_3_offset.h29 // base address: 0x4980
30 #define regSDMA0_DEC_START 0x0000
31 #define regSDMA0_DEC_START_BASE_IDX 0
32 #define regSDMA0_F32_MISC_CNTL 0x000b
33 #define regSDMA0_F32_MISC_CNTL_BASE_IDX 0
34 #define regSDMA0_GLOBAL_TIMESTAMP_LO 0x000f
35 #define regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX 0
36 #define regSDMA0_GLOBAL_TIMESTAMP_HI 0x0010
37 #define regSDMA0_GLOBAL_TIMESTAMP_HI_BASE_IDX 0
38 #define regSDMA0_POWER_CNTL 0x001
[all...]
H A Dgc_10_3_0_offset.h25 #define mmSQ_DEBUG_STS_GLOBAL 0x10A9
26 #define mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0
27 #define mmSQ_DEBUG_STS_GLOBAL2 0x10B0
28 #define mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0
29 #define mmSQ_DEBUG 0x10B1
30 #define mmSQ_DEBUG_BASE_IDX 0
33 // base address: 0x4980
34 #define mmSDMA0_DEC_START 0x0000
35 #define mmSDMA0_DEC_START_BASE_IDX 0
36 #define mmSDMA0_GLOBAL_TIMESTAMP_LO 0x000
[all...]
/linux/sound/hda/codecs/realtek/
H A Dalc269.c52 static const hda_nid_t alc269_ignore[] = { 0x1d, 0 }; in alc269_parse_auto_config()
53 static const hda_nid_t alc269_ssids[] = { 0, 0x1b, 0x14, 0x21 }; in alc269_parse_auto_config()
54 static const hda_nid_t alc269va_ssids[] = { 0x15, 0x1b, 0x14, 0 }; in alc269_parse_auto_config()
[all...]

12