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/linux/Documentation/devicetree/bindings/media/
H A Dstih407-c8sectpfe.txt30 - pinctrl-0 : phandle referencing pin configuration for this tsin configuration
36 - tsin-num : tsin id of the InputBlock (must be between 0 to 6)
55 reg = <0x08a20000 0x10000>, <0x08a00000 0x4000>;
59 pinctrl-0 = <&pinctrl_tsin0_serial>;
73 tsin0: port@0 {
74 tsin-num = <0>;
[all...]
/linux/arch/arm/boot/dts/st/
H A Dstihxxx-b2120.dtsi28 #size-cells = <0>;
30 simple-audio-card,dai-link@0 {
31 reg = <0>;
69 sound-dai = <&sti_sasg_codec 0>;
101 st,i2c-min-scl-pulse-width-us = <0>;
108 st,i2c-min-scl-pulse-width-us = <0>;
138 st,i2c-min-scl-pulse-width-us = <0>;
150 fixed-link = <0 1 1000 0 0>;
[all...]
/linux/Documentation/devicetree/bindings/remoteproc/
H A Dqcom,sc7280-wpss-pil.yaml166 reg = <0x08a00000 0x10000>;
169 <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
192 qcom,smem-states = <&wpss_smp2p_out 0>;
199 qcom,halt-regs = <&tcsr_mutex 0x37000>;
/linux/arch/arm64/boot/dts/qcom/
H A Dipq5018.dtsi21 #clock-cells = <0>;
26 #clock-cells = <0>;
32 #size-cells = <0>;
34 cpu0: cpu@0 {
37 reg = <0x0>;
47 reg = <0x1>;
57 cache-size = <0x80000>;
82 qcom,dload-mode = <&tcsr 0x6100>;
90 reg = <0x0 0x4000000
[all...]
H A Dipq5424.dtsi23 #clock-cells = <0>;
28 #clock-cells = <0>;
34 #size-cells = <0>;
36 cpu0: cpu@0 {
39 reg = <0x0>;
60 reg = <0x100>;
75 reg = <0x200>;
90 reg = <0x300>;
105 qcom,dload-mode = <&tcsr 0x25100>;
112 reg = <0x
[all...]
H A Dipq6018.dtsi23 #clock-cells = <0>;
29 #clock-cells = <0>;
35 #size-cells = <0>;
37 cpu0: cpu@0 {
40 reg = <0x0>;
53 reg = <0x1>;
65 reg = <0x2>;
77 reg = <0x3>;
95 qcom,dload-mode = <&tcsr 0x6100>;
107 opp-supported-hw = <0x
[all...]
H A Dsc7280.dtsi83 #clock-cells = <0>;
89 #clock-cells = <0>;
100 reg = <0x0 0x004cd000 0x0 0x1000>;
104 reg = <0x0 0x80000000 0x0 0x60000
[all...]
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_default.h26 #define mmSDMA0_DEC_START_DEFAULT 0x00000000
27 #define mmSDMA0_PG_CNTL_DEFAULT 0x00000000
28 #define mmSDMA0_PG_CTX_LO_DEFAULT 0x00000000
29 #define mmSDMA0_PG_CTX_HI_DEFAULT 0x00000000
30 #define mmSDMA0_PG_CTX_CNTL_DEFAULT 0x00000000
31 #define mmSDMA0_POWER_CNTL_DEFAULT 0x40000050
32 #define mmSDMA0_CLK_CTRL_DEFAULT 0x00000100
33 #define mmSDMA0_CNTL_DEFAULT 0x000000c2
34 #define mmSDMA0_CHICKEN_BITS_DEFAULT 0x01af0107
35 #define mmSDMA0_GB_ADDR_CONFIG_DEFAULT 0x0000004
[all...]
H A Dgc_10_3_0_default.h27 #define mmSDMA0_DEC_START_DEFAULT 0x00000000
28 #define mmSDMA0_GLOBAL_TIMESTAMP_LO_DEFAULT 0x00000000
29 #define mmSDMA0_GLOBAL_TIMESTAMP_HI_DEFAULT 0x00000000
30 #define mmSDMA0_PG_CNTL_DEFAULT 0x00000000
31 #define mmSDMA0_PG_CTX_LO_DEFAULT 0x00000000
32 #define mmSDMA0_PG_CTX_HI_DEFAULT 0x00000000
33 #define mmSDMA0_PG_CTX_CNTL_DEFAULT 0x00000000
34 #define mmSDMA0_POWER_CNTL_DEFAULT 0x40000050
35 #define mmSDMA0_CLK_CTRL_DEFAULT 0x00000100
36 #define mmSDMA0_CNTL_DEFAULT 0x000000c
[all...]