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/linux/drivers/usb/serial/ !
H A Dipaq.c37 { USB_DEVICE(0x0104, 0x00BE) }, /* Socket USB Sync */
38 { USB_DEVICE(0x03F0, 0x1016) }, /* HP USB Sync */
39 { USB_DEVICE(0x03F0, 0x1116) }, /* HP USB Sync 1611 */
40 { USB_DEVICE(0x03F0, 0x1216) }, /* HP USB Sync 1612 */
41 { USB_DEVICE(0x03F0, 0x2016) }, /* HP USB Sync 1620 */
42 { USB_DEVICE(0x03F0, 0x2116) }, /* HP USB Sync 1621 */
43 { USB_DEVICE(0x03F0, 0x2216) }, /* HP USB Sync 1622 */
44 { USB_DEVICE(0x03F0, 0x3016) }, /* HP USB Sync 1630 */
45 { USB_DEVICE(0x03F0, 0x3116) }, /* HP USB Sync 1631 */
46 { USB_DEVICE(0x03F0, 0x3216) }, /* HP USB Sync 1632 */
[all …]
/linux/Documentation/devicetree/bindings/misc/ !
H A Dqcom,fastrpc.yaml65 const: 0
68 "(compute-)?cb@[0-9]*$":
127 #size-cells = <0>;
132 iommus = <&apps_smmu 0x0541 0x0>;
138 iommus = <&apps_smmu 0x0542 0x0>;
144 iommus = <&apps_smmu 0x0543 0x0>;
/linux/sound/soc/codecs/ !
H A Drt1015.h17 #define RT1015_DEVICE_ID_VAL 0x1011
18 #define RT1015_DEVICE_ID_VAL2 0x1015
20 #define RT1015_RESET 0x0000
21 #define RT1015_CLK2 0x0004
22 #define RT1015_CLK3 0x0006
23 #define RT1015_PLL1 0x000a
24 #define RT1015_PLL2 0x000c
25 #define RT1015_DUM_RW1 0x000e
26 #define RT1015_DUM_RW2 0x0010
27 #define RT1015_DUM_RW3 0x0012
[all …]
H A Drt1011.h11 #define RT1011_DEVICE_ID_NUM 0x1011
13 #define RT1011_RESET 0x0000
14 #define RT1011_CLK_1 0x0002
15 #define RT1011_CLK_2 0x0004
16 #define RT1011_CLK_3 0x0006
17 #define RT1011_CLK_4 0x0008
18 #define RT1011_PLL_1 0x000a
19 #define RT1011_PLL_2 0x000c
20 #define RT1011_SRC_1 0x000e
21 #define RT1011_SRC_2 0x0010
[all …]
H A Drt1015.c39 { 0x0000, 0x0000 },
40 { 0x0004, 0xa000 },
41 { 0x0006, 0x0003 },
42 { 0x000a, 0x081e },
43 { 0x000c, 0x0006 },
44 { 0x000e, 0x0000 },
45 { 0x0010, 0x0000 },
46 { 0x0012, 0x0000 },
47 { 0x0014, 0x0000 },
48 { 0x0016, 0x0000 },
[all …]
H A Dwm5100-tables.c815 { 0x0000, 0x0000 }, /* R0 - software reset */
816 { 0x0001, 0x0000 }, /* R1 - Device Revision */
817 { 0x0010, 0x0801 }, /* R16 - Ctrl IF 1 */
818 { 0x0020, 0x0000 }, /* R32 - Tone Generator 1 */
819 { 0x0030, 0x0000 }, /* R48 - PWM Drive 1 */
820 { 0x0031, 0x0100 }, /* R49 - PWM Drive 2 */
821 { 0x0032, 0x0100 }, /* R50 - PWM Drive 3 */
822 { 0x0100, 0x0002 }, /* R256 - Clocking 1 */
823 { 0x0101, 0x0000 }, /* R257 - Clocking 3 */
824 { 0x0102, 0x0011 }, /* R258 - Clocking 4 */
[all …]
H A Drt1011.c37 { RT1011_POWER_9, 0xa840 },
39 { RT1011_ADC_SET_5, 0x0a20 },
40 { RT1011_DAC_SET_2, 0xa032 },
42 { RT1011_SPK_PRO_DC_DET_1, 0xb00c },
43 { RT1011_SPK_PRO_DC_DET_2, 0xcccc },
45 { RT1011_A_TIMING_1, 0x6054 },
47 { RT1011_POWER_7, 0x3e55 },
48 { RT1011_POWER_8, 0x0520 },
49 { RT1011_BOOST_CON_1, 0xe188 },
50 { RT1011_POWER_4, 0x16f2 },
[all …]
/linux/include/linux/bcma/ !
H A Dbcma.h62 #define BCMA_MANUF_ARM 0x43B
63 #define BCMA_MANUF_MIPS 0x4A7
64 #define BCMA_MANUF_BCM 0x4BF
67 #define BCMA_CL_SIM 0x0
68 #define BCMA_CL_EROM 0x1
69 #define BCMA_CL_CORESIGHT 0x9
70 #define BCMA_CL_VERIF 0xB
71 #define BCMA_CL_OPTIMO 0xD
72 #define BCMA_CL_GEN 0xE
73 #define BCMA_CL_PRIMECELL 0xF
[all …]
/linux/drivers/net/wireless/realtek/rtl818x/rtl8187/ !
H A Drtl8225.c28 usb_control_msg(priv->udev, usb_rcvctrlpipe(priv->udev, 0), in rtl818x_ioread8_idx()
30 (unsigned long)addr, idx & 0x03, in rtl818x_ioread8_idx()
45 usb_control_msg(priv->udev, usb_rcvctrlpipe(priv->udev, 0), in rtl818x_ioread16_idx()
47 (unsigned long)addr, idx & 0x03, in rtl818x_ioread16_idx()
62 usb_control_msg(priv->udev, usb_rcvctrlpipe(priv->udev, 0), in rtl818x_ioread32_idx()
64 (unsigned long)addr, idx & 0x03, in rtl818x_ioread32_idx()
79 usb_control_msg(priv->udev, usb_sndctrlpipe(priv->udev, 0), in rtl818x_iowrite8_idx()
81 (unsigned long)addr, idx & 0x03, in rtl818x_iowrite8_idx()
93 usb_control_msg(priv->udev, usb_sndctrlpipe(priv->udev, 0), in rtl818x_iowrite16_idx()
95 (unsigned long)addr, idx & 0x03, in rtl818x_iowrite16_idx()
[all …]
/linux/drivers/mfd/ !
H A Dwm8994-regmap.c18 { 0x0001, 0x0000 }, /* R1 - Power Management (1) */
19 { 0x0002, 0x6000 }, /* R2 - Power Management (2) */
20 { 0x0003, 0x0000 }, /* R3 - Power Management (3) */
21 { 0x0004, 0x0000 }, /* R4 - Power Management (4) */
22 { 0x0005, 0x0000 }, /* R5 - Power Management (5) */
23 { 0x0006, 0x0000 }, /* R6 - Power Management (6) */
24 { 0x0015, 0x0000 }, /* R21 - Input Mixer (1) */
25 { 0x0018, 0x008B }, /* R24 - Left Line Input 1&2 Volume */
26 { 0x0019, 0x008B }, /* R25 - Left Line Input 3&4 Volume */
27 { 0x001A, 0x008B }, /* R26 - Right Line Input 1&2 Volume */
[all …]
/linux/drivers/net/wan/ !
H A Dfarsync.c82 module_param(fst_txq_low, int, 0);
83 module_param(fst_txq_high, int, 0);
84 module_param(fst_max_reads, int, 0);
85 module_param(fst_excluded_cards, int, 0);
86 module_param_array(fst_excluded_list, int, NULL, 0);
105 #define FST_MEMSIZE 0x100000 /* Size of card memory (1Mb) */
107 #define SMC_BASE 0x00002000L /* Base offset of the shared memory window main
110 #define BFM_BASE 0x00010000L /* Base offset of the shared memory window DMA
159 /* #define cnv_bcnt(len) (( ~(len) + 1 ) & 0x7FFF ) */
166 #define DMA_OWN 0x80 /* SmartDMA owns the descriptor */
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/ !
H A Dvcn_4_0_0_offset.h29 // base address: 0x1fb00
30 …UVD_TOP_CTRL 0x00c0
32 …UVD_CGC_GATE 0x00c1
34 …UVD_CGC_CTRL 0x00c2
36 …AVM_SUVD_CGC_GATE 0x00c4
38 …CDEFE_SUVD_CGC_GATE 0x00c4
40 …EFC_SUVD_CGC_GATE 0x00c4
42 …ENT_SUVD_CGC_GATE 0x00c4
44 …IME_SUVD_CGC_GATE 0x00c4
46 …PPU_SUVD_CGC_GATE 0x00c4
[all …]
H A Dvcn_4_0_3_offset.h29 // base address: 0x1fb00
30 …UVD_TOP_CTRL 0x00c0
32 …UVD_CGC_GATE 0x00c1
34 …UVD_CGC_CTRL 0x00c2
36 …AVM_SUVD_CGC_GATE 0x00c4
38 …CDEFE_SUVD_CGC_GATE 0x00c4
40 …EFC_SUVD_CGC_GATE 0x00c4
42 …ENT_SUVD_CGC_GATE 0x00c4
44 …IME_SUVD_CGC_GATE 0x00c4
46 …PPU_SUVD_CGC_GATE 0x00c4
[all …]
/linux/drivers/net/wireless/realtek/rtl818x/rtl8180/ !
H A Drtl8225.c29 bangdata = (data << 4) | (addr & 0xf); in rtl8225_write()
31 reg80 = rtl818x_ioread16(priv, &priv->map->RFPinsOutput) & 0xfff3; in rtl8225_write()
34 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, reg82 | 0x7); in rtl8225_write()
37 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, reg84 | 0x7 | 0x400); in rtl8225_write()
48 for (i = 15; i >= 0; i--) { in rtl8225_write()
69 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, reg84 | 0x400); in rtl8225_write()
70 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1FFF); in rtl8225_write()
81 reg84 = rtl818x_ioread16(priv, &priv->map->RFPinsSelect) | 0x400; in rtl8225_read()
83 reg80 &= ~0xF; in rtl8225_read()
85 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, reg82 | 0x000F); in rtl8225_read()
[all …]
/linux/sound/hda/codecs/ !
H A Dconexant.c52 HDA_CODEC_VOLUME_MONO("Beep Playback Volume", 0, 1, 0, HDA_OUTPUT),
53 HDA_CODEC_MUTE_BEEP_MONO("Beep Playback Switch", 0, 1, 0, HDA_OUTPUT),
64 for (i = 0; i < ARRAY_SIZE(cxt_beep_mixer); i++) { in set_beep_amp()
71 return 0; in set_beep_amp()
81 return set_beep_amp(spec, nid, 0, HDA_OUTPUT); in cx_auto_parse_beep()
82 return 0; in cx_auto_parse_beep()
85 #define cx_auto_parse_beep(codec) 0
122 for (i = 0; i < num_pins; i++) { in cx_auto_turn_eapd()
124 snd_hda_codec_write(codec, pins[i], 0, in cx_auto_turn_eapd()
126 on ? 0x02 : 0); in cx_auto_turn_eapd()
[all …]
/linux/fs/smb/client/ !
H A Dwinucase.c23 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
24 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
25 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
26 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
27 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
28 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
29 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
30 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
31 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
32 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
[all …]
/linux/arch/arm64/boot/dts/qcom/ !
H A Dsm8350.dtsi40 #clock-cells = <0>;
48 #clock-cells = <0>;
54 #size-cells = <0>;
56 cpu0: cpu@0 {
59 reg = <0x0 0x0>;
60 clocks = <&cpufreq_hw 0>;
63 qcom,freq-domain = <&cpufreq_hw 0>;
83 reg = <0x0 0x100>;
84 clocks = <&cpufreq_hw 0>;
87 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/ !
H A Ddcn_3_2_1_offset.h27 // base address: 0x0
28 …DENTIST_DISPCLK_CNTL 0x0064
33 // base address: 0x0
34 …PHYPLLA_PIXCLK_RESYNC_CNTL 0x0040
36 …PHYPLLB_PIXCLK_RESYNC_CNTL 0x0041
38 …PHYPLLC_PIXCLK_RESYNC_CNTL 0x0042
40 …PHYPLLD_PIXCLK_RESYNC_CNTL 0x0043
42 …DP_DTO_DBUF_EN 0x0044
44 …DSCCLK3_DTO_PARAM 0x0045
46 …DPREFCLK_CGTT_BLK_CTRL_REG 0x0048
[all …]
H A Ddcn_4_1_0_offset.h11 // base address: 0x0
12 …DENTIST_DISPCLK_CNTL 0x0064
17 // base address: 0x0
18 …PHYPLLA_PIXCLK_RESYNC_CNTL 0x0040
20 …PHYPLLB_PIXCLK_RESYNC_CNTL 0x0041
22 …PHYPLLC_PIXCLK_RESYNC_CNTL 0x0042
24 …PHYPLLD_PIXCLK_RESYNC_CNTL 0x0043
26 …DP_DTO_DBUF_EN 0x0044
28 …DSCCLK3_DTO_PARAM 0x0045
30 …DSCCLK4_DTO_PARAM 0x0046
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/ !
H A Dgc_9_4_2_offset.h29 // base address: 0x0
30 …DIDT_SQ_CTRL0 0x0000
31 …DIDT_SQ_CTRL2 0x0002
32 …DIDT_SQ_STALL_CTRL 0x0004
33 …DIDT_SQ_TUNING_CTRL 0x0005
34 …DIDT_SQ_STALL_AUTO_RELEASE_CTRL 0x0006
35 …DIDT_SQ_CTRL3 0x0007
36 …DIDT_SQ_STALL_PATTERN_1_2 0x0008
37 …DIDT_SQ_STALL_PATTERN_3_4 0x0009
38 …DIDT_SQ_STALL_PATTERN_5_6 0x000a
[all …]
H A Dgc_9_1_offset.h24 …SQ_DEBUG_STS_GLOBAL 0x0309
25 …ne mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0
26 …SQ_DEBUG_STS_GLOBAL2 0x0310
27 …ne mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0
28 …SQ_DEBUG_STS_GLOBAL3 0x0311
29 …ne mmSQ_DEBUG_STS_GLOBAL3_BASE_IDX 0
32 // base address: 0x8000
33 …GRBM_CNTL 0x0000
34 …ne mmGRBM_CNTL_BASE_IDX 0
35 …GRBM_SKEW_CNTL 0x0001
[all …]
H A Dgc_9_2_1_offset.h24 …SQ_DEBUG_STS_GLOBAL 0x0309
25 …ne mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0
26 …SQ_DEBUG_STS_GLOBAL2 0x0310
27 …ne mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0
28 …SQ_DEBUG_STS_GLOBAL3 0x0311
29 …ne mmSQ_DEBUG_STS_GLOBAL3_BASE_IDX 0
32 // base address: 0x8000
33 …GRBM_CNTL 0x0000
34 …ne mmGRBM_CNTL_BASE_IDX 0
35 …GRBM_SKEW_CNTL 0x0001
[all …]
H A Dgc_9_4_3_offset.h29 // base address: 0x8000
30 …GRBM_CNTL 0x0000
31 …e regGRBM_CNTL_BASE_IDX 0
32 …GRBM_SKEW_CNTL 0x0001
33 …e regGRBM_SKEW_CNTL_BASE_IDX 0
34 …GRBM_STATUS2 0x0002
35 …e regGRBM_STATUS2_BASE_IDX 0
36 …GRBM_PWR_CNTL 0x0003
37 …e regGRBM_PWR_CNTL_BASE_IDX 0
38 …GRBM_STATUS 0x0004
[all …]
H A Dgc_9_0_offset.h24 …SQ_DEBUG_STS_GLOBAL 0x0309
25 …ne mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0
26 …SQ_DEBUG_STS_GLOBAL2 0x0310
27 …ne mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0
28 …SQ_DEBUG_STS_GLOBAL3 0x0311
29 …ne mmSQ_DEBUG_STS_GLOBAL3_BASE_IDX 0
32 // base address: 0x8000
33 …GRBM_CNTL 0x0000
34 …ne mmGRBM_CNTL_BASE_IDX 0
35 …GRBM_SKEW_CNTL 0x0001
[all …]
/linux/drivers/hid/ !
H A Dhid-debug.c40 { 0x00, 0, "Undefined" },
41 { 0x01, 0, "GenericDesktop" },
42 { 0x01, 0x0001, "Pointer" },
43 { 0x01, 0x0002, "Mouse" },
44 { 0x01, 0x0004, "Joystick" },
45 { 0x01, 0x0005, "Gamepad" },
46 { 0x01, 0x0006, "Keyboard" },
47 { 0x01, 0x0007, "Keypad" },
48 { 0x01, 0x0008, "MultiaxisController" },
49 { 0x01, 0x0009, "TabletPCSystemControls" },
[all …]

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