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/linux/arch/mips/include/asm/sn/sn0/
H A Daddrs.h57 #define NASID_BITMASK (0x1ffLL)
62 #define BDDIR_UPPER_MASK (UINT64_CAST 0x7ffff << 10)
63 #define BDECC_UPPER_MASK (UINT64_CAST 0x3ffffff << 3)
70 #define NASID_BITMASK (0xffLL)
76 #define BDDIR_UPPER_MASK (UINT64_CAST 0xfffff << 10)
77 #define BDECC_UPPER_MASK (UINT64_CAST 0x7ffffff << 3)
90 ((widget == 0) ? NODE_BWIN_BASE((nasid), SWIN0_BIGWIN) \
106 #define BWIN_WIDGET_MASK 0x7
150 #define MISC_PROM_BASE PHYS_TO_K0(0x01300000)
151 #define MISC_PROM_SIZE 0x20000
[all...]
/linux/arch/mips/alchemy/
H A Dboard-gpr.c42 alchemy_gpio_direction_output(4, 0); in gpr_reset()
43 alchemy_gpio_direction_output(5, 0); in gpr_reset()
48 alchemy_gpio_direction_output(1, 0); in gpr_reset()
81 [0] = {
91 .id = 0,
99 * 0x00000000-0x00200000 : "kernel"
100 * 0x00200000-0x00a00000 : "rootfs"
101 * 0x01d0000
[all...]
H A Dboard-mtx1.c41 __asm__ __volatile__("jr\t%0" : : "r"(0xbfc00000)); in mtx1_reset()
57 alchemy_gpio_direction_output(204, 0); in board_setup()
64 alchemy_wrsys(~0, AU1000_SYS_TRIOUTCLR); in board_setup()
65 alchemy_gpio_direction_output(0, 0); /* Disable M66EN (PCI 66MHz) */ in board_setup()
68 alchemy_gpio_direction_output(5, 0); /* Disable eth PHY TX_ER */ in board_setup()
72 alchemy_gpio_direction_output(212, 0); /* red off */ in board_setup()
105 .dev_id = "mtx1-wdt.0",
115 .id = 0,
[all...]
/linux/arch/arm/mach-davinci/
H A Dhardware.h23 #define IO_PHYS UL(0x01c00000)
24 #define IO_OFFSET 0xfd000000 /* Virtual IO = 0xfec00000 */
25 #define IO_SIZE 0x00400000
H A Ddevices-da8xx.c27 #define DA8XX_TPCC_BASE 0x01c00000
28 #define DA8XX_TPTC0_BASE 0x01c08000
29 #define DA8XX_TPTC1_BASE 0x01c08400
30 #define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */
31 #define DA8XX_I2C0_BASE 0x01c22000
32 #define DA8XX_RTC_BASE 0x01c23000
33 #define DA8XX_PRUSS_MEM_BASE 0x01c30000
34 #define DA8XX_MMCSD0_BASE 0x01c40000
35 #define DA8XX_SPI0_BASE 0x01c4100
[all...]
/linux/Documentation/devicetree/bindings/mfd/
H A Dsyscon-common.yaml69 reg = <0x01c00000 0x1000>;
/linux/Documentation/devicetree/bindings/media/
H A Dallwinner,sun50i-h6-vpu-g2.yaml60 reg = <0x01c00000 0x1000>;
/linux/arch/mips/include/asm/mach-rc32434/
H A Ddma.h17 #define DMA0_BASE_ADDR 0x18040000
31 #define DMA_DESC_COUNT_BIT 0
32 #define DMA_DESC_COUNT_MSK 0x0003ffff
34 #define DMA_DESC_DS_MSK 0x00300000
37 #define DMA_DESC_DEV_CMD_MSK 0x01c00000
40 #define DMA_DESC_DEV_CMD_BYTE 0
71 #define DMA_CHAN_RUN_BIT (1 << 0)
74 #define DMA_CHAN_MODE_MSK 0x0000000c
75 #define DMA_CHAN_MODE_AUTO 0
[all...]
/linux/drivers/gpu/drm/mcde/
H A Dmcde_drm.h13 #define MCDE_CR 0x00000000
14 #define MCDE_CR_IFIFOEMPTYLINECOUNT_V422_SHIFT 0
15 #define MCDE_CR_IFIFOEMPTYLINECOUNT_V422_MASK 0x0000003F
22 #define MCDE_CONF0 0x00000004
23 #define MCDE_CONF0_SYNCMUX0 BIT(0)
32 #define MCDE_CONF0_IFIFOCTRLWTRMRKLVL_MASK 0x00007000
34 #define MCDE_CONF0_OUTMUX0_MASK 0x00070000
36 #define MCDE_CONF0_OUTMUX1_MASK 0x00380000
38 #define MCDE_CONF0_OUTMUX2_MASK 0x01C00000
[all...]
/linux/Documentation/devicetree/bindings/pci/
H A Dqcom,pcie-sc8180x.yaml89 reg = <0 0x01c00000 0 0x3000>,
90 <0 0x60000000 0 0xf1d>,
91 <0
[all...]
H A Dqcom,pcie-sm8350.yaml94 reg = <0 0x01c00000 0 0x3000>,
95 <0 0x60000000 0 0xf1d>,
96 <0
[all...]
H A Dqcom,pcie-sm8150.yaml95 reg = <0 0x01c00000 0 0x3000>,
96 <0 0x60000000 0 0xf1d>,
97 <0
[all...]
H A Dqcom,pcie-sa8775p.yaml101 reg = <0x0 0x01c00000 0x0 0x3000>,
102 <0x0 0x40000000 0x0 0xf20>,
103 <0x
[all...]
H A Dqcom,pcie-sm8450.yaml99 reg = <0 0x01c00000 0 0x3000>,
100 <0 0x60000000 0 0xf1d>,
101 <0
[all...]
H A Dqcom,pcie-sm8550.yaml103 reg = <0 0x01c00000 0 0x3000>,
104 <0 0x60000000 0 0xf1d>,
105 <0
[all...]
H A Dqcom,pcie-sm8250.yaml104 reg = <0 0x01c00000 0 0x3000>,
105 <0 0x60000000 0 0xf1d>,
106 <0
[all...]
H A Dqcom,pcie-ep.yaml295 reg = <0x01c00000 0x3000>,
296 <0x40000000 0xf1d>,
297 <0x40000f20 0xc8>,
298 <0x40001000 0x1000>,
299 <0x4000200
[all...]
/linux/Documentation/devicetree/bindings/sram/
H A Dallwinner,sun4i-a10-system-control.yaml62 "^regulators@[0-9a-f]+$":
121 reg = <0x01c00000 0x30>;
126 sram_a: sram@0 {
128 reg = <0x00000000 0xc000>;
131 ranges = <0 0x00000000 0xc00
[all...]
/linux/arch/powerpc/boot/dts/fsl/
H A Dmpc8569mds.dts30 reg = <0x0 0xe0005000 0x0 0x1000>;
32 ranges = <0x0 0x0 0x0 0xfe000000 0x02000000
33 0x
[all...]
/linux/arch/mips/include/asm/mach-loongson64/
H A Dloongson.h62 for (x = 0; x < 100000; x++) \
75 #define LOONGSON_FLASH_BASE 0x1c000000
76 #define LOONGSON_FLASH_SIZE 0x02000000 /* 32M */
79 #define LOONGSON_LIO0_BASE 0x1e000000
80 #define LOONGSON_LIO0_SIZE 0x01C00000 /* 28M */
83 #define LOONGSON_BOOT_BASE 0x1fc00000
84 #define LOONGSON_BOOT_SIZE 0x00100000 /* 1M */
86 #define LOONGSON_REG_BASE 0x1fe00000
87 #define LOONGSON_REG_SIZE 0x0010000
[all...]
/linux/arch/arm/boot/dts/renesas/
H A Dr7s72100-rskrza1.dts29 reg = <0x08000000 0x02000000>;
34 reg = <0x18000000 0x08000000>;
47 partition@0 {
49 reg = <0x00000000 0x00080000>;
54 reg = <0x00080000 0x00040000>;
59 reg = <0x000c000
[all...]
/linux/arch/arm64/boot/dts/allwinner/
H A Dsun50i-h5.dtsi11 #size-cells = <0>;
13 cpu0: cpu@0 {
16 reg = <0>;
80 reg = <0x01c00000 0x1000>;
87 reg = <0x00018000 0x1c000>;
90 ranges = <0 0x0001800
[all...]
/linux/arch/mips/include/asm/mach-loongson2ef/
H A Dloongson.h60 for (x = 0; x < 100000; x++) \
69 #define LOONGSON_FLASH_BASE 0x1c000000
70 #define LOONGSON_FLASH_SIZE 0x02000000 /* 32M */
73 #define LOONGSON_LIO0_BASE 0x1e000000
74 #define LOONGSON_LIO0_SIZE 0x01C00000 /* 28M */
77 #define LOONGSON_BOOT_BASE 0x1fc00000
78 #define LOONGSON_BOOT_SIZE 0x00100000 /* 1M */
80 #define LOONGSON_REG_BASE 0x1fe00000
81 #define LOONGSON_REG_SIZE 0x0010000
[all...]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-am68-sk-som.dtsi16 reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
17 <0x00000008 0x80000000 0x00000003 0x80000000>;
26 reg = <0x00 0x9e80000
[all...]
/linux/drivers/net/ethernet/intel/ixgbevf/
H A Ddefines.h8 #define IXGBE_DEV_ID_82599_VF 0x10ED
9 #define IXGBE_DEV_ID_X540_VF 0x1515
10 #define IXGBE_DEV_ID_X550_VF 0x1565
11 #define IXGBE_DEV_ID_X550EM_X_VF 0x15A8
12 #define IXGBE_DEV_ID_X550EM_A_VF 0x15C5
14 #define IXGBE_DEV_ID_82599_VF_HV 0x152E
15 #define IXGBE_DEV_ID_X540_VF_HV 0x1530
16 #define IXGBE_DEV_ID_X550_VF_HV 0x1564
17 #define IXGBE_DEV_ID_X550EM_X_VF_HV 0x15A9
19 #define IXGBE_DEV_ID_E610_VF 0x57A
[all...]

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