Searched +full:0 +full:x010a2000 (Results 1 – 5 of 5) sorted by relevance
43 reg = <0x010a2000 0x1000>,44 <0x010ad000 0x2000>;
26 #define mmGRBM_CNTL_DEFAULT 0x0000001827 #define mmGRBM_SKEW_CNTL_DEFAULT 0x0000002028 #define mmGRBM_STATUS2_DEFAULT 0x0000000029 #define mmGRBM_PWR_CNTL_DEFAULT 0x0000000030 #define mmGRBM_STATUS_DEFAULT 0x0000000031 #define mmGRBM_STATUS_SE0_DEFAULT 0x0000000032 #define mmGRBM_STATUS_SE1_DEFAULT 0x0000000033 #define mmGRBM_SOFT_RESET_DEFAULT 0x0000000034 #define mmGRBM_CGTT_CLK_CNTL_DEFAULT 0x0000010035 #define mmGRBM_GFX_CLKEN_CNTL_DEFAULT 0x00001008[all …]
67 #clock-cells = <0>;73 #clock-cells = <0>;79 #size-cells = <0>;81 cpu0: cpu@0 {84 reg = <0x0 0x0>;85 clocks = <&cpufreq_hw 0>;96 qcom,freq-domain = <&cpufreq_hw 0>;113 reg = <0x0 0x100>;114 clocks = <&cpufreq_hw 0>;125 qcom,freq-domain = <&cpufreq_hw 0>;[all …]
35 #clock-cells = <0>;42 #clock-cells = <0>;50 #size-cells = <0>;52 cpu0: cpu@0 {55 reg = <0x0 0x0>;56 clocks = <&cpufreq_hw 0>;61 qcom,freq-domain = <&cpufreq_hw 0>;63 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,84 reg = <0x0 0x100>;85 clocks = <&cpufreq_hw 0>;[all …]
79 #clock-cells = <0>;86 #clock-cells = <0>;93 #size-cells = <0>;95 cpu0: cpu@0 {98 reg = <0x0 0x0>;99 clocks = <&cpufreq_hw 0>;103 qcom,freq-domain = <&cpufreq_hw 0>;127 reg = <0x0 0x100>;128 clocks = <&cpufreq_hw 0>;132 qcom,freq-domain = <&cpufreq_hw 0>;[all …]