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/linux/arch/arm/boot/dts/nvidia/
H A Dtegra30-asus-tf300t.dts75 reg = <0x10>;
94 mount-matrix = "0", "-1", "0",
95 "-1", "0", "0",
96 "0", "0", "-1";
100 mount-matrix = "-1", "0", "0",
101 "0", "
[all...]
H A Dtegra30-asus-tf300tg.dts22 <TEGRA_GPIO(X, 0) GPIO_ACTIVE_HIGH>,
171 reg = <0x10>;
190 mount-matrix = "1", "0", "0",
191 "0", "-1", "0",
192 "0", "0", "-1";
196 mount-matrix = "-1", "0", "0",
[all...]
H A Dtegra30-asus-tf201.dts67 reg = <0x4d>;
82 mount-matrix = "-1", "0", "0",
83 "0", "-1", "0",
84 "0", "0", "-1";
88 mount-matrix = "0", "-1", "0",
89 "-1", "0", "
[all...]
H A Dtegra30-asus-tf700t.dts92 reg = <0x10>;
111 mount-matrix = "1", "0", "0",
112 "0", "-1", "0",
113 "0", "0", "-1";
117 mount-matrix = "0", "1", "0",
118 "1", "0", "
[all...]
H A Dtegra30-asus-tf300tl.dts191 reg = <0x10>;
210 mount-matrix = "-1", "0", "0",
211 "0", "-1", "0",
212 "0", "0", "1";
216 mount-matrix = "-1", "0", "0",
217 "0", "
[all...]
H A Dtegra30-lg-p880.dts17 pinctrl-0 = <&state_default>;
120 emc-timings-0 {
122 nvidia,ram-code = <0>;
127 nvidia,emem-configuration = < 0x00050001 0xc0000010
128 0x00000001 0x00000001 0x00000002 0x00000000
129 0x0000000
[all...]
H A Dtegra30-lg-p895.dts12 pinctrl-0 = <&state_default>;
123 nvidia,emem-configuration = < 0x00020001 0xc0000010
124 0x00000001 0x00000001 0x00000002 0x00000000
125 0x00000003 0x00000001 0x0000000
[all...]
H A Dtegra124-nyan-blaze-emc.dtsi92 0x40040001
93 0x8000000a
94 0x00000001
95 0x00000001
96 0x00000002
97 0x00000000
98 0x00000002
99 0x00000001
100 0x00000002
101 0x0000000
[all...]
H A Dtegra124-jetson-tk1-emc.dtsi104 0x40040001
105 0x8000000a
106 0x00000001
107 0x00000001
108 0x00000002
109 0x00000000
110 0x00000002
111 0x00000001
112 0x00000003
113 0x0000000
[all...]
H A Dtegra124-apalis-emc.dtsi108 0x40040001 0x8000000a
109 0x00000001 0x00000001
110 0x00000002 0x00000000
111 0x00000002 0x00000001
112 0x00000003 0x0000000
[all...]
H A Dtegra30-asus-nexus7-grouper-memory-timings.dtsi5 emc-timings-0 {
6 nvidia,ram-code = <0>; /* Elpida EDJ2108EDBG-DJL-F */
12 0x00020001 /* MC_EMEM_ARB_CFG */
13 0xc0000020 /* MC_EMEM_ARB_OUTSTANDING_REQ */
14 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
15 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
16 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
17 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
18 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
19 0x0000000
[all...]
H A Dtegra30-asus-tf600t.dts40 reg = <0x80000000 0x80000000>;
50 alloc-ranges = <0x80000000 0x30000000>;
51 size = <0x10000000>; /* 256MiB */
78 pinctrl-0 = <&state_default>;
134 nvidia,lock = <0>;
135 nvidia,io-reset = <0>;
594 nvidia,lock = <0>;
595 nvidia,io-reset = <0>;
[all...]
H A Dtegra124-nyan-big-emc.dtsi263 0x40040001 /* MC_EMEM_ARB_CFG */
264 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */
265 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
266 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
267 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
268 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
269 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
270 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
271 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
272 0x0000000
[all...]
/linux/include/linux/ssb/
H A Dssb_driver_extif.h24 #define SSB_EXTIF_PCMCIA_IOBASE(x) ((x) + 0x100000)
25 #define SSB_EXTIF_PCMCIA_CFGBASE(x) ((x) + 0x200000)
26 #define SSB_EXTIF_CFGIF_BASE(x) ((x) + 0x800000)
27 #define SSB_EXTIF_FLASH_BASE(x) ((x) + 0xc00000)
47 #define SSB_EXTIF_CTL 0x0000
48 #define SSB_EXTIF_CTL_UARTEN (1 << 0) /* UART enable */
49 #define SSB_EXTIF_EXTSTAT 0x0004
50 #define SSB_EXTIF_EXTSTAT_EMODE (1 << 0) /* Endian mode (ro) */
53 #define SSB_EXTIF_PCMCIA_CFG 0x0010
54 #define SSB_EXTIF_PCMCIA_MEMWAIT 0x001
[all...]
/linux/arch/arm/boot/dts/marvell/
H A Darmada-xp-crs326-24g-2s-bit.dts18 flash@0 {
22 reg = <0>; /* Chip select 0 */
27 reg = <0x00000000 0x001f0000>;
31 reg = <0x001f0000 0x00010000>;
35 reg = <0x0020000
[all...]
H A Darmada-xp-crs328-4c-20s-4s-bit.dts18 flash@0 {
22 reg = <0>; /* Chip select 0 */
27 reg = <0x00000000 0x001f0000>;
31 reg = <0x001f0000 0x00010000>;
35 reg = <0x0020000
[all...]
H A Darmada-xp-crs305-1g-4s-bit.dts18 flash@0 {
22 reg = <0>; /* Chip select 0 */
27 reg = <0x00000000 0x001f0000>;
31 reg = <0x001f0000 0x00010000>;
35 reg = <0x0020000
[all...]
H A Darmada-xp-crs328-4c-20s-4s.dtsi11 * internal registers to 0xf1000000 (instead of the default
12 * 0xd0000000). The 0xf1000000 is the default used by the recent,
15 * left internal registers mapped at 0xd0000000. If you are in this
33 reg = <0 0x00000000 0 0x20000000>; /* 512 MB */
50 devbus,badr-skew-ps = <0>;
53 devbus,rd-setup-ps = <0>;
[all...]
H A Darmada-xp-crs305-1g-4s.dtsi11 * internal registers to 0xf1000000 (instead of the default
12 * 0xd0000000). The 0xf1000000 is the default used by the recent,
15 * left internal registers mapped at 0xd0000000. If you are in this
33 reg = <0 0x00000000 0 0x20000000>; /* 512 MB */
50 devbus,badr-skew-ps = <0>;
53 devbus,rd-setup-ps = <0>;
[all...]
H A Darmada-xp-crs326-24g-2s.dtsi11 * internal registers to 0xf1000000 (instead of the default
12 * 0xd0000000). The 0xf1000000 is the default used by the recent,
15 * left internal registers mapped at 0xd0000000. If you are in this
33 reg = <0 0x00000000 0 0x20000000>; /* 512 MB */
50 devbus,badr-skew-ps = <0>;
53 devbus,rd-setup-ps = <0>;
[all...]
/linux/arch/mips/include/asm/
H A Dinst.h25 #define I_JTARGET_SFT 0
26 #define MIPSInst_JTARGET(x) (MIPSInst(x) & 0x03ffffff)
29 #define MIPSInst_RS(x) ((MIPSInst(x) & 0x03e00000) >> I_RS_SFT)
32 #define MIPSInst_RT(x) ((MIPSInst(x) & 0x001f0000) >> I_RT_SFT)
34 #define I_IMM_SFT 0
35 #define MIPSInst_SIMM(x) ((int)((short)(MIPSInst(x) & 0xffff)))
36 #define MIPSInst_UIMM(x) (MIPSInst(x) & 0xffff)
39 #define MIPSInst_CACHEOP(x) ((MIPSInst(x) & 0x001c0000) >> I_CACHEOP_SFT)
42 #define MIPSInst_CACHESEL(x) ((MIPSInst(x) & 0x0003000
[all...]
/linux/drivers/media/platform/imagination/
H A De5010-mmu-regs.h14 #define MMU_MMU_DIR_BASE_ADDR_OFFSET (0x0020)
18 #define MMU_MMU_DIR_BASE_ADDR_MMU_DIR_BASE_ADDR_MASK (0xFFFFFFFF)
19 #define MMU_MMU_DIR_BASE_ADDR_MMU_DIR_BASE_ADDR_SHIFT (0)
21 #define MMU_MMU_TILE_CFG_OFFSET (0x0040)
25 #define MMU_MMU_TILE_CFG_TILE_128INTERLEAVE_MASK (0x00000010)
28 #define MMU_MMU_TILE_CFG_TILE_ENABLE_MASK (0x00000008)
31 #define MMU_MMU_TILE_CFG_TILE_STRIDE_MASK (0x00000007)
32 #define MMU_MMU_TILE_CFG_TILE_STRIDE_SHIFT (0)
34 #define MMU_MMU_TILE_MIN_ADDR_OFFSET (0x0050)
38 #define MMU_MMU_TILE_MIN_ADDR_TILE_MIN_ADDR_MASK (0xFFFFFFF
[all...]
/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,sm7150-gcc.yaml45 reg = <0x00100000 0x001f0000>;
/linux/arch/microblaze/include/asm/
H A Dpvr.h13 #define PVR_MSR_BIT 0x400
22 #define PVR0_PVR_FULL_MASK 0x80000000
23 #define PVR0_USE_BARREL_MASK 0x40000000
24 #define PVR0_USE_DIV_MASK 0x20000000
25 #define PVR0_USE_HW_MUL_MASK 0x10000000
26 #define PVR0_USE_FPU_MASK 0x08000000
27 #define PVR0_USE_EXC_MASK 0x04000000
28 #define PVR0_USE_ICACHE_MASK 0x02000000
29 #define PVR0_USE_DCACHE_MASK 0x01000000
30 #define PVR0_USE_MMU 0x0080000
[all...]
/linux/include/linux/bcma/
H A Dbcma_driver_gmac_cmn.h7 #define BCMA_GMAC_CMN_STAG0 0x000
8 #define BCMA_GMAC_CMN_STAG1 0x004
9 #define BCMA_GMAC_CMN_STAG2 0x008
10 #define BCMA_GMAC_CMN_STAG3 0x00C
11 #define BCMA_GMAC_CMN_PARSER_CTL 0x020
12 #define BCMA_GMAC_CMN_MIB_MAX_LEN 0x024
13 #define BCMA_GMAC_CMN_PHY_ACCESS 0x100
14 #define BCMA_GMAC_CMN_PA_DATA_MASK 0x0000ffff
15 #define BCMA_GMAC_CMN_PA_ADDR_MASK 0x001f0000
[all...]

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