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Searched +full:0 +full:x00064000 (Results 1 – 14 of 14) sorted by relevance

/linux/arch/arm/boot/dts/nvidia/
H A Dtegra124-nyan-blaze-emc.dtsi92 0x40040001
93 0x8000000a
94 0x00000001
95 0x00000001
96 0x00000002
97 0x00000000
98 0x00000002
99 0x00000001
100 0x00000002
101 0x0000000
[all...]
H A Dtegra124-nyan-big-emc.dtsi263 0x40040001 /* MC_EMEM_ARB_CFG */
264 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */
265 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
266 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
267 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
268 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
269 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
270 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
271 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
272 0x0000000
[all...]
H A Dtegra30-lg-p880.dts17 pinctrl-0 = <&state_default>;
120 emc-timings-0 {
122 nvidia,ram-code = <0>;
127 nvidia,emem-configuration = < 0x00050001 0xc0000010
128 0x00000001 0x00000001 0x00000002 0x00000000
129 0x0000000
[all...]
H A Dtegra30-lg-p895.dts12 pinctrl-0 = <&state_default>;
123 nvidia,emem-configuration = < 0x00020001 0xc0000010
124 0x00000001 0x00000001 0x00000002 0x00000000
125 0x00000003 0x00000001 0x0000000
[all...]
H A Dtegra30-asus-tf201.dts67 reg = <0x4d>;
82 mount-matrix = "-1", "0", "0",
83 "0", "-1", "0",
84 "0", "0", "-1";
88 mount-matrix = "0", "-1", "0",
89 "-1", "0", "
[all...]
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dnvidia,tegra124-emc.yaml33 const: 0
51 "^emc-timings-[0-9]+$":
62 "^timing-[0-9]+$":
93 minimum: 0
156 minimum: 0
356 reg = <0x70019000 0x1000>;
369 reg = <0x7001b000 0x1000>;
377 #interconnect-cells = <0>;
[all...]
/linux/arch/arm/boot/dts/nxp/lpc/
H A Dlpc3250-phy3250.dts18 reg = <0x80000000 0x4000000>;
25 gpios = <&gpio 5 1 0>; /* GPO_P3 1, GPIO 80, active high */
30 gpios = <&gpio 5 14 0>; /* GPO_P3 14, GPIO 93, active high */
51 gpio = <&gpio 5 4 0>;
61 gpio = <&gpio 5 0 0>;
71 gpio = <&gpio 5 5 0>;
84 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
94 reg = <0x1
[all...]
/linux/Documentation/devicetree/bindings/mtd/
H A Dlpc32xx-mlc.txt28 reg = <0x200A8000 0x11000>;
29 interrupts = <11 0>;
44 reg = <0x00000000 0x00064000>;
H A Dlpc32xx-slc.txt29 reg = <0x20020000 0x1000>;
46 reg = <0x00000000 0x00064000>;
/linux/drivers/mtd/parsers/
H A Dsharpslpart.c43 #define BLOCK_IS_RESERVED 0xffff
49 #define SHARPSL_PARTINFO1_LADDR 0x00060000
50 #define SHARPSL_PARTINFO2_LADDR 0x00064000
52 #define BOOT_MAGIC 0x424f4f54
53 #define FSRO_MAGIC 0x4653524f
54 #define FSRW_MAGIC 0x46535257
72 u8 freebytes = 0; in sharpsl_nand_check_ooblayout()
73 int section = 0; in sharpsl_nand_check_ooblayout()
91 if (freebytes == 0xf in sharpsl_nand_check_ooblayout()
[all...]
/linux/arch/arm/boot/dts/ti/omap/
H A Domap5-l4.dtsi1 &l4_cfg { /* 0x4a000000 */
4 clocks = <&l4cfg_clkctrl OMAP5_L4_CFG_CLKCTRL 0>;
6 reg = <0x4a000000 0x800>,
7 <0x4a000800 0x800>,
8 <0x4a001000 0x1000>;
12 ranges = <0x00000000 0x4a00000
[all...]
H A Domap4-l4.dtsi2 &l4_cfg { /* 0x4a000000 */
5 clocks = <&l4_cfg_clkctrl OMAP4_L4_CFG_CLKCTRL 0>;
7 reg = <0x4a000000 0x800>,
8 <0x4a000800 0x800>,
9 <0x4a001000 0x1000>;
13 ranges = <0x00000000 0x4a00000
[all...]
/linux/drivers/soc/qcom/
H A Dllcc-qcom.c23 #define ACTIVATE BIT(0)
25 #define ACT_CLEAR BIT(0)
27 #define ACT_CTRL_OPCODE_ACTIVATE BIT(0)
29 #define ACT_CTRL_ACT_TRIG BIT(0)
35 #define ATTR0_RES_WAYS_MASK GENMASK(15, 0)
54 #define LLCC_TRP_ATTR0_CFGn(n) (0x21000 + SZ_8 * n)
55 #define LLCC_TRP_ATTR1_CFGn(n) (0x21004 + SZ_8 * n)
56 #define LLCC_TRP_ATTR2_CFGn(n) (0x21100 + SZ_4 * n)
62 #define LLCC_TRP_SCID_DIS_CAP_ALLOC 0x21f00
63 #define LLCC_TRP_PCB_ACT 0x21f0
[all...]
/linux/drivers/net/wireless/realtek/rtw89/
H A Drtw8852c_table.c10 {0xF0FF0000, 0x00000000},
11 {0xF03300FF, 0x00000001},
12 {0xF03400FF, 0x00000002},
13 {0xF03500FF, 0x00000003},
14 {0xF03600FF, 0x0000000
[all...]