Searched +full:0 +full:x00010000 (Results 1 – 25 of 1037) sorted by relevance
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13 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */14 0x80 0x00000000 0x0 0x00002000>; /* configuration space */17 ranges = <0x81000000 0x[all...]
23 cpu0: cpu@0 {26 reg = <0x0>;27 clocks = <&clockgen QORIQ_CLK_CMUX 0>;36 reg = <0x1>;37 clocks = <&clockgen QORIQ_CLK_CMUX 0>;46 reg = <0x100>;56 reg = <0x101>;66 reg = <0x200>;76 reg = <0x201>;86 reg = <0x30[all...]
30 size = <0 0x1000000>;31 alignment = <0 0x1000000>;34 size = <0 0x400000>;35 alignment = <0 0x400000>;38 size = <0 0x200000[all...]
48 size = <0 0x1000000>;49 alignment = <0 0x1000000>;52 size = <0 0x400000>;53 alignment = <0 0x400000>;56 size = <0 0x200000[all...]
27 size = <0 0x1000000>;28 alignment = <0 0x1000000>;31 size = <0 0x400000>;32 alignment = <0 0x400000>;35 size = <0 0x200000[all...]
17 #size-cells = <0>;19 PowerPC,8536@0 {21 reg = <0>;28 reg = <0 0 0 0>; // Filled by U-Boot32 reg = <0 0xffe05000 0 [all...]
17 #size-cells = <0>;19 PowerPC,8536@0 {21 reg = <0>;28 reg = <0 0 0 0>; // Filled by U-Boot32 reg = <0xf 0xffe05000 0 [all...]
42 size = <0 0x1000000>;43 alignment = <0 0x1000000>;46 size = <0 0x400000>;47 alignment = <0 0x400000>;50 size = <0 0x200000[all...]
50 size = <0 0x1000000>;51 alignment = <0 0x1000000>;55 size = <0 0x400000>;56 alignment = <0 0x400000>;60 size = <0 0x200000[all...]
56 reg = <0xf 0xfe124000 0 0x2000>;57 ranges = <0 0 0xf 0xe8000000 0x0800000058 2 0 [all...]
54 size = <0 0x1000000>;55 alignment = <0 0x1000000>;59 size = <0 0x400000>;60 alignment = <0 0x400000>;64 size = <0 0x200000[all...]
74 size = <0 0x1000000>;75 alignment = <0 0x1000000>;78 size = <0 0x400000>;79 alignment = <0 0x400000>;82 size = <0 0x200000[all...]
68 size = <0 0x1000000>;69 alignment = <0 0x1000000>;72 size = <0 0x400000>;73 alignment = <0 0x400000>;76 size = <0 0x200000[all...]
39 #define NE2000_ADDR 0x4000030040 #define NE2000_ODDOFFSET 0x0001000041 #define NE2000_ADDRSIZE 0x0002000042 #define NE2000_IRQ_VECTOR 0xf049 #define NE2000_ADDR 0x4000030050 #define NE2000_ODDOFFSET 0x0001000051 #define NE2000_ADDRSIZE 0x0002000052 #define NE2000_IRQ_VECTOR 0x1[all...]
7 http://0x04.net/cgit/index.cgi/rules-ng-ng8 git clone git://0x04.net/rules-ng-ng43 #define PIPE_ID_PIPE_3D 0x0000000044 #define PIPE_ID_PIPE_2D 0x0000000145 #define SYNC_RECIPIENT_FE 0x0000000146 #define SYNC_RECIPIENT_RA 0x0000000547 #define SYNC_RECIPIENT_PE 0x0000000748 #define SYNC_RECIPIENT_DE 0x0000000b49 #define SYNC_RECIPIENT_BLT 0x0000001050 #define ENDIAN_MODE_NO_SWAP 0x0000000[all...]
82 .max_level = 0,143 return 0; in cik_query_video_codecs() 205 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); in cik_uvd_ctx_rreg() 216 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); in cik_uvd_ctx_wreg() 245 0xc200, 0xe0ffffff, 0xe0000000250 0x31dc, 0xffffffff, 0x0000080[all...]
98 pinctrl-0 = <&i2c0_pins>;103 reg = <0x29>;110 pinctrl-0 = <&spi0_pins>;114 flash@0 {116 reg = <0>;124 partition@0 {126 reg = <0x00000000 0x00040000>;132 reg = <0x00040000 0x0002000[all...]
12 cpu0: cpu@0 {32 reg = <0x4a002260 0x433 0x4a00232C 0x434 0x4a002378 0x18>;36 interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; /* talert */39 #thermal-sensor-cells = <0>;45 reg = <0x4a307bd[all...]
90 #size-cells = <0>;123 <&dra7_pmx_core 0x3e0>;138 flash@0 {141 reg = <0>;152 partition@0 {154 reg = <0x00000000 0x00010000>;158 reg = <0x00010000 [all...]
17 #define SIS_GCR 0x0018 #define SIS_GCR_MACRO_POWER_DOWN 0x8000000019 #define SIS_GCR_MODEM_ENABLE 0x0001000020 #define SIS_GCR_SOFTWARE_RESET 0x0000000123 #define SIS_GIER 0x0424 #define SIS_GIER_MODEM_TIMER_IRQ_ENABLE 0x0010000025 #define SIS_GIER_MODEM_RX_DMA_IRQ_ENABLE 0x0008000026 #define SIS_GIER_MODEM_TX_DMA_IRQ_ENABLE 0x0004000027 #define SIS_GIER_AC97_GPIO1_IRQ_ENABLE 0x0002000[all...]