1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
2 /*
3 * Copyright (c) 2014-2025, Advanced Micro Devices, Inc.
4 * Copyright (c) 2014, Synopsys, Inc.
5 * All rights reserved
6 */
7
8 #include <linux/module.h>
9 #include <linux/spinlock.h>
10 #include <linux/tcp.h>
11 #include <linux/if_vlan.h>
12 #include <linux/interrupt.h>
13 #include <linux/clk.h>
14 #include <linux/if_ether.h>
15 #include <linux/net_tstamp.h>
16 #include <linux/phy.h>
17 #include <net/vxlan.h>
18
19 #include "xgbe.h"
20 #include "xgbe-common.h"
21
22 static unsigned int ecc_sec_info_threshold = 10;
23 static unsigned int ecc_sec_warn_threshold = 10000;
24 static unsigned int ecc_sec_period = 600;
25 static unsigned int ecc_ded_threshold = 2;
26 static unsigned int ecc_ded_period = 600;
27
28 #ifdef CONFIG_AMD_XGBE_HAVE_ECC
29 /* Only expose the ECC parameters if supported */
30 module_param(ecc_sec_info_threshold, uint, 0644);
31 MODULE_PARM_DESC(ecc_sec_info_threshold,
32 " ECC corrected error informational threshold setting");
33
34 module_param(ecc_sec_warn_threshold, uint, 0644);
35 MODULE_PARM_DESC(ecc_sec_warn_threshold,
36 " ECC corrected error warning threshold setting");
37
38 module_param(ecc_sec_period, uint, 0644);
39 MODULE_PARM_DESC(ecc_sec_period, " ECC corrected error period (in seconds)");
40
41 module_param(ecc_ded_threshold, uint, 0644);
42 MODULE_PARM_DESC(ecc_ded_threshold, " ECC detected error threshold setting");
43
44 module_param(ecc_ded_period, uint, 0644);
45 MODULE_PARM_DESC(ecc_ded_period, " ECC detected error period (in seconds)");
46 #endif
47
48 static int xgbe_one_poll(struct napi_struct *, int);
49 static int xgbe_all_poll(struct napi_struct *, int);
50 static void xgbe_stop(struct xgbe_prv_data *);
51
xgbe_alloc_node(size_t size,int node)52 static void *xgbe_alloc_node(size_t size, int node)
53 {
54 void *mem;
55
56 mem = kzalloc_node(size, GFP_KERNEL, node);
57 if (!mem)
58 mem = kzalloc(size, GFP_KERNEL);
59
60 return mem;
61 }
62
xgbe_free_channels(struct xgbe_prv_data * pdata)63 static void xgbe_free_channels(struct xgbe_prv_data *pdata)
64 {
65 unsigned int i;
66
67 for (i = 0; i < ARRAY_SIZE(pdata->channel); i++) {
68 if (!pdata->channel[i])
69 continue;
70
71 kfree(pdata->channel[i]->rx_ring);
72 kfree(pdata->channel[i]->tx_ring);
73 kfree(pdata->channel[i]);
74
75 pdata->channel[i] = NULL;
76 }
77
78 pdata->channel_count = 0;
79 }
80
xgbe_alloc_channels(struct xgbe_prv_data * pdata)81 static int xgbe_alloc_channels(struct xgbe_prv_data *pdata)
82 {
83 struct xgbe_channel *channel;
84 struct xgbe_ring *ring;
85 unsigned int count, i;
86 unsigned int cpu;
87 int node;
88
89 count = max_t(unsigned int, pdata->tx_ring_count, pdata->rx_ring_count);
90 for (i = 0; i < count; i++) {
91 /* Attempt to use a CPU on the node the device is on */
92 cpu = cpumask_local_spread(i, dev_to_node(pdata->dev));
93
94 /* Set the allocation node based on the returned CPU */
95 node = cpu_to_node(cpu);
96
97 channel = xgbe_alloc_node(sizeof(*channel), node);
98 if (!channel)
99 goto err_mem;
100 pdata->channel[i] = channel;
101
102 snprintf(channel->name, sizeof(channel->name), "channel-%u", i);
103 channel->pdata = pdata;
104 channel->queue_index = i;
105 channel->dma_regs = pdata->xgmac_regs + DMA_CH_BASE +
106 (DMA_CH_INC * i);
107 channel->node = node;
108 cpumask_set_cpu(cpu, &channel->affinity_mask);
109
110 if (pdata->per_channel_irq)
111 channel->dma_irq = pdata->channel_irq[i];
112
113 if (i < pdata->tx_ring_count) {
114 ring = xgbe_alloc_node(sizeof(*ring), node);
115 if (!ring)
116 goto err_mem;
117
118 spin_lock_init(&ring->lock);
119 ring->node = node;
120
121 channel->tx_ring = ring;
122 }
123
124 if (i < pdata->rx_ring_count) {
125 ring = xgbe_alloc_node(sizeof(*ring), node);
126 if (!ring)
127 goto err_mem;
128
129 spin_lock_init(&ring->lock);
130 ring->node = node;
131
132 channel->rx_ring = ring;
133 }
134
135 netif_dbg(pdata, drv, pdata->netdev,
136 "%s: cpu=%u, node=%d\n", channel->name, cpu, node);
137
138 netif_dbg(pdata, drv, pdata->netdev,
139 "%s: dma_regs=%p, dma_irq=%d, tx=%p, rx=%p\n",
140 channel->name, channel->dma_regs, channel->dma_irq,
141 channel->tx_ring, channel->rx_ring);
142 }
143
144 pdata->channel_count = count;
145
146 return 0;
147
148 err_mem:
149 xgbe_free_channels(pdata);
150
151 return -ENOMEM;
152 }
153
xgbe_tx_avail_desc(struct xgbe_ring * ring)154 static inline unsigned int xgbe_tx_avail_desc(struct xgbe_ring *ring)
155 {
156 return (ring->rdesc_count - (ring->cur - ring->dirty));
157 }
158
xgbe_rx_dirty_desc(struct xgbe_ring * ring)159 static inline unsigned int xgbe_rx_dirty_desc(struct xgbe_ring *ring)
160 {
161 return (ring->cur - ring->dirty);
162 }
163
xgbe_maybe_stop_tx_queue(struct xgbe_channel * channel,struct xgbe_ring * ring,unsigned int count)164 static int xgbe_maybe_stop_tx_queue(struct xgbe_channel *channel,
165 struct xgbe_ring *ring, unsigned int count)
166 {
167 struct xgbe_prv_data *pdata = channel->pdata;
168
169 if (count > xgbe_tx_avail_desc(ring)) {
170 netif_info(pdata, drv, pdata->netdev,
171 "Tx queue stopped, not enough descriptors available\n");
172 netif_stop_subqueue(pdata->netdev, channel->queue_index);
173 ring->tx.queue_stopped = 1;
174
175 /* If we haven't notified the hardware because of xmit_more
176 * support, tell it now
177 */
178 if (ring->tx.xmit_more)
179 pdata->hw_if.tx_start_xmit(channel, ring);
180
181 return NETDEV_TX_BUSY;
182 }
183
184 return 0;
185 }
186
xgbe_calc_rx_buf_size(struct net_device * netdev,unsigned int mtu)187 static int xgbe_calc_rx_buf_size(struct net_device *netdev, unsigned int mtu)
188 {
189 unsigned int rx_buf_size;
190
191 rx_buf_size = mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
192 rx_buf_size = clamp_val(rx_buf_size, XGBE_RX_MIN_BUF_SIZE, PAGE_SIZE);
193
194 rx_buf_size = (rx_buf_size + XGBE_RX_BUF_ALIGN - 1) &
195 ~(XGBE_RX_BUF_ALIGN - 1);
196
197 return rx_buf_size;
198 }
199
xgbe_enable_rx_tx_int(struct xgbe_prv_data * pdata,struct xgbe_channel * channel)200 static void xgbe_enable_rx_tx_int(struct xgbe_prv_data *pdata,
201 struct xgbe_channel *channel)
202 {
203 struct xgbe_hw_if *hw_if = &pdata->hw_if;
204 enum xgbe_int int_id;
205
206 if (channel->tx_ring && channel->rx_ring)
207 int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
208 else if (channel->tx_ring)
209 int_id = XGMAC_INT_DMA_CH_SR_TI;
210 else if (channel->rx_ring)
211 int_id = XGMAC_INT_DMA_CH_SR_RI;
212 else
213 return;
214
215 hw_if->enable_int(channel, int_id);
216 }
217
xgbe_enable_rx_tx_ints(struct xgbe_prv_data * pdata)218 static void xgbe_enable_rx_tx_ints(struct xgbe_prv_data *pdata)
219 {
220 unsigned int i;
221
222 for (i = 0; i < pdata->channel_count; i++)
223 xgbe_enable_rx_tx_int(pdata, pdata->channel[i]);
224 }
225
xgbe_disable_rx_tx_int(struct xgbe_prv_data * pdata,struct xgbe_channel * channel)226 static void xgbe_disable_rx_tx_int(struct xgbe_prv_data *pdata,
227 struct xgbe_channel *channel)
228 {
229 struct xgbe_hw_if *hw_if = &pdata->hw_if;
230 enum xgbe_int int_id;
231
232 if (channel->tx_ring && channel->rx_ring)
233 int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
234 else if (channel->tx_ring)
235 int_id = XGMAC_INT_DMA_CH_SR_TI;
236 else if (channel->rx_ring)
237 int_id = XGMAC_INT_DMA_CH_SR_RI;
238 else
239 return;
240
241 hw_if->disable_int(channel, int_id);
242 }
243
xgbe_disable_rx_tx_ints(struct xgbe_prv_data * pdata)244 static void xgbe_disable_rx_tx_ints(struct xgbe_prv_data *pdata)
245 {
246 unsigned int i;
247
248 for (i = 0; i < pdata->channel_count; i++)
249 xgbe_disable_rx_tx_int(pdata, pdata->channel[i]);
250 }
251
xgbe_ecc_sec(struct xgbe_prv_data * pdata,unsigned long * period,unsigned int * count,const char * area)252 static bool xgbe_ecc_sec(struct xgbe_prv_data *pdata, unsigned long *period,
253 unsigned int *count, const char *area)
254 {
255 if (time_before(jiffies, *period)) {
256 (*count)++;
257 } else {
258 *period = jiffies + (ecc_sec_period * HZ);
259 *count = 1;
260 }
261
262 if (*count > ecc_sec_info_threshold)
263 dev_warn_once(pdata->dev,
264 "%s ECC corrected errors exceed informational threshold\n",
265 area);
266
267 if (*count > ecc_sec_warn_threshold) {
268 dev_warn_once(pdata->dev,
269 "%s ECC corrected errors exceed warning threshold\n",
270 area);
271 return true;
272 }
273
274 return false;
275 }
276
xgbe_ecc_ded(struct xgbe_prv_data * pdata,unsigned long * period,unsigned int * count,const char * area)277 static bool xgbe_ecc_ded(struct xgbe_prv_data *pdata, unsigned long *period,
278 unsigned int *count, const char *area)
279 {
280 if (time_before(jiffies, *period)) {
281 (*count)++;
282 } else {
283 *period = jiffies + (ecc_ded_period * HZ);
284 *count = 1;
285 }
286
287 if (*count > ecc_ded_threshold) {
288 netdev_alert(pdata->netdev,
289 "%s ECC detected errors exceed threshold\n",
290 area);
291 return true;
292 }
293
294 return false;
295 }
296
xgbe_ecc_isr_bh_work(struct work_struct * work)297 static void xgbe_ecc_isr_bh_work(struct work_struct *work)
298 {
299 struct xgbe_prv_data *pdata = from_work(pdata, work, ecc_bh_work);
300 unsigned int ecc_isr;
301 bool stop = false;
302
303 /* Mask status with only the interrupts we care about */
304 ecc_isr = XP_IOREAD(pdata, XP_ECC_ISR);
305 ecc_isr &= XP_IOREAD(pdata, XP_ECC_IER);
306 netif_dbg(pdata, intr, pdata->netdev, "ECC_ISR=%#010x\n", ecc_isr);
307
308 if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, TX_DED)) {
309 stop |= xgbe_ecc_ded(pdata, &pdata->tx_ded_period,
310 &pdata->tx_ded_count, "TX fifo");
311 }
312
313 if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, RX_DED)) {
314 stop |= xgbe_ecc_ded(pdata, &pdata->rx_ded_period,
315 &pdata->rx_ded_count, "RX fifo");
316 }
317
318 if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, DESC_DED)) {
319 stop |= xgbe_ecc_ded(pdata, &pdata->desc_ded_period,
320 &pdata->desc_ded_count,
321 "descriptor cache");
322 }
323
324 if (stop) {
325 pdata->hw_if.disable_ecc_ded(pdata);
326 schedule_work(&pdata->stopdev_work);
327 goto out;
328 }
329
330 if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, TX_SEC)) {
331 if (xgbe_ecc_sec(pdata, &pdata->tx_sec_period,
332 &pdata->tx_sec_count, "TX fifo"))
333 pdata->hw_if.disable_ecc_sec(pdata, XGBE_ECC_SEC_TX);
334 }
335
336 if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, RX_SEC))
337 if (xgbe_ecc_sec(pdata, &pdata->rx_sec_period,
338 &pdata->rx_sec_count, "RX fifo"))
339 pdata->hw_if.disable_ecc_sec(pdata, XGBE_ECC_SEC_RX);
340
341 if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, DESC_SEC))
342 if (xgbe_ecc_sec(pdata, &pdata->desc_sec_period,
343 &pdata->desc_sec_count, "descriptor cache"))
344 pdata->hw_if.disable_ecc_sec(pdata, XGBE_ECC_SEC_DESC);
345
346 out:
347 /* Clear all ECC interrupts */
348 XP_IOWRITE(pdata, XP_ECC_ISR, ecc_isr);
349
350 /* Reissue interrupt if status is not clear */
351 if (pdata->vdata->irq_reissue_support)
352 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 1);
353 }
354
xgbe_ecc_isr(int irq,void * data)355 static irqreturn_t xgbe_ecc_isr(int irq, void *data)
356 {
357 struct xgbe_prv_data *pdata = data;
358
359 if (pdata->isr_as_bh_work)
360 queue_work(system_bh_wq, &pdata->ecc_bh_work);
361 else
362 xgbe_ecc_isr_bh_work(&pdata->ecc_bh_work);
363
364 return IRQ_HANDLED;
365 }
366
xgbe_isr_bh_work(struct work_struct * work)367 static void xgbe_isr_bh_work(struct work_struct *work)
368 {
369 struct xgbe_prv_data *pdata = from_work(pdata, work, dev_bh_work);
370 unsigned int mac_isr, mac_tssr, mac_mdioisr;
371 struct xgbe_hw_if *hw_if = &pdata->hw_if;
372 bool per_ch_irq, ti, ri, rbu, fbe;
373 unsigned int dma_isr, dma_ch_isr;
374 struct xgbe_channel *channel;
375 unsigned int i;
376
377 /* The DMA interrupt status register also reports MAC and MTL
378 * interrupts. So for polling mode, we just need to check for
379 * this register to be non-zero
380 */
381 dma_isr = XGMAC_IOREAD(pdata, DMA_ISR);
382 if (!dma_isr)
383 goto isr_done;
384
385 netif_dbg(pdata, intr, pdata->netdev, "DMA_ISR=%#010x\n", dma_isr);
386
387 for (i = 0; i < pdata->channel_count; i++) {
388 bool schedule_napi = false;
389 struct napi_struct *napi;
390
391 if (!(dma_isr & (1 << i)))
392 continue;
393
394 channel = pdata->channel[i];
395
396 dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR);
397
398 /* Precompute flags once */
399 ti = !!XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, TI);
400 ri = !!XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RI);
401 rbu = !!XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RBU);
402 fbe = !!XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, FBE);
403
404 netif_dbg(pdata, intr, pdata->netdev, "DMA_CH%u_ISR=%#010x\n",
405 i, dma_ch_isr);
406
407 per_ch_irq = pdata->per_channel_irq;
408
409 /*
410 * Decide which NAPI to use and whether to schedule:
411 * - When not using per-channel IRQs: schedule on global NAPI
412 * if TI or RI are set.
413 * - RBU should also trigger NAPI (either per-channel or global)
414 * to allow refill.
415 */
416 if (!per_ch_irq && (ti || ri))
417 schedule_napi = true;
418
419 if (rbu) {
420 schedule_napi = true;
421 pdata->ext_stats.rx_buffer_unavailable++;
422 }
423
424 napi = per_ch_irq ? &channel->napi : &pdata->napi;
425
426 if (schedule_napi && napi_schedule_prep(napi)) {
427 /* Disable interrupts appropriately before polling */
428 if (per_ch_irq) {
429 if (pdata->channel_irq_mode)
430 xgbe_disable_rx_tx_int(pdata, channel);
431 else
432 disable_irq_nosync(channel->dma_irq);
433 } else {
434 xgbe_disable_rx_tx_ints(pdata);
435 }
436
437 /* Turn on polling */
438 __napi_schedule(napi);
439 } else {
440 /*
441 * Don't clear Rx/Tx status if doing per-channel DMA
442 * interrupts; those bits will be serviced/cleared by
443 * the per-channel ISR/NAPI. In non-per-channel mode
444 * when we're not scheduling NAPI here, ensure we don't
445 * accidentally clear TI/RI in HW: zero them in the
446 * local copy so that the eventual write-back does not
447 * clear TI/RI.
448 */
449 XGMAC_SET_BITS(dma_ch_isr, DMA_CH_SR, TI, 0);
450 XGMAC_SET_BITS(dma_ch_isr, DMA_CH_SR, RI, 0);
451 }
452
453 /* Restart the device on a Fatal Bus Error */
454 if (fbe)
455 schedule_work(&pdata->restart_work);
456
457 /* Clear interrupt signals */
458 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr);
459 }
460
461 if (XGMAC_GET_BITS(dma_isr, DMA_ISR, MACIS)) {
462 mac_isr = XGMAC_IOREAD(pdata, MAC_ISR);
463
464 netif_dbg(pdata, intr, pdata->netdev, "MAC_ISR=%#010x\n",
465 mac_isr);
466
467 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCTXIS))
468 hw_if->tx_mmc_int(pdata);
469
470 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCRXIS))
471 hw_if->rx_mmc_int(pdata);
472
473 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, TSIS)) {
474 mac_tssr = XGMAC_IOREAD(pdata, MAC_TSSR);
475
476 netif_dbg(pdata, intr, pdata->netdev,
477 "MAC_TSSR=%#010x\n", mac_tssr);
478
479 if (XGMAC_GET_BITS(mac_tssr, MAC_TSSR, TXTSC)) {
480 /* Read Tx Timestamp to clear interrupt */
481 pdata->tx_tstamp =
482 xgbe_get_tx_tstamp(pdata);
483 queue_work(pdata->dev_workqueue,
484 &pdata->tx_tstamp_work);
485 }
486 }
487
488 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, SMI)) {
489 mac_mdioisr = XGMAC_IOREAD(pdata, MAC_MDIOISR);
490
491 netif_dbg(pdata, intr, pdata->netdev,
492 "MAC_MDIOISR=%#010x\n", mac_mdioisr);
493
494 if (XGMAC_GET_BITS(mac_mdioisr, MAC_MDIOISR,
495 SNGLCOMPINT))
496 complete(&pdata->mdio_complete);
497 }
498 }
499
500 isr_done:
501 /* If there is not a separate AN irq, handle it here */
502 if (pdata->dev_irq == pdata->an_irq)
503 pdata->phy_if.an_isr(pdata);
504
505 /* If there is not a separate ECC irq, handle it here */
506 if (pdata->vdata->ecc_support && (pdata->dev_irq == pdata->ecc_irq))
507 xgbe_ecc_isr_bh_work(&pdata->ecc_bh_work);
508
509 /* If there is not a separate I2C irq, handle it here */
510 if (pdata->vdata->i2c_support && (pdata->dev_irq == pdata->i2c_irq))
511 pdata->i2c_if.i2c_isr(pdata);
512
513 /* Reissue interrupt if status is not clear */
514 if (pdata->vdata->irq_reissue_support) {
515 unsigned int reissue_mask;
516
517 reissue_mask = 1 << 0;
518 if (!pdata->per_channel_irq)
519 reissue_mask |= 0xffff << 4;
520
521 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, reissue_mask);
522 }
523 }
524
xgbe_isr(int irq,void * data)525 static irqreturn_t xgbe_isr(int irq, void *data)
526 {
527 struct xgbe_prv_data *pdata = data;
528
529 if (pdata->isr_as_bh_work)
530 queue_work(system_bh_wq, &pdata->dev_bh_work);
531 else
532 xgbe_isr_bh_work(&pdata->dev_bh_work);
533
534 return IRQ_HANDLED;
535 }
536
xgbe_dma_isr(int irq,void * data)537 static irqreturn_t xgbe_dma_isr(int irq, void *data)
538 {
539 struct xgbe_channel *channel = data;
540 struct xgbe_prv_data *pdata = channel->pdata;
541 unsigned int dma_status;
542
543 /* Per channel DMA interrupts are enabled, so we use the per
544 * channel napi structure and not the private data napi structure
545 */
546 if (napi_schedule_prep(&channel->napi)) {
547 /* Disable Tx and Rx interrupts */
548 if (pdata->channel_irq_mode)
549 xgbe_disable_rx_tx_int(pdata, channel);
550 else
551 disable_irq_nosync(channel->dma_irq);
552
553 /* Turn on polling */
554 __napi_schedule_irqoff(&channel->napi);
555 }
556
557 /* Clear Tx/Rx signals */
558 dma_status = 0;
559 XGMAC_SET_BITS(dma_status, DMA_CH_SR, TI, 1);
560 XGMAC_SET_BITS(dma_status, DMA_CH_SR, RI, 1);
561 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_status);
562
563 return IRQ_HANDLED;
564 }
565
xgbe_tx_timer(struct timer_list * t)566 static void xgbe_tx_timer(struct timer_list *t)
567 {
568 struct xgbe_channel *channel = timer_container_of(channel, t,
569 tx_timer);
570 struct xgbe_prv_data *pdata = channel->pdata;
571 struct napi_struct *napi;
572
573 DBGPR("-->xgbe_tx_timer\n");
574
575 napi = (pdata->per_channel_irq) ? &channel->napi : &pdata->napi;
576
577 if (napi_schedule_prep(napi)) {
578 /* Disable Tx and Rx interrupts */
579 if (pdata->per_channel_irq)
580 if (pdata->channel_irq_mode)
581 xgbe_disable_rx_tx_int(pdata, channel);
582 else
583 disable_irq_nosync(channel->dma_irq);
584 else
585 xgbe_disable_rx_tx_ints(pdata);
586
587 /* Turn on polling */
588 __napi_schedule(napi);
589 }
590
591 channel->tx_timer_active = 0;
592
593 DBGPR("<--xgbe_tx_timer\n");
594 }
595
xgbe_service(struct work_struct * work)596 static void xgbe_service(struct work_struct *work)
597 {
598 struct xgbe_prv_data *pdata = container_of(work,
599 struct xgbe_prv_data,
600 service_work);
601
602 pdata->phy_if.phy_status(pdata);
603 }
604
xgbe_service_timer(struct timer_list * t)605 static void xgbe_service_timer(struct timer_list *t)
606 {
607 struct xgbe_prv_data *pdata = timer_container_of(pdata, t,
608 service_timer);
609 struct xgbe_channel *channel;
610 unsigned int poll_interval;
611 unsigned int i;
612
613 queue_work(pdata->dev_workqueue, &pdata->service_work);
614
615 /* Adaptive link status polling for fast failure detection:
616 *
617 * - When carrier is UP: poll every 100ms for rapid link-down detection
618 * Enables sub-second response to link failures, minimizing traffic
619 * loss.
620 *
621 * - When carrier is DOWN: poll every 1s to conserve CPU resources
622 * Link-up events are less time-critical.
623 *
624 * The 100ms active polling interval balances responsiveness with
625 * efficiency:
626 * - Provides ~100-200ms link-down detection (10x faster than 1s
627 * polling)
628 * - Minimal CPU overhead (1% vs 0.1% with 1s polling)
629 * - Enables fast failover in link aggregation deployments
630 */
631 if (netif_running(pdata->netdev) && netif_carrier_ok(pdata->netdev))
632 poll_interval = msecs_to_jiffies(100); /* 100ms when up */
633 else
634 poll_interval = HZ; /* 1 second when down */
635
636 mod_timer(&pdata->service_timer, jiffies + poll_interval);
637
638 if (!pdata->tx_usecs)
639 return;
640
641 for (i = 0; i < pdata->channel_count; i++) {
642 channel = pdata->channel[i];
643 if (!channel->tx_ring || channel->tx_timer_active)
644 break;
645 channel->tx_timer_active = 1;
646 mod_timer(&channel->tx_timer,
647 jiffies + usecs_to_jiffies(pdata->tx_usecs));
648 }
649 }
650
xgbe_init_timers(struct xgbe_prv_data * pdata)651 static void xgbe_init_timers(struct xgbe_prv_data *pdata)
652 {
653 struct xgbe_channel *channel;
654 unsigned int i;
655
656 timer_setup(&pdata->service_timer, xgbe_service_timer, 0);
657
658 for (i = 0; i < pdata->channel_count; i++) {
659 channel = pdata->channel[i];
660 if (!channel->tx_ring)
661 break;
662
663 timer_setup(&channel->tx_timer, xgbe_tx_timer, 0);
664 }
665 }
666
xgbe_start_timers(struct xgbe_prv_data * pdata)667 static void xgbe_start_timers(struct xgbe_prv_data *pdata)
668 {
669 mod_timer(&pdata->service_timer, jiffies + HZ);
670 }
671
xgbe_stop_timers(struct xgbe_prv_data * pdata)672 static void xgbe_stop_timers(struct xgbe_prv_data *pdata)
673 {
674 struct xgbe_channel *channel;
675 unsigned int i;
676
677 timer_delete_sync(&pdata->service_timer);
678
679 for (i = 0; i < pdata->channel_count; i++) {
680 channel = pdata->channel[i];
681 if (!channel->tx_ring)
682 break;
683
684 /* Deactivate the Tx timer */
685 timer_delete_sync(&channel->tx_timer);
686 channel->tx_timer_active = 0;
687 }
688 }
689
xgbe_get_all_hw_features(struct xgbe_prv_data * pdata)690 void xgbe_get_all_hw_features(struct xgbe_prv_data *pdata)
691 {
692 unsigned int mac_hfr0, mac_hfr1, mac_hfr2;
693 struct xgbe_hw_features *hw_feat = &pdata->hw_feat;
694
695 mac_hfr0 = XGMAC_IOREAD(pdata, MAC_HWF0R);
696 mac_hfr1 = XGMAC_IOREAD(pdata, MAC_HWF1R);
697 mac_hfr2 = XGMAC_IOREAD(pdata, MAC_HWF2R);
698
699 memset(hw_feat, 0, sizeof(*hw_feat));
700
701 hw_feat->version = XGMAC_IOREAD(pdata, MAC_VR);
702
703 /* Hardware feature register 0 */
704 hw_feat->gmii = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, GMIISEL);
705 hw_feat->vlhash = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VLHASH);
706 hw_feat->sma = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SMASEL);
707 hw_feat->rwk = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RWKSEL);
708 hw_feat->mgk = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MGKSEL);
709 hw_feat->mmc = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MMCSEL);
710 hw_feat->aoe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, ARPOFFSEL);
711 hw_feat->ts = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSEL);
712 hw_feat->eee = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, EEESEL);
713 hw_feat->tx_coe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TXCOESEL);
714 hw_feat->rx_coe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RXCOESEL);
715 hw_feat->addn_mac = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R,
716 ADDMACADRSEL);
717 hw_feat->ts_src = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSTSSEL);
718 hw_feat->sa_vlan_ins = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SAVLANINS);
719 hw_feat->vxn = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VXN);
720
721 /* Hardware feature register 1 */
722 hw_feat->rx_fifo_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
723 RXFIFOSIZE);
724 hw_feat->tx_fifo_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
725 TXFIFOSIZE);
726 hw_feat->adv_ts_hi = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADVTHWORD);
727 hw_feat->dma_width = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADDR64);
728 hw_feat->dcb = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DCBEN);
729 hw_feat->sph = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, SPHEN);
730 hw_feat->tso = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, TSOEN);
731 hw_feat->dma_debug = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DBGMEMA);
732 hw_feat->rss = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, RSSEN);
733 hw_feat->tc_cnt = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, NUMTC);
734 hw_feat->hash_table_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
735 HASHTBLSZ);
736 hw_feat->l3l4_filter_num = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
737 L3L4FNUM);
738
739 /* Hardware feature register 2 */
740 hw_feat->rx_q_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXQCNT);
741 hw_feat->tx_q_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXQCNT);
742 hw_feat->rx_ch_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXCHCNT);
743 hw_feat->tx_ch_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXCHCNT);
744 hw_feat->pps_out_num = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, PPSOUTNUM);
745 hw_feat->aux_snap_num = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, AUXSNAPNUM);
746
747 /* Sanity check and warn if hardware reports more than supported */
748 if (hw_feat->pps_out_num > XGBE_MAX_PPS_OUT) {
749 dev_warn(pdata->dev,
750 "Hardware reports %u PPS outputs, limiting to %u\n",
751 hw_feat->pps_out_num, XGBE_MAX_PPS_OUT);
752 hw_feat->pps_out_num = XGBE_MAX_PPS_OUT;
753 }
754
755 if (hw_feat->aux_snap_num > XGBE_MAX_AUX_SNAP) {
756 dev_warn(pdata->dev,
757 "Hardware reports %u aux snapshot inputs, limiting to %u\n",
758 hw_feat->aux_snap_num, XGBE_MAX_AUX_SNAP);
759 hw_feat->aux_snap_num = XGBE_MAX_AUX_SNAP;
760 }
761
762 /* Translate the Hash Table size into actual number */
763 switch (hw_feat->hash_table_size) {
764 case 0:
765 break;
766 case 1:
767 hw_feat->hash_table_size = 64;
768 break;
769 case 2:
770 hw_feat->hash_table_size = 128;
771 break;
772 case 3:
773 hw_feat->hash_table_size = 256;
774 break;
775 }
776
777 /* Translate the address width setting into actual number */
778 switch (hw_feat->dma_width) {
779 case 0:
780 hw_feat->dma_width = 32;
781 break;
782 case 1:
783 hw_feat->dma_width = 40;
784 break;
785 case 2:
786 hw_feat->dma_width = 48;
787 break;
788 default:
789 hw_feat->dma_width = 32;
790 }
791
792 /* The Queue, Channel and TC counts are zero based so increment them
793 * to get the actual number
794 */
795 hw_feat->rx_q_cnt++;
796 hw_feat->tx_q_cnt++;
797 hw_feat->rx_ch_cnt++;
798 hw_feat->tx_ch_cnt++;
799 hw_feat->tc_cnt++;
800
801 /* Translate the fifo sizes into actual numbers */
802 hw_feat->rx_fifo_size = 1 << (hw_feat->rx_fifo_size + 7);
803 hw_feat->tx_fifo_size = 1 << (hw_feat->tx_fifo_size + 7);
804
805 if (netif_msg_probe(pdata)) {
806 dev_dbg(pdata->dev, "Hardware features:\n");
807
808 /* Hardware feature register 0 */
809 dev_dbg(pdata->dev, " 1GbE support : %s\n",
810 hw_feat->gmii ? "yes" : "no");
811 dev_dbg(pdata->dev, " VLAN hash filter : %s\n",
812 hw_feat->vlhash ? "yes" : "no");
813 dev_dbg(pdata->dev, " MDIO interface : %s\n",
814 hw_feat->sma ? "yes" : "no");
815 dev_dbg(pdata->dev, " Wake-up packet support : %s\n",
816 hw_feat->rwk ? "yes" : "no");
817 dev_dbg(pdata->dev, " Magic packet support : %s\n",
818 hw_feat->mgk ? "yes" : "no");
819 dev_dbg(pdata->dev, " Management counters : %s\n",
820 hw_feat->mmc ? "yes" : "no");
821 dev_dbg(pdata->dev, " ARP offload : %s\n",
822 hw_feat->aoe ? "yes" : "no");
823 dev_dbg(pdata->dev, " IEEE 1588-2008 Timestamp : %s\n",
824 hw_feat->ts ? "yes" : "no");
825 dev_dbg(pdata->dev, " Energy Efficient Ethernet : %s\n",
826 hw_feat->eee ? "yes" : "no");
827 dev_dbg(pdata->dev, " TX checksum offload : %s\n",
828 hw_feat->tx_coe ? "yes" : "no");
829 dev_dbg(pdata->dev, " RX checksum offload : %s\n",
830 hw_feat->rx_coe ? "yes" : "no");
831 dev_dbg(pdata->dev, " Additional MAC addresses : %u\n",
832 hw_feat->addn_mac);
833 dev_dbg(pdata->dev, " Timestamp source : %s\n",
834 (hw_feat->ts_src == 1) ? "internal" :
835 (hw_feat->ts_src == 2) ? "external" :
836 (hw_feat->ts_src == 3) ? "internal/external" : "n/a");
837 dev_dbg(pdata->dev, " SA/VLAN insertion : %s\n",
838 hw_feat->sa_vlan_ins ? "yes" : "no");
839 dev_dbg(pdata->dev, " VXLAN/NVGRE support : %s\n",
840 hw_feat->vxn ? "yes" : "no");
841
842 /* Hardware feature register 1 */
843 dev_dbg(pdata->dev, " RX fifo size : %u\n",
844 hw_feat->rx_fifo_size);
845 dev_dbg(pdata->dev, " TX fifo size : %u\n",
846 hw_feat->tx_fifo_size);
847 dev_dbg(pdata->dev, " IEEE 1588 high word : %s\n",
848 hw_feat->adv_ts_hi ? "yes" : "no");
849 dev_dbg(pdata->dev, " DMA width : %u\n",
850 hw_feat->dma_width);
851 dev_dbg(pdata->dev, " Data Center Bridging : %s\n",
852 hw_feat->dcb ? "yes" : "no");
853 dev_dbg(pdata->dev, " Split header : %s\n",
854 hw_feat->sph ? "yes" : "no");
855 dev_dbg(pdata->dev, " TCP Segmentation Offload : %s\n",
856 hw_feat->tso ? "yes" : "no");
857 dev_dbg(pdata->dev, " Debug memory interface : %s\n",
858 hw_feat->dma_debug ? "yes" : "no");
859 dev_dbg(pdata->dev, " Receive Side Scaling : %s\n",
860 hw_feat->rss ? "yes" : "no");
861 dev_dbg(pdata->dev, " Traffic Class count : %u\n",
862 hw_feat->tc_cnt);
863 dev_dbg(pdata->dev, " Hash table size : %u\n",
864 hw_feat->hash_table_size);
865 dev_dbg(pdata->dev, " L3/L4 Filters : %u\n",
866 hw_feat->l3l4_filter_num);
867
868 /* Hardware feature register 2 */
869 dev_dbg(pdata->dev, " RX queue count : %u\n",
870 hw_feat->rx_q_cnt);
871 dev_dbg(pdata->dev, " TX queue count : %u\n",
872 hw_feat->tx_q_cnt);
873 dev_dbg(pdata->dev, " RX DMA channel count : %u\n",
874 hw_feat->rx_ch_cnt);
875 dev_dbg(pdata->dev, " TX DMA channel count : %u\n",
876 hw_feat->rx_ch_cnt);
877 dev_dbg(pdata->dev, " PPS outputs : %u\n",
878 hw_feat->pps_out_num);
879 dev_dbg(pdata->dev, " Auxiliary snapshot inputs : %u\n",
880 hw_feat->aux_snap_num);
881 }
882 }
883
xgbe_vxlan_set_port(struct net_device * netdev,unsigned int table,unsigned int entry,struct udp_tunnel_info * ti)884 static int xgbe_vxlan_set_port(struct net_device *netdev, unsigned int table,
885 unsigned int entry, struct udp_tunnel_info *ti)
886 {
887 struct xgbe_prv_data *pdata = netdev_priv(netdev);
888
889 pdata->vxlan_port = be16_to_cpu(ti->port);
890 pdata->hw_if.enable_vxlan(pdata);
891
892 return 0;
893 }
894
xgbe_vxlan_unset_port(struct net_device * netdev,unsigned int table,unsigned int entry,struct udp_tunnel_info * ti)895 static int xgbe_vxlan_unset_port(struct net_device *netdev, unsigned int table,
896 unsigned int entry, struct udp_tunnel_info *ti)
897 {
898 struct xgbe_prv_data *pdata = netdev_priv(netdev);
899
900 pdata->hw_if.disable_vxlan(pdata);
901 pdata->vxlan_port = 0;
902
903 return 0;
904 }
905
906 static const struct udp_tunnel_nic_info xgbe_udp_tunnels = {
907 .set_port = xgbe_vxlan_set_port,
908 .unset_port = xgbe_vxlan_unset_port,
909 .flags = UDP_TUNNEL_NIC_INFO_OPEN_ONLY,
910 .tables = {
911 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN, },
912 },
913 };
914
xgbe_get_udp_tunnel_info(void)915 const struct udp_tunnel_nic_info *xgbe_get_udp_tunnel_info(void)
916 {
917 return &xgbe_udp_tunnels;
918 }
919
xgbe_napi_enable(struct xgbe_prv_data * pdata,unsigned int add)920 static void xgbe_napi_enable(struct xgbe_prv_data *pdata, unsigned int add)
921 {
922 struct xgbe_channel *channel;
923 unsigned int i;
924
925 if (pdata->per_channel_irq) {
926 for (i = 0; i < pdata->channel_count; i++) {
927 channel = pdata->channel[i];
928 if (add)
929 netif_napi_add(pdata->netdev, &channel->napi,
930 xgbe_one_poll);
931
932 napi_enable(&channel->napi);
933 }
934 } else {
935 if (add)
936 netif_napi_add(pdata->netdev, &pdata->napi,
937 xgbe_all_poll);
938
939 napi_enable(&pdata->napi);
940 }
941 }
942
xgbe_napi_disable(struct xgbe_prv_data * pdata,unsigned int del)943 static void xgbe_napi_disable(struct xgbe_prv_data *pdata, unsigned int del)
944 {
945 struct xgbe_channel *channel;
946 unsigned int i;
947
948 if (pdata->per_channel_irq) {
949 for (i = 0; i < pdata->channel_count; i++) {
950 channel = pdata->channel[i];
951 napi_disable(&channel->napi);
952
953 if (del)
954 netif_napi_del(&channel->napi);
955 }
956 } else {
957 napi_disable(&pdata->napi);
958
959 if (del)
960 netif_napi_del(&pdata->napi);
961 }
962 }
963
xgbe_request_irqs(struct xgbe_prv_data * pdata)964 static int xgbe_request_irqs(struct xgbe_prv_data *pdata)
965 {
966 struct xgbe_channel *channel;
967 struct net_device *netdev = pdata->netdev;
968 unsigned int i;
969 int ret;
970
971 INIT_WORK(&pdata->dev_bh_work, xgbe_isr_bh_work);
972 INIT_WORK(&pdata->ecc_bh_work, xgbe_ecc_isr_bh_work);
973
974 ret = devm_request_irq(pdata->dev, pdata->dev_irq, xgbe_isr, 0,
975 netdev_name(netdev), pdata);
976 if (ret) {
977 netdev_alert(netdev, "error requesting irq %d\n",
978 pdata->dev_irq);
979 return ret;
980 }
981
982 if (pdata->vdata->ecc_support && (pdata->dev_irq != pdata->ecc_irq)) {
983 ret = devm_request_irq(pdata->dev, pdata->ecc_irq, xgbe_ecc_isr,
984 0, pdata->ecc_name, pdata);
985 if (ret) {
986 netdev_alert(netdev, "error requesting ecc irq %d\n",
987 pdata->ecc_irq);
988 goto err_dev_irq;
989 }
990 }
991
992 if (!pdata->per_channel_irq)
993 return 0;
994
995 for (i = 0; i < pdata->channel_count; i++) {
996 channel = pdata->channel[i];
997 snprintf(channel->dma_irq_name,
998 sizeof(channel->dma_irq_name) - 1,
999 "%s-TxRx-%u", netdev_name(netdev),
1000 channel->queue_index);
1001
1002 ret = devm_request_irq(pdata->dev, channel->dma_irq,
1003 xgbe_dma_isr, 0,
1004 channel->dma_irq_name, channel);
1005 if (ret) {
1006 netdev_alert(netdev, "error requesting irq %d\n",
1007 channel->dma_irq);
1008 goto err_dma_irq;
1009 }
1010
1011 irq_set_affinity_hint(channel->dma_irq,
1012 &channel->affinity_mask);
1013 }
1014
1015 return 0;
1016
1017 err_dma_irq:
1018 /* Using an unsigned int, 'i' will go to UINT_MAX and exit */
1019 for (i--; i < pdata->channel_count; i--) {
1020 channel = pdata->channel[i];
1021
1022 irq_set_affinity_hint(channel->dma_irq, NULL);
1023 devm_free_irq(pdata->dev, channel->dma_irq, channel);
1024 }
1025
1026 if (pdata->vdata->ecc_support && (pdata->dev_irq != pdata->ecc_irq))
1027 devm_free_irq(pdata->dev, pdata->ecc_irq, pdata);
1028
1029 err_dev_irq:
1030 devm_free_irq(pdata->dev, pdata->dev_irq, pdata);
1031
1032 return ret;
1033 }
1034
xgbe_free_irqs(struct xgbe_prv_data * pdata)1035 static void xgbe_free_irqs(struct xgbe_prv_data *pdata)
1036 {
1037 struct xgbe_channel *channel;
1038 unsigned int i;
1039
1040 devm_free_irq(pdata->dev, pdata->dev_irq, pdata);
1041
1042 cancel_work_sync(&pdata->dev_bh_work);
1043 cancel_work_sync(&pdata->ecc_bh_work);
1044
1045 if (pdata->vdata->ecc_support && (pdata->dev_irq != pdata->ecc_irq))
1046 devm_free_irq(pdata->dev, pdata->ecc_irq, pdata);
1047
1048 if (!pdata->per_channel_irq)
1049 return;
1050
1051 for (i = 0; i < pdata->channel_count; i++) {
1052 channel = pdata->channel[i];
1053
1054 irq_set_affinity_hint(channel->dma_irq, NULL);
1055 devm_free_irq(pdata->dev, channel->dma_irq, channel);
1056 }
1057 }
1058
xgbe_init_tx_coalesce(struct xgbe_prv_data * pdata)1059 void xgbe_init_tx_coalesce(struct xgbe_prv_data *pdata)
1060 {
1061 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1062
1063 DBGPR("-->xgbe_init_tx_coalesce\n");
1064
1065 pdata->tx_usecs = XGMAC_INIT_DMA_TX_USECS;
1066 pdata->tx_frames = XGMAC_INIT_DMA_TX_FRAMES;
1067
1068 hw_if->config_tx_coalesce(pdata);
1069
1070 DBGPR("<--xgbe_init_tx_coalesce\n");
1071 }
1072
xgbe_init_rx_coalesce(struct xgbe_prv_data * pdata)1073 void xgbe_init_rx_coalesce(struct xgbe_prv_data *pdata)
1074 {
1075 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1076
1077 DBGPR("-->xgbe_init_rx_coalesce\n");
1078
1079 pdata->rx_riwt = hw_if->usec_to_riwt(pdata, XGMAC_INIT_DMA_RX_USECS);
1080 pdata->rx_usecs = XGMAC_INIT_DMA_RX_USECS;
1081 pdata->rx_frames = XGMAC_INIT_DMA_RX_FRAMES;
1082
1083 hw_if->config_rx_coalesce(pdata);
1084
1085 DBGPR("<--xgbe_init_rx_coalesce\n");
1086 }
1087
xgbe_free_tx_data(struct xgbe_prv_data * pdata)1088 static void xgbe_free_tx_data(struct xgbe_prv_data *pdata)
1089 {
1090 struct xgbe_desc_if *desc_if = &pdata->desc_if;
1091 struct xgbe_ring *ring;
1092 struct xgbe_ring_data *rdata;
1093 unsigned int i, j;
1094
1095 DBGPR("-->xgbe_free_tx_data\n");
1096
1097 for (i = 0; i < pdata->channel_count; i++) {
1098 ring = pdata->channel[i]->tx_ring;
1099 if (!ring)
1100 break;
1101
1102 for (j = 0; j < ring->rdesc_count; j++) {
1103 rdata = XGBE_GET_DESC_DATA(ring, j);
1104 desc_if->unmap_rdata(pdata, rdata);
1105 }
1106 }
1107
1108 DBGPR("<--xgbe_free_tx_data\n");
1109 }
1110
xgbe_free_rx_data(struct xgbe_prv_data * pdata)1111 static void xgbe_free_rx_data(struct xgbe_prv_data *pdata)
1112 {
1113 struct xgbe_desc_if *desc_if = &pdata->desc_if;
1114 struct xgbe_ring *ring;
1115 struct xgbe_ring_data *rdata;
1116 unsigned int i, j;
1117
1118 DBGPR("-->xgbe_free_rx_data\n");
1119
1120 for (i = 0; i < pdata->channel_count; i++) {
1121 ring = pdata->channel[i]->rx_ring;
1122 if (!ring)
1123 break;
1124
1125 for (j = 0; j < ring->rdesc_count; j++) {
1126 rdata = XGBE_GET_DESC_DATA(ring, j);
1127 desc_if->unmap_rdata(pdata, rdata);
1128 }
1129 }
1130
1131 DBGPR("<--xgbe_free_rx_data\n");
1132 }
1133
xgbe_phy_reset(struct xgbe_prv_data * pdata)1134 static int xgbe_phy_reset(struct xgbe_prv_data *pdata)
1135 {
1136 pdata->phy_speed = SPEED_UNKNOWN;
1137
1138 return pdata->phy_if.phy_reset(pdata);
1139 }
1140
xgbe_powerdown(struct net_device * netdev)1141 int xgbe_powerdown(struct net_device *netdev)
1142 {
1143 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1144 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1145
1146 if (!netif_running(netdev)) {
1147 netdev_dbg(netdev, "Device is not running, skipping powerdown\n");
1148 return -EINVAL;
1149 }
1150
1151 if (pdata->power_down) {
1152 netdev_dbg(netdev, "Device is already powered down\n");
1153 return -EINVAL;
1154 }
1155
1156 netif_device_detach(netdev);
1157 netif_tx_stop_all_queues(netdev);
1158
1159 xgbe_stop_timers(pdata);
1160 flush_workqueue(pdata->dev_workqueue);
1161
1162 xgbe_napi_disable(pdata, 0);
1163
1164 hw_if->powerdown_tx(pdata);
1165 hw_if->powerdown_rx(pdata);
1166
1167 pdata->power_down = 1;
1168
1169 return 0;
1170 }
1171
xgbe_powerup(struct net_device * netdev)1172 int xgbe_powerup(struct net_device *netdev)
1173 {
1174 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1175 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1176
1177 if (!netif_running(netdev)) {
1178 netdev_dbg(netdev, "Device is not running, skipping powerup\n");
1179 return -EINVAL;
1180 }
1181
1182 if (!pdata->power_down) {
1183 netdev_dbg(netdev, "Device is already powered up\n");
1184 return -EINVAL;
1185 }
1186
1187 hw_if->powerup_tx(pdata);
1188 hw_if->powerup_rx(pdata);
1189
1190 xgbe_napi_enable(pdata, 0);
1191
1192 netif_tx_start_all_queues(netdev);
1193 xgbe_start_timers(pdata);
1194 netif_device_attach(netdev);
1195
1196 pdata->power_down = 0;
1197
1198 return 0;
1199 }
1200
xgbe_free_memory(struct xgbe_prv_data * pdata)1201 static void xgbe_free_memory(struct xgbe_prv_data *pdata)
1202 {
1203 struct xgbe_desc_if *desc_if = &pdata->desc_if;
1204
1205 /* Free the ring descriptors and buffers */
1206 desc_if->free_ring_resources(pdata);
1207
1208 /* Free the channel and ring structures */
1209 xgbe_free_channels(pdata);
1210 }
1211
xgbe_alloc_memory(struct xgbe_prv_data * pdata)1212 static int xgbe_alloc_memory(struct xgbe_prv_data *pdata)
1213 {
1214 struct xgbe_desc_if *desc_if = &pdata->desc_if;
1215 struct net_device *netdev = pdata->netdev;
1216 int ret;
1217
1218 if (pdata->new_tx_ring_count) {
1219 pdata->tx_ring_count = pdata->new_tx_ring_count;
1220 pdata->tx_q_count = pdata->tx_ring_count;
1221 pdata->new_tx_ring_count = 0;
1222 }
1223
1224 if (pdata->new_rx_ring_count) {
1225 pdata->rx_ring_count = pdata->new_rx_ring_count;
1226 pdata->new_rx_ring_count = 0;
1227 }
1228
1229 /* Calculate the Rx buffer size before allocating rings */
1230 pdata->rx_buf_size = xgbe_calc_rx_buf_size(netdev, netdev->mtu);
1231
1232 /* Allocate the channel and ring structures */
1233 ret = xgbe_alloc_channels(pdata);
1234 if (ret)
1235 return ret;
1236
1237 /* Allocate the ring descriptors and buffers */
1238 ret = desc_if->alloc_ring_resources(pdata);
1239 if (ret)
1240 goto err_channels;
1241
1242 /* Initialize the service and Tx timers */
1243 xgbe_init_timers(pdata);
1244
1245 return 0;
1246
1247 err_channels:
1248 xgbe_free_memory(pdata);
1249
1250 return ret;
1251 }
1252
xgbe_start(struct xgbe_prv_data * pdata)1253 static int xgbe_start(struct xgbe_prv_data *pdata)
1254 {
1255 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1256 struct xgbe_phy_if *phy_if = &pdata->phy_if;
1257 struct net_device *netdev = pdata->netdev;
1258 unsigned int i;
1259 int ret;
1260
1261 /* Set the number of queues */
1262 ret = netif_set_real_num_tx_queues(netdev, pdata->tx_ring_count);
1263 if (ret) {
1264 netdev_err(netdev, "error setting real tx queue count\n");
1265 return ret;
1266 }
1267
1268 ret = netif_set_real_num_rx_queues(netdev, pdata->rx_ring_count);
1269 if (ret) {
1270 netdev_err(netdev, "error setting real rx queue count\n");
1271 return ret;
1272 }
1273
1274 /* Set RSS lookup table data for programming */
1275 for (i = 0; i < XGBE_RSS_MAX_TABLE_SIZE; i++)
1276 XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH,
1277 i % pdata->rx_ring_count);
1278
1279 ret = hw_if->init(pdata);
1280 if (ret)
1281 return ret;
1282
1283 xgbe_napi_enable(pdata, 1);
1284
1285 ret = xgbe_request_irqs(pdata);
1286 if (ret)
1287 goto err_napi;
1288
1289 /* Reset the phy settings */
1290 ret = xgbe_phy_reset(pdata);
1291 if (ret)
1292 goto err_irqs;
1293
1294 /* Start the phy */
1295 ret = phy_if->phy_start(pdata);
1296 if (ret)
1297 goto err_irqs;
1298
1299 hw_if->enable_tx(pdata);
1300 hw_if->enable_rx(pdata);
1301 /* Synchronize flag with hardware state after enabling TX/RX.
1302 * This prevents stale state after device restart cycles.
1303 */
1304 pdata->data_path_stopped = false;
1305
1306 udp_tunnel_nic_reset_ntf(netdev);
1307
1308 netif_tx_start_all_queues(netdev);
1309
1310 xgbe_start_timers(pdata);
1311 queue_work(pdata->dev_workqueue, &pdata->service_work);
1312
1313 clear_bit(XGBE_STOPPED, &pdata->dev_state);
1314
1315 return 0;
1316
1317 err_irqs:
1318 xgbe_free_irqs(pdata);
1319
1320 err_napi:
1321 xgbe_napi_disable(pdata, 1);
1322
1323 hw_if->exit(pdata);
1324
1325 return ret;
1326 }
1327
xgbe_stop(struct xgbe_prv_data * pdata)1328 static void xgbe_stop(struct xgbe_prv_data *pdata)
1329 {
1330 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1331 struct xgbe_phy_if *phy_if = &pdata->phy_if;
1332 struct xgbe_channel *channel;
1333 struct net_device *netdev = pdata->netdev;
1334 struct netdev_queue *txq;
1335 unsigned int i;
1336
1337 DBGPR("-->xgbe_stop\n");
1338
1339 if (test_bit(XGBE_STOPPED, &pdata->dev_state))
1340 return;
1341
1342 netif_tx_stop_all_queues(netdev);
1343 netif_carrier_off(pdata->netdev);
1344
1345 xgbe_stop_timers(pdata);
1346 flush_workqueue(pdata->dev_workqueue);
1347
1348 xgbe_vxlan_unset_port(netdev, 0, 0, NULL);
1349
1350 hw_if->disable_tx(pdata);
1351 hw_if->disable_rx(pdata);
1352
1353 phy_if->phy_stop(pdata);
1354
1355 xgbe_free_irqs(pdata);
1356
1357 xgbe_napi_disable(pdata, 1);
1358
1359 hw_if->exit(pdata);
1360
1361 for (i = 0; i < pdata->channel_count; i++) {
1362 channel = pdata->channel[i];
1363 if (!channel->tx_ring)
1364 continue;
1365
1366 txq = netdev_get_tx_queue(netdev, channel->queue_index);
1367 netdev_tx_reset_queue(txq);
1368 }
1369
1370 set_bit(XGBE_STOPPED, &pdata->dev_state);
1371
1372 DBGPR("<--xgbe_stop\n");
1373 }
1374
xgbe_stopdev(struct work_struct * work)1375 static void xgbe_stopdev(struct work_struct *work)
1376 {
1377 struct xgbe_prv_data *pdata = container_of(work,
1378 struct xgbe_prv_data,
1379 stopdev_work);
1380
1381 rtnl_lock();
1382
1383 xgbe_stop(pdata);
1384
1385 xgbe_free_tx_data(pdata);
1386 xgbe_free_rx_data(pdata);
1387
1388 rtnl_unlock();
1389
1390 netdev_alert(pdata->netdev, "device stopped\n");
1391 }
1392
xgbe_full_restart_dev(struct xgbe_prv_data * pdata)1393 void xgbe_full_restart_dev(struct xgbe_prv_data *pdata)
1394 {
1395 /* If not running, "restart" will happen on open */
1396 if (!netif_running(pdata->netdev))
1397 return;
1398
1399 xgbe_stop(pdata);
1400
1401 xgbe_free_memory(pdata);
1402 xgbe_alloc_memory(pdata);
1403
1404 xgbe_start(pdata);
1405 }
1406
xgbe_restart_dev(struct xgbe_prv_data * pdata)1407 void xgbe_restart_dev(struct xgbe_prv_data *pdata)
1408 {
1409 /* If not running, "restart" will happen on open */
1410 if (!netif_running(pdata->netdev))
1411 return;
1412
1413 xgbe_stop(pdata);
1414
1415 xgbe_free_tx_data(pdata);
1416 xgbe_free_rx_data(pdata);
1417
1418 xgbe_start(pdata);
1419 }
1420
xgbe_restart(struct work_struct * work)1421 static void xgbe_restart(struct work_struct *work)
1422 {
1423 struct xgbe_prv_data *pdata = container_of(work,
1424 struct xgbe_prv_data,
1425 restart_work);
1426
1427 rtnl_lock();
1428
1429 xgbe_restart_dev(pdata);
1430
1431 rtnl_unlock();
1432 }
1433
xgbe_prep_vlan(struct sk_buff * skb,struct xgbe_packet_data * packet)1434 static void xgbe_prep_vlan(struct sk_buff *skb, struct xgbe_packet_data *packet)
1435 {
1436 if (skb_vlan_tag_present(skb))
1437 packet->vlan_ctag = skb_vlan_tag_get(skb);
1438 }
1439
xgbe_prep_tso(struct sk_buff * skb,struct xgbe_packet_data * packet)1440 static int xgbe_prep_tso(struct sk_buff *skb, struct xgbe_packet_data *packet)
1441 {
1442 int ret;
1443
1444 if (!XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1445 TSO_ENABLE))
1446 return 0;
1447
1448 ret = skb_cow_head(skb, 0);
1449 if (ret)
1450 return ret;
1451
1452 if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, VXLAN)) {
1453 packet->header_len = skb_inner_tcp_all_headers(skb);
1454 packet->tcp_header_len = inner_tcp_hdrlen(skb);
1455 } else {
1456 packet->header_len = skb_tcp_all_headers(skb);
1457 packet->tcp_header_len = tcp_hdrlen(skb);
1458 }
1459 packet->tcp_payload_len = skb->len - packet->header_len;
1460 packet->mss = skb_shinfo(skb)->gso_size;
1461
1462 DBGPR(" packet->header_len=%u\n", packet->header_len);
1463 DBGPR(" packet->tcp_header_len=%u, packet->tcp_payload_len=%u\n",
1464 packet->tcp_header_len, packet->tcp_payload_len);
1465 DBGPR(" packet->mss=%u\n", packet->mss);
1466
1467 /* Update the number of packets that will ultimately be transmitted
1468 * along with the extra bytes for each extra packet
1469 */
1470 packet->tx_packets = skb_shinfo(skb)->gso_segs;
1471 packet->tx_bytes += (packet->tx_packets - 1) * packet->header_len;
1472
1473 return 0;
1474 }
1475
xgbe_is_vxlan(struct sk_buff * skb)1476 static bool xgbe_is_vxlan(struct sk_buff *skb)
1477 {
1478 if (!skb->encapsulation)
1479 return false;
1480
1481 if (skb->ip_summed != CHECKSUM_PARTIAL)
1482 return false;
1483
1484 switch (skb->protocol) {
1485 case htons(ETH_P_IP):
1486 if (ip_hdr(skb)->protocol != IPPROTO_UDP)
1487 return false;
1488 break;
1489
1490 case htons(ETH_P_IPV6):
1491 if (ipv6_hdr(skb)->nexthdr != IPPROTO_UDP)
1492 return false;
1493 break;
1494
1495 default:
1496 return false;
1497 }
1498
1499 if (skb->inner_protocol_type != ENCAP_TYPE_ETHER ||
1500 skb->inner_protocol != htons(ETH_P_TEB) ||
1501 (skb_inner_mac_header(skb) - skb_transport_header(skb) !=
1502 sizeof(struct udphdr) + sizeof(struct vxlanhdr)))
1503 return false;
1504
1505 return true;
1506 }
1507
xgbe_is_tso(struct sk_buff * skb)1508 static int xgbe_is_tso(struct sk_buff *skb)
1509 {
1510 if (skb->ip_summed != CHECKSUM_PARTIAL)
1511 return 0;
1512
1513 if (!skb_is_gso(skb))
1514 return 0;
1515
1516 DBGPR(" TSO packet to be processed\n");
1517
1518 return 1;
1519 }
1520
xgbe_packet_info(struct xgbe_prv_data * pdata,struct xgbe_ring * ring,struct sk_buff * skb,struct xgbe_packet_data * packet)1521 static void xgbe_packet_info(struct xgbe_prv_data *pdata,
1522 struct xgbe_ring *ring, struct sk_buff *skb,
1523 struct xgbe_packet_data *packet)
1524 {
1525 skb_frag_t *frag;
1526 unsigned int context_desc;
1527 unsigned int len;
1528 unsigned int i;
1529
1530 packet->skb = skb;
1531
1532 context_desc = 0;
1533 packet->rdesc_count = 0;
1534
1535 packet->tx_packets = 1;
1536 packet->tx_bytes = skb->len;
1537
1538 if (xgbe_is_tso(skb)) {
1539 /* TSO requires an extra descriptor if mss is different */
1540 if (skb_shinfo(skb)->gso_size != ring->tx.cur_mss) {
1541 context_desc = 1;
1542 packet->rdesc_count++;
1543 }
1544
1545 /* TSO requires an extra descriptor for TSO header */
1546 packet->rdesc_count++;
1547
1548 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1549 TSO_ENABLE, 1);
1550 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1551 CSUM_ENABLE, 1);
1552 } else if (skb->ip_summed == CHECKSUM_PARTIAL)
1553 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1554 CSUM_ENABLE, 1);
1555
1556 if (xgbe_is_vxlan(skb))
1557 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1558 VXLAN, 1);
1559
1560 if (skb_vlan_tag_present(skb)) {
1561 /* VLAN requires an extra descriptor if tag is different */
1562 if (skb_vlan_tag_get(skb) != ring->tx.cur_vlan_ctag)
1563 /* We can share with the TSO context descriptor */
1564 if (!context_desc) {
1565 context_desc = 1;
1566 packet->rdesc_count++;
1567 }
1568
1569 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1570 VLAN_CTAG, 1);
1571 }
1572
1573 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1574 (pdata->tstamp_config.tx_type == HWTSTAMP_TX_ON))
1575 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1576 PTP, 1);
1577
1578 for (len = skb_headlen(skb); len;) {
1579 packet->rdesc_count++;
1580 len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE);
1581 }
1582
1583 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1584 frag = &skb_shinfo(skb)->frags[i];
1585 for (len = skb_frag_size(frag); len; ) {
1586 packet->rdesc_count++;
1587 len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE);
1588 }
1589 }
1590 }
1591
xgbe_open(struct net_device * netdev)1592 static int xgbe_open(struct net_device *netdev)
1593 {
1594 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1595 int ret;
1596
1597 /* Create the various names based on netdev name */
1598 snprintf(pdata->an_name, sizeof(pdata->an_name) - 1, "%s-pcs",
1599 netdev_name(netdev));
1600
1601 snprintf(pdata->ecc_name, sizeof(pdata->ecc_name) - 1, "%s-ecc",
1602 netdev_name(netdev));
1603
1604 snprintf(pdata->i2c_name, sizeof(pdata->i2c_name) - 1, "%s-i2c",
1605 netdev_name(netdev));
1606
1607 /* Create workqueues */
1608 pdata->dev_workqueue =
1609 create_singlethread_workqueue(netdev_name(netdev));
1610 if (!pdata->dev_workqueue) {
1611 netdev_err(netdev, "device workqueue creation failed\n");
1612 return -ENOMEM;
1613 }
1614
1615 pdata->an_workqueue =
1616 create_singlethread_workqueue(pdata->an_name);
1617 if (!pdata->an_workqueue) {
1618 netdev_err(netdev, "phy workqueue creation failed\n");
1619 ret = -ENOMEM;
1620 goto err_dev_wq;
1621 }
1622
1623 /* Enable the clocks */
1624 ret = clk_prepare_enable(pdata->sysclk);
1625 if (ret) {
1626 netdev_alert(netdev, "dma clk_prepare_enable failed\n");
1627 goto err_an_wq;
1628 }
1629
1630 ret = clk_prepare_enable(pdata->ptpclk);
1631 if (ret) {
1632 netdev_alert(netdev, "ptp clk_prepare_enable failed\n");
1633 goto err_sysclk;
1634 }
1635
1636 INIT_WORK(&pdata->service_work, xgbe_service);
1637 INIT_WORK(&pdata->restart_work, xgbe_restart);
1638 INIT_WORK(&pdata->stopdev_work, xgbe_stopdev);
1639 INIT_WORK(&pdata->tx_tstamp_work, xgbe_tx_tstamp);
1640
1641 /* Initialize PTP timestamping and clock. */
1642 xgbe_init_ptp(pdata);
1643
1644 ret = xgbe_alloc_memory(pdata);
1645 if (ret)
1646 goto err_ptpclk;
1647
1648 ret = xgbe_start(pdata);
1649 if (ret)
1650 goto err_mem;
1651
1652 clear_bit(XGBE_DOWN, &pdata->dev_state);
1653
1654 return 0;
1655
1656 err_mem:
1657 xgbe_free_memory(pdata);
1658
1659 err_ptpclk:
1660 clk_disable_unprepare(pdata->ptpclk);
1661
1662 err_sysclk:
1663 clk_disable_unprepare(pdata->sysclk);
1664
1665 err_an_wq:
1666 destroy_workqueue(pdata->an_workqueue);
1667
1668 err_dev_wq:
1669 destroy_workqueue(pdata->dev_workqueue);
1670
1671 return ret;
1672 }
1673
xgbe_close(struct net_device * netdev)1674 static int xgbe_close(struct net_device *netdev)
1675 {
1676 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1677
1678 /* Stop the device */
1679 xgbe_stop(pdata);
1680
1681 xgbe_free_memory(pdata);
1682
1683 /* Disable the clocks */
1684 clk_disable_unprepare(pdata->ptpclk);
1685 clk_disable_unprepare(pdata->sysclk);
1686
1687 destroy_workqueue(pdata->an_workqueue);
1688
1689 destroy_workqueue(pdata->dev_workqueue);
1690
1691 set_bit(XGBE_DOWN, &pdata->dev_state);
1692
1693 return 0;
1694 }
1695
xgbe_xmit(struct sk_buff * skb,struct net_device * netdev)1696 static netdev_tx_t xgbe_xmit(struct sk_buff *skb, struct net_device *netdev)
1697 {
1698 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1699 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1700 struct xgbe_desc_if *desc_if = &pdata->desc_if;
1701 struct xgbe_channel *channel;
1702 struct xgbe_ring *ring;
1703 struct xgbe_packet_data *packet;
1704 struct netdev_queue *txq;
1705 netdev_tx_t ret;
1706
1707 DBGPR("-->xgbe_xmit: skb->len = %d\n", skb->len);
1708
1709 channel = pdata->channel[skb->queue_mapping];
1710 txq = netdev_get_tx_queue(netdev, channel->queue_index);
1711 ring = channel->tx_ring;
1712 packet = &ring->packet_data;
1713
1714 ret = NETDEV_TX_OK;
1715
1716 if (skb->len == 0) {
1717 netif_err(pdata, tx_err, netdev,
1718 "empty skb received from stack\n");
1719 dev_kfree_skb_any(skb);
1720 goto tx_netdev_return;
1721 }
1722
1723 /* Calculate preliminary packet info */
1724 memset(packet, 0, sizeof(*packet));
1725 xgbe_packet_info(pdata, ring, skb, packet);
1726
1727 /* Check that there are enough descriptors available */
1728 ret = xgbe_maybe_stop_tx_queue(channel, ring, packet->rdesc_count);
1729 if (ret)
1730 goto tx_netdev_return;
1731
1732 ret = xgbe_prep_tso(skb, packet);
1733 if (ret) {
1734 netif_err(pdata, tx_err, netdev,
1735 "error processing TSO packet\n");
1736 dev_kfree_skb_any(skb);
1737 goto tx_netdev_return;
1738 }
1739 xgbe_prep_vlan(skb, packet);
1740
1741 if (!desc_if->map_tx_skb(channel, skb)) {
1742 dev_kfree_skb_any(skb);
1743 goto tx_netdev_return;
1744 }
1745
1746 xgbe_prep_tx_tstamp(pdata, skb, packet);
1747
1748 /* Report on the actual number of bytes (to be) sent */
1749 netdev_tx_sent_queue(txq, packet->tx_bytes);
1750
1751 /* Configure required descriptor fields for transmission */
1752 hw_if->dev_xmit(channel);
1753
1754 if (netif_msg_pktdata(pdata))
1755 xgbe_print_pkt(netdev, skb, true);
1756
1757 /* Stop the queue in advance if there may not be enough descriptors */
1758 xgbe_maybe_stop_tx_queue(channel, ring, XGBE_TX_MAX_DESCS);
1759
1760 ret = NETDEV_TX_OK;
1761
1762 tx_netdev_return:
1763 return ret;
1764 }
1765
xgbe_set_rx_mode(struct net_device * netdev)1766 static void xgbe_set_rx_mode(struct net_device *netdev)
1767 {
1768 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1769 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1770
1771 DBGPR("-->xgbe_set_rx_mode\n");
1772
1773 hw_if->config_rx_mode(pdata);
1774
1775 DBGPR("<--xgbe_set_rx_mode\n");
1776 }
1777
xgbe_set_mac_address(struct net_device * netdev,void * addr)1778 static int xgbe_set_mac_address(struct net_device *netdev, void *addr)
1779 {
1780 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1781 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1782 struct sockaddr *saddr = addr;
1783
1784 DBGPR("-->xgbe_set_mac_address\n");
1785
1786 if (!is_valid_ether_addr(saddr->sa_data))
1787 return -EADDRNOTAVAIL;
1788
1789 eth_hw_addr_set(netdev, saddr->sa_data);
1790
1791 hw_if->set_mac_address(pdata, netdev->dev_addr);
1792
1793 DBGPR("<--xgbe_set_mac_address\n");
1794
1795 return 0;
1796 }
1797
xgbe_change_mtu(struct net_device * netdev,int mtu)1798 static int xgbe_change_mtu(struct net_device *netdev, int mtu)
1799 {
1800 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1801 int ret;
1802
1803 DBGPR("-->xgbe_change_mtu\n");
1804
1805 ret = xgbe_calc_rx_buf_size(netdev, mtu);
1806 if (ret < 0)
1807 return ret;
1808
1809 pdata->rx_buf_size = ret;
1810 WRITE_ONCE(netdev->mtu, mtu);
1811
1812 xgbe_restart_dev(pdata);
1813
1814 DBGPR("<--xgbe_change_mtu\n");
1815
1816 return 0;
1817 }
1818
xgbe_tx_timeout(struct net_device * netdev,unsigned int txqueue)1819 static void xgbe_tx_timeout(struct net_device *netdev, unsigned int txqueue)
1820 {
1821 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1822
1823 netdev_warn(netdev, "tx timeout, device restarting\n");
1824 schedule_work(&pdata->restart_work);
1825 }
1826
xgbe_get_stats64(struct net_device * netdev,struct rtnl_link_stats64 * s)1827 static void xgbe_get_stats64(struct net_device *netdev,
1828 struct rtnl_link_stats64 *s)
1829 {
1830 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1831 struct xgbe_mmc_stats *pstats = &pdata->mmc_stats;
1832
1833 DBGPR("-->%s\n", __func__);
1834
1835 pdata->hw_if.read_mmc_stats(pdata);
1836
1837 s->rx_packets = pstats->rxframecount_gb;
1838 s->rx_bytes = pstats->rxoctetcount_gb;
1839 s->rx_errors = pstats->rxframecount_gb -
1840 pstats->rxbroadcastframes_g -
1841 pstats->rxmulticastframes_g -
1842 pstats->rxunicastframes_g;
1843 s->multicast = pstats->rxmulticastframes_g;
1844 s->rx_length_errors = pstats->rxlengtherror;
1845 s->rx_crc_errors = pstats->rxcrcerror;
1846 s->rx_over_errors = pstats->rxfifooverflow;
1847 s->rx_frame_errors = pstats->rxalignmenterror;
1848
1849 s->tx_packets = pstats->txframecount_gb;
1850 s->tx_bytes = pstats->txoctetcount_gb;
1851 s->tx_errors = pstats->txframecount_gb - pstats->txframecount_g;
1852 s->tx_dropped = netdev->stats.tx_dropped;
1853
1854 DBGPR("<--%s\n", __func__);
1855 }
1856
xgbe_vlan_rx_add_vid(struct net_device * netdev,__be16 proto,u16 vid)1857 static int xgbe_vlan_rx_add_vid(struct net_device *netdev, __be16 proto,
1858 u16 vid)
1859 {
1860 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1861 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1862
1863 DBGPR("-->%s\n", __func__);
1864
1865 set_bit(vid, pdata->active_vlans);
1866 hw_if->update_vlan_hash_table(pdata);
1867
1868 DBGPR("<--%s\n", __func__);
1869
1870 return 0;
1871 }
1872
xgbe_vlan_rx_kill_vid(struct net_device * netdev,__be16 proto,u16 vid)1873 static int xgbe_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto,
1874 u16 vid)
1875 {
1876 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1877 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1878
1879 DBGPR("-->%s\n", __func__);
1880
1881 clear_bit(vid, pdata->active_vlans);
1882 hw_if->update_vlan_hash_table(pdata);
1883
1884 DBGPR("<--%s\n", __func__);
1885
1886 return 0;
1887 }
1888
1889 #ifdef CONFIG_NET_POLL_CONTROLLER
xgbe_poll_controller(struct net_device * netdev)1890 static void xgbe_poll_controller(struct net_device *netdev)
1891 {
1892 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1893 struct xgbe_channel *channel;
1894 unsigned int i;
1895
1896 DBGPR("-->xgbe_poll_controller\n");
1897
1898 if (pdata->per_channel_irq) {
1899 for (i = 0; i < pdata->channel_count; i++) {
1900 channel = pdata->channel[i];
1901 xgbe_dma_isr(channel->dma_irq, channel);
1902 }
1903 } else {
1904 disable_irq(pdata->dev_irq);
1905 xgbe_isr(pdata->dev_irq, pdata);
1906 enable_irq(pdata->dev_irq);
1907 }
1908
1909 DBGPR("<--xgbe_poll_controller\n");
1910 }
1911 #endif /* End CONFIG_NET_POLL_CONTROLLER */
1912
xgbe_setup_tc(struct net_device * netdev,enum tc_setup_type type,void * type_data)1913 static int xgbe_setup_tc(struct net_device *netdev, enum tc_setup_type type,
1914 void *type_data)
1915 {
1916 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1917 struct tc_mqprio_qopt *mqprio = type_data;
1918 u8 tc;
1919
1920 if (type != TC_SETUP_QDISC_MQPRIO)
1921 return -EOPNOTSUPP;
1922
1923 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
1924 tc = mqprio->num_tc;
1925
1926 if (tc > pdata->hw_feat.tc_cnt)
1927 return -EINVAL;
1928
1929 pdata->num_tcs = tc;
1930 pdata->hw_if.config_tc(pdata);
1931
1932 return 0;
1933 }
1934
xgbe_fix_features(struct net_device * netdev,netdev_features_t features)1935 static netdev_features_t xgbe_fix_features(struct net_device *netdev,
1936 netdev_features_t features)
1937 {
1938 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1939 netdev_features_t vxlan_base;
1940
1941 vxlan_base = NETIF_F_GSO_UDP_TUNNEL | NETIF_F_RX_UDP_TUNNEL_PORT;
1942
1943 if (!pdata->hw_feat.vxn)
1944 return features;
1945
1946 /* VXLAN CSUM requires VXLAN base */
1947 if ((features & NETIF_F_GSO_UDP_TUNNEL_CSUM) &&
1948 !(features & NETIF_F_GSO_UDP_TUNNEL)) {
1949 netdev_notice(netdev,
1950 "forcing tx udp tunnel support\n");
1951 features |= NETIF_F_GSO_UDP_TUNNEL;
1952 }
1953
1954 /* Can't do one without doing the other */
1955 if ((features & vxlan_base) != vxlan_base) {
1956 netdev_notice(netdev,
1957 "forcing both tx and rx udp tunnel support\n");
1958 features |= vxlan_base;
1959 }
1960
1961 if (features & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)) {
1962 if (!(features & NETIF_F_GSO_UDP_TUNNEL_CSUM)) {
1963 netdev_notice(netdev,
1964 "forcing tx udp tunnel checksumming on\n");
1965 features |= NETIF_F_GSO_UDP_TUNNEL_CSUM;
1966 }
1967 } else {
1968 if (features & NETIF_F_GSO_UDP_TUNNEL_CSUM) {
1969 netdev_notice(netdev,
1970 "forcing tx udp tunnel checksumming off\n");
1971 features &= ~NETIF_F_GSO_UDP_TUNNEL_CSUM;
1972 }
1973 }
1974
1975 return features;
1976 }
1977
xgbe_set_features(struct net_device * netdev,netdev_features_t features)1978 static int xgbe_set_features(struct net_device *netdev,
1979 netdev_features_t features)
1980 {
1981 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1982 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1983 netdev_features_t rxhash, rxcsum, rxvlan, rxvlan_filter;
1984 int ret = 0;
1985
1986 rxhash = pdata->netdev_features & NETIF_F_RXHASH;
1987 rxcsum = pdata->netdev_features & NETIF_F_RXCSUM;
1988 rxvlan = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_RX;
1989 rxvlan_filter = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_FILTER;
1990
1991 if ((features & NETIF_F_RXHASH) && !rxhash)
1992 ret = hw_if->enable_rss(pdata);
1993 else if (!(features & NETIF_F_RXHASH) && rxhash)
1994 ret = hw_if->disable_rss(pdata);
1995 if (ret)
1996 return ret;
1997
1998 if ((features & NETIF_F_RXCSUM) && !rxcsum) {
1999 hw_if->enable_sph(pdata);
2000 hw_if->enable_vxlan(pdata);
2001 hw_if->enable_rx_csum(pdata);
2002 schedule_work(&pdata->restart_work);
2003 } else if (!(features & NETIF_F_RXCSUM) && rxcsum) {
2004 hw_if->disable_sph(pdata);
2005 hw_if->disable_vxlan(pdata);
2006 hw_if->disable_rx_csum(pdata);
2007 schedule_work(&pdata->restart_work);
2008 }
2009
2010 if ((features & NETIF_F_HW_VLAN_CTAG_RX) && !rxvlan)
2011 hw_if->enable_rx_vlan_stripping(pdata);
2012 else if (!(features & NETIF_F_HW_VLAN_CTAG_RX) && rxvlan)
2013 hw_if->disable_rx_vlan_stripping(pdata);
2014
2015 if ((features & NETIF_F_HW_VLAN_CTAG_FILTER) && !rxvlan_filter)
2016 hw_if->enable_rx_vlan_filtering(pdata);
2017 else if (!(features & NETIF_F_HW_VLAN_CTAG_FILTER) && rxvlan_filter)
2018 hw_if->disable_rx_vlan_filtering(pdata);
2019
2020 pdata->netdev_features = features;
2021
2022 DBGPR("<--xgbe_set_features\n");
2023
2024 return 0;
2025 }
2026
xgbe_features_check(struct sk_buff * skb,struct net_device * netdev,netdev_features_t features)2027 static netdev_features_t xgbe_features_check(struct sk_buff *skb,
2028 struct net_device *netdev,
2029 netdev_features_t features)
2030 {
2031 features = vlan_features_check(skb, features);
2032 features = vxlan_features_check(skb, features);
2033
2034 return features;
2035 }
2036
2037 static const struct net_device_ops xgbe_netdev_ops = {
2038 .ndo_open = xgbe_open,
2039 .ndo_stop = xgbe_close,
2040 .ndo_start_xmit = xgbe_xmit,
2041 .ndo_set_rx_mode = xgbe_set_rx_mode,
2042 .ndo_set_mac_address = xgbe_set_mac_address,
2043 .ndo_validate_addr = eth_validate_addr,
2044 .ndo_change_mtu = xgbe_change_mtu,
2045 .ndo_tx_timeout = xgbe_tx_timeout,
2046 .ndo_get_stats64 = xgbe_get_stats64,
2047 .ndo_vlan_rx_add_vid = xgbe_vlan_rx_add_vid,
2048 .ndo_vlan_rx_kill_vid = xgbe_vlan_rx_kill_vid,
2049 #ifdef CONFIG_NET_POLL_CONTROLLER
2050 .ndo_poll_controller = xgbe_poll_controller,
2051 #endif
2052 .ndo_setup_tc = xgbe_setup_tc,
2053 .ndo_fix_features = xgbe_fix_features,
2054 .ndo_set_features = xgbe_set_features,
2055 .ndo_features_check = xgbe_features_check,
2056 .ndo_hwtstamp_get = xgbe_get_hwtstamp_settings,
2057 .ndo_hwtstamp_set = xgbe_set_hwtstamp_settings,
2058 };
2059
xgbe_get_netdev_ops(void)2060 const struct net_device_ops *xgbe_get_netdev_ops(void)
2061 {
2062 return &xgbe_netdev_ops;
2063 }
2064
xgbe_rx_refresh(struct xgbe_channel * channel)2065 static void xgbe_rx_refresh(struct xgbe_channel *channel)
2066 {
2067 struct xgbe_prv_data *pdata = channel->pdata;
2068 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2069 struct xgbe_desc_if *desc_if = &pdata->desc_if;
2070 struct xgbe_ring *ring = channel->rx_ring;
2071 struct xgbe_ring_data *rdata;
2072
2073 while (ring->dirty != ring->cur) {
2074 rdata = XGBE_GET_DESC_DATA(ring, ring->dirty);
2075
2076 /* Reset rdata values */
2077 desc_if->unmap_rdata(pdata, rdata);
2078
2079 if (desc_if->map_rx_buffer(pdata, ring, rdata))
2080 break;
2081
2082 hw_if->rx_desc_reset(pdata, rdata, ring->dirty);
2083
2084 ring->dirty++;
2085 }
2086
2087 /* Make sure everything is written before the register write */
2088 wmb();
2089
2090 /* Update the Rx Tail Pointer Register with address of
2091 * the last cleaned entry */
2092 rdata = XGBE_GET_DESC_DATA(ring, ring->dirty - 1);
2093 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO,
2094 lower_32_bits(rdata->rdesc_dma));
2095 }
2096
xgbe_create_skb(struct xgbe_prv_data * pdata,struct napi_struct * napi,struct xgbe_ring_data * rdata,unsigned int len)2097 static struct sk_buff *xgbe_create_skb(struct xgbe_prv_data *pdata,
2098 struct napi_struct *napi,
2099 struct xgbe_ring_data *rdata,
2100 unsigned int len)
2101 {
2102 struct sk_buff *skb;
2103 u8 *packet;
2104
2105 skb = napi_alloc_skb(napi, rdata->rx.hdr.dma_len);
2106 if (!skb)
2107 return NULL;
2108
2109 /* Pull in the header buffer which may contain just the header
2110 * or the header plus data
2111 */
2112 dma_sync_single_range_for_cpu(pdata->dev, rdata->rx.hdr.dma_base,
2113 rdata->rx.hdr.dma_off,
2114 rdata->rx.hdr.dma_len, DMA_FROM_DEVICE);
2115
2116 packet = page_address(rdata->rx.hdr.pa.pages) +
2117 rdata->rx.hdr.pa.pages_offset;
2118 skb_copy_to_linear_data(skb, packet, len);
2119 skb_put(skb, len);
2120
2121 return skb;
2122 }
2123
xgbe_rx_buf1_len(struct xgbe_ring_data * rdata,struct xgbe_packet_data * packet)2124 static unsigned int xgbe_rx_buf1_len(struct xgbe_ring_data *rdata,
2125 struct xgbe_packet_data *packet)
2126 {
2127 /* Always zero if not the first descriptor */
2128 if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, FIRST))
2129 return 0;
2130
2131 /* First descriptor with split header, return header length */
2132 if (rdata->rx.hdr_len)
2133 return rdata->rx.hdr_len;
2134
2135 /* First descriptor but not the last descriptor and no split header,
2136 * so the full buffer was used
2137 */
2138 if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, LAST))
2139 return rdata->rx.hdr.dma_len;
2140
2141 /* First descriptor and last descriptor and no split header, so
2142 * calculate how much of the buffer was used
2143 */
2144 return min_t(unsigned int, rdata->rx.hdr.dma_len, rdata->rx.len);
2145 }
2146
xgbe_rx_buf2_len(struct xgbe_ring_data * rdata,struct xgbe_packet_data * packet,unsigned int len)2147 static unsigned int xgbe_rx_buf2_len(struct xgbe_ring_data *rdata,
2148 struct xgbe_packet_data *packet,
2149 unsigned int len)
2150 {
2151 /* Always the full buffer if not the last descriptor */
2152 if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, LAST))
2153 return rdata->rx.buf.dma_len;
2154
2155 /* Last descriptor so calculate how much of the buffer was used
2156 * for the last bit of data
2157 */
2158 return rdata->rx.len - len;
2159 }
2160
xgbe_tx_poll(struct xgbe_channel * channel)2161 static int xgbe_tx_poll(struct xgbe_channel *channel)
2162 {
2163 struct xgbe_prv_data *pdata = channel->pdata;
2164 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2165 struct xgbe_desc_if *desc_if = &pdata->desc_if;
2166 struct xgbe_ring *ring = channel->tx_ring;
2167 struct xgbe_ring_data *rdata;
2168 struct xgbe_ring_desc *rdesc;
2169 struct net_device *netdev = pdata->netdev;
2170 struct netdev_queue *txq;
2171 int processed = 0;
2172 int force_cleanup;
2173 unsigned int tx_packets = 0, tx_bytes = 0;
2174 unsigned int cur;
2175
2176 DBGPR("-->xgbe_tx_poll\n");
2177
2178 /* Nothing to do if there isn't a Tx ring for this channel */
2179 if (!ring)
2180 return 0;
2181
2182 cur = ring->cur;
2183
2184 /* Be sure we get ring->cur before accessing descriptor data */
2185 smp_rmb();
2186
2187 txq = netdev_get_tx_queue(netdev, channel->queue_index);
2188
2189 /* Smart descriptor cleanup during link-down conditions.
2190 *
2191 * When link is down, hardware stops processing TX descriptors (OWN bit
2192 * remains set). Enable intelligent cleanup to reclaim these abandoned
2193 * descriptors and maintain TX queue health.
2194 *
2195 * This cleanup mechanism enables:
2196 * - Continuous TX queue availability for new packets when link recovers
2197 * - Clean resource management (skbs, DMA mappings, descriptors)
2198 * - Fast failover in link aggregation scenarios
2199 */
2200 force_cleanup = !pdata->phy.link;
2201
2202 while ((processed < XGBE_TX_DESC_MAX_PROC) &&
2203 (ring->dirty != cur)) {
2204 rdata = XGBE_GET_DESC_DATA(ring, ring->dirty);
2205 rdesc = rdata->rdesc;
2206
2207 if (!hw_if->tx_complete(rdesc)) {
2208 if (!force_cleanup)
2209 break;
2210 /* Link-down descriptor cleanup: reclaim abandoned
2211 * resources.
2212 *
2213 * Hardware has stopped processing this descriptor, so
2214 * perform intelligent cleanup to free skbs and reclaim
2215 * descriptors for future use when link recovers.
2216 *
2217 * These are not counted as successful transmissions
2218 * since packets never reached the wire.
2219 */
2220 netif_dbg(pdata, tx_err, netdev,
2221 "force-freeing stuck TX desc %u (link down)\n",
2222 ring->dirty);
2223 }
2224
2225 /* Make sure descriptor fields are read after reading the OWN
2226 * bit */
2227 dma_rmb();
2228
2229 if (netif_msg_tx_done(pdata))
2230 xgbe_dump_tx_desc(pdata, ring, ring->dirty, 1, 0);
2231
2232 /* Only count packets actually transmitted (not force-cleaned)
2233 */
2234 if (!force_cleanup || hw_if->is_last_desc(rdesc)) {
2235 if (hw_if->is_last_desc(rdesc)) {
2236 tx_packets += rdata->tx.packets;
2237 tx_bytes += rdata->tx.bytes;
2238 }
2239 }
2240
2241 /* Free the SKB and reset the descriptor for re-use */
2242 desc_if->unmap_rdata(pdata, rdata);
2243 hw_if->tx_desc_reset(rdata);
2244
2245 processed++;
2246 ring->dirty++;
2247 }
2248
2249 if (!processed)
2250 return 0;
2251
2252 netdev_tx_completed_queue(txq, tx_packets, tx_bytes);
2253
2254 if ((ring->tx.queue_stopped == 1) &&
2255 (xgbe_tx_avail_desc(ring) > XGBE_TX_DESC_MIN_FREE)) {
2256 ring->tx.queue_stopped = 0;
2257 netif_tx_wake_queue(txq);
2258 }
2259
2260 DBGPR("<--xgbe_tx_poll: processed=%d\n", processed);
2261
2262 return processed;
2263 }
2264
xgbe_rx_poll(struct xgbe_channel * channel,int budget)2265 static int xgbe_rx_poll(struct xgbe_channel *channel, int budget)
2266 {
2267 struct xgbe_prv_data *pdata = channel->pdata;
2268 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2269 struct xgbe_ring *ring = channel->rx_ring;
2270 struct xgbe_ring_data *rdata;
2271 struct xgbe_packet_data *packet;
2272 struct net_device *netdev = pdata->netdev;
2273 struct napi_struct *napi;
2274 struct sk_buff *skb;
2275 struct skb_shared_hwtstamps *hwtstamps;
2276 unsigned int last, error, context_next, context;
2277 unsigned int len, buf1_len, buf2_len, max_len;
2278 unsigned int received = 0;
2279 int packet_count = 0;
2280
2281 DBGPR("-->xgbe_rx_poll: budget=%d\n", budget);
2282
2283 /* Nothing to do if there isn't a Rx ring for this channel */
2284 if (!ring)
2285 return 0;
2286
2287 last = 0;
2288 context_next = 0;
2289
2290 napi = (pdata->per_channel_irq) ? &channel->napi : &pdata->napi;
2291
2292 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
2293 packet = &ring->packet_data;
2294 while (packet_count < budget) {
2295 DBGPR(" cur = %d\n", ring->cur);
2296
2297 /* First time in loop see if we need to restore state */
2298 if (!received && rdata->state_saved) {
2299 skb = rdata->state.skb;
2300 error = rdata->state.error;
2301 len = rdata->state.len;
2302 } else {
2303 memset(packet, 0, sizeof(*packet));
2304 skb = NULL;
2305 error = 0;
2306 len = 0;
2307 }
2308
2309 read_again:
2310 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
2311
2312 if (xgbe_rx_dirty_desc(ring) > (XGBE_RX_DESC_CNT >> 3))
2313 xgbe_rx_refresh(channel);
2314
2315 if (hw_if->dev_read(channel))
2316 break;
2317
2318 received++;
2319 ring->cur++;
2320
2321 last = XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
2322 LAST);
2323 context_next = XGMAC_GET_BITS(packet->attributes,
2324 RX_PACKET_ATTRIBUTES,
2325 CONTEXT_NEXT);
2326 context = XGMAC_GET_BITS(packet->attributes,
2327 RX_PACKET_ATTRIBUTES,
2328 CONTEXT);
2329
2330 /* Earlier error, just drain the remaining data */
2331 if ((!last || context_next) && error)
2332 goto read_again;
2333
2334 if (error || packet->errors) {
2335 dev_kfree_skb(skb);
2336 goto next_packet;
2337 }
2338
2339 if (!context) {
2340 /* Get the data length in the descriptor buffers */
2341 buf1_len = xgbe_rx_buf1_len(rdata, packet);
2342 len += buf1_len;
2343 buf2_len = xgbe_rx_buf2_len(rdata, packet, len);
2344 len += buf2_len;
2345
2346 if (buf2_len > rdata->rx.buf.dma_len) {
2347 /* Hardware inconsistency within the descriptors
2348 * that has resulted in a length underflow.
2349 */
2350 error = 1;
2351 goto skip_data;
2352 }
2353
2354 if (!skb) {
2355 skb = xgbe_create_skb(pdata, napi, rdata,
2356 buf1_len);
2357 if (!skb) {
2358 error = 1;
2359 goto skip_data;
2360 }
2361 }
2362
2363 if (buf2_len) {
2364 dma_sync_single_range_for_cpu(pdata->dev,
2365 rdata->rx.buf.dma_base,
2366 rdata->rx.buf.dma_off,
2367 rdata->rx.buf.dma_len,
2368 DMA_FROM_DEVICE);
2369
2370 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
2371 rdata->rx.buf.pa.pages,
2372 rdata->rx.buf.pa.pages_offset,
2373 buf2_len,
2374 rdata->rx.buf.dma_len);
2375 rdata->rx.buf.pa.pages = NULL;
2376 }
2377 }
2378
2379 skip_data:
2380 if (!last || context_next)
2381 goto read_again;
2382
2383 if (!skb || error) {
2384 dev_kfree_skb(skb);
2385 goto next_packet;
2386 }
2387
2388 /* Be sure we don't exceed the configured MTU */
2389 max_len = netdev->mtu + ETH_HLEN;
2390 if (!(netdev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
2391 (skb->protocol == htons(ETH_P_8021Q)))
2392 max_len += VLAN_HLEN;
2393
2394 if (skb->len > max_len) {
2395 netif_err(pdata, rx_err, netdev,
2396 "packet length exceeds configured MTU\n");
2397 dev_kfree_skb(skb);
2398 goto next_packet;
2399 }
2400
2401 if (netif_msg_pktdata(pdata))
2402 xgbe_print_pkt(netdev, skb, false);
2403
2404 skb_checksum_none_assert(skb);
2405 if (XGMAC_GET_BITS(packet->attributes,
2406 RX_PACKET_ATTRIBUTES, CSUM_DONE))
2407 skb->ip_summed = CHECKSUM_UNNECESSARY;
2408
2409 if (XGMAC_GET_BITS(packet->attributes,
2410 RX_PACKET_ATTRIBUTES, TNP)) {
2411 skb->encapsulation = 1;
2412
2413 if (XGMAC_GET_BITS(packet->attributes,
2414 RX_PACKET_ATTRIBUTES, TNPCSUM_DONE))
2415 skb->csum_level = 1;
2416 }
2417
2418 if (XGMAC_GET_BITS(packet->attributes,
2419 RX_PACKET_ATTRIBUTES, VLAN_CTAG))
2420 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
2421 packet->vlan_ctag);
2422
2423 if (XGMAC_GET_BITS(packet->attributes,
2424 RX_PACKET_ATTRIBUTES, RX_TSTAMP)) {
2425 hwtstamps = skb_hwtstamps(skb);
2426 hwtstamps->hwtstamp = ns_to_ktime(packet->rx_tstamp);
2427 }
2428
2429 if (XGMAC_GET_BITS(packet->attributes,
2430 RX_PACKET_ATTRIBUTES, RSS_HASH))
2431 skb_set_hash(skb, packet->rss_hash,
2432 packet->rss_hash_type);
2433
2434 skb->dev = netdev;
2435 skb->protocol = eth_type_trans(skb, netdev);
2436 skb_record_rx_queue(skb, channel->queue_index);
2437
2438 napi_gro_receive(napi, skb);
2439
2440 next_packet:
2441 packet_count++;
2442 }
2443
2444 /* Check if we need to save state before leaving */
2445 if (received && (!last || context_next)) {
2446 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
2447 rdata->state_saved = 1;
2448 rdata->state.skb = skb;
2449 rdata->state.len = len;
2450 rdata->state.error = error;
2451 }
2452
2453 DBGPR("<--xgbe_rx_poll: packet_count = %d\n", packet_count);
2454
2455 return packet_count;
2456 }
2457
xgbe_one_poll(struct napi_struct * napi,int budget)2458 static int xgbe_one_poll(struct napi_struct *napi, int budget)
2459 {
2460 struct xgbe_channel *channel = container_of(napi, struct xgbe_channel,
2461 napi);
2462 struct xgbe_prv_data *pdata = channel->pdata;
2463 int processed = 0;
2464
2465 DBGPR("-->xgbe_one_poll: budget=%d\n", budget);
2466
2467 /* Cleanup Tx ring first */
2468 xgbe_tx_poll(channel);
2469
2470 /* Process Rx ring next */
2471 processed = xgbe_rx_poll(channel, budget);
2472
2473 /* If we processed everything, we are done */
2474 if ((processed < budget) && napi_complete_done(napi, processed)) {
2475 /* Enable Tx and Rx interrupts */
2476 if (pdata->channel_irq_mode)
2477 xgbe_enable_rx_tx_int(pdata, channel);
2478 else
2479 enable_irq(channel->dma_irq);
2480 }
2481
2482 DBGPR("<--xgbe_one_poll: received = %d\n", processed);
2483
2484 return processed;
2485 }
2486
xgbe_all_poll(struct napi_struct * napi,int budget)2487 static int xgbe_all_poll(struct napi_struct *napi, int budget)
2488 {
2489 struct xgbe_prv_data *pdata = container_of(napi, struct xgbe_prv_data,
2490 napi);
2491 struct xgbe_channel *channel;
2492 int ring_budget;
2493 int processed, last_processed;
2494 unsigned int i;
2495
2496 DBGPR("-->xgbe_all_poll: budget=%d\n", budget);
2497
2498 processed = 0;
2499 ring_budget = budget / pdata->rx_ring_count;
2500 do {
2501 last_processed = processed;
2502
2503 for (i = 0; i < pdata->channel_count; i++) {
2504 channel = pdata->channel[i];
2505
2506 /* Cleanup Tx ring first */
2507 xgbe_tx_poll(channel);
2508
2509 /* Process Rx ring next */
2510 if (ring_budget > (budget - processed))
2511 ring_budget = budget - processed;
2512 processed += xgbe_rx_poll(channel, ring_budget);
2513 }
2514 } while ((processed < budget) && (processed != last_processed));
2515
2516 /* If we processed everything, we are done */
2517 if ((processed < budget) && napi_complete_done(napi, processed)) {
2518 /* Enable Tx and Rx interrupts */
2519 xgbe_enable_rx_tx_ints(pdata);
2520 }
2521
2522 DBGPR("<--xgbe_all_poll: received = %d\n", processed);
2523
2524 return processed;
2525 }
2526
xgbe_dump_tx_desc(struct xgbe_prv_data * pdata,struct xgbe_ring * ring,unsigned int idx,unsigned int count,unsigned int flag)2527 void xgbe_dump_tx_desc(struct xgbe_prv_data *pdata, struct xgbe_ring *ring,
2528 unsigned int idx, unsigned int count, unsigned int flag)
2529 {
2530 struct xgbe_ring_data *rdata;
2531 struct xgbe_ring_desc *rdesc;
2532
2533 while (count--) {
2534 rdata = XGBE_GET_DESC_DATA(ring, idx);
2535 rdesc = rdata->rdesc;
2536 netdev_dbg(pdata->netdev,
2537 "TX_NORMAL_DESC[%d %s] = %08x:%08x:%08x:%08x\n", idx,
2538 (flag == 1) ? "QUEUED FOR TX" : "TX BY DEVICE",
2539 le32_to_cpu(rdesc->desc0),
2540 le32_to_cpu(rdesc->desc1),
2541 le32_to_cpu(rdesc->desc2),
2542 le32_to_cpu(rdesc->desc3));
2543 idx++;
2544 }
2545 }
2546
xgbe_dump_rx_desc(struct xgbe_prv_data * pdata,struct xgbe_ring * ring,unsigned int idx)2547 void xgbe_dump_rx_desc(struct xgbe_prv_data *pdata, struct xgbe_ring *ring,
2548 unsigned int idx)
2549 {
2550 struct xgbe_ring_data *rdata;
2551 struct xgbe_ring_desc *rdesc;
2552
2553 rdata = XGBE_GET_DESC_DATA(ring, idx);
2554 rdesc = rdata->rdesc;
2555 netdev_dbg(pdata->netdev,
2556 "RX_NORMAL_DESC[%d RX BY DEVICE] = %08x:%08x:%08x:%08x\n",
2557 idx, le32_to_cpu(rdesc->desc0), le32_to_cpu(rdesc->desc1),
2558 le32_to_cpu(rdesc->desc2), le32_to_cpu(rdesc->desc3));
2559 }
2560
xgbe_print_pkt(struct net_device * netdev,struct sk_buff * skb,bool tx_rx)2561 void xgbe_print_pkt(struct net_device *netdev, struct sk_buff *skb, bool tx_rx)
2562 {
2563 struct ethhdr *eth = (struct ethhdr *)skb->data;
2564 unsigned char buffer[128];
2565 unsigned int i;
2566
2567 netdev_dbg(netdev, "\n************** SKB dump ****************\n");
2568
2569 netdev_dbg(netdev, "%s packet of %d bytes\n",
2570 (tx_rx ? "TX" : "RX"), skb->len);
2571
2572 netdev_dbg(netdev, "Dst MAC addr: %pM\n", eth->h_dest);
2573 netdev_dbg(netdev, "Src MAC addr: %pM\n", eth->h_source);
2574 netdev_dbg(netdev, "Protocol: %#06x\n", ntohs(eth->h_proto));
2575
2576 for (i = 0; i < skb->len; i += 32) {
2577 unsigned int len = min(skb->len - i, 32U);
2578
2579 hex_dump_to_buffer(&skb->data[i], len, 32, 1,
2580 buffer, sizeof(buffer), false);
2581 netdev_dbg(netdev, " %#06x: %s\n", i, buffer);
2582 }
2583
2584 netdev_dbg(netdev, "\n************** SKB dump ****************\n");
2585 }
2586