1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2022 Intel Corporation
4 */
5
6 #include "xe_wa.h"
7
8 #include <drm/drm_managed.h>
9 #include <kunit/visibility.h>
10 #include <linux/compiler_types.h>
11 #include <linux/fault-inject.h>
12
13 #include <generated/xe_device_wa_oob.h>
14 #include <generated/xe_wa_oob.h>
15
16 #include "regs/xe_engine_regs.h"
17 #include "regs/xe_gt_regs.h"
18 #include "regs/xe_regs.h"
19 #include "xe_device_types.h"
20 #include "xe_force_wake.h"
21 #include "xe_gt.h"
22 #include "xe_hw_engine_types.h"
23 #include "xe_mmio.h"
24 #include "xe_platform_types.h"
25 #include "xe_rtp.h"
26 #include "xe_sriov.h"
27 #include "xe_step.h"
28
29 /**
30 * DOC: Hardware workarounds
31 *
32 * Hardware workarounds are register programming documented to be executed in
33 * the driver that fall outside of the normal programming sequences for a
34 * platform. There are some basic categories of workarounds, depending on
35 * how/when they are applied:
36 *
37 * - LRC workarounds: workarounds that touch registers that are
38 * saved/restored to/from the HW context image. The list is emitted (via Load
39 * Register Immediate commands) once when initializing the device and saved in
40 * the default context. That default context is then used on every context
41 * creation to have a "primed golden context", i.e. a context image that
42 * already contains the changes needed to all the registers.
43 *
44 * - Engine workarounds: the list of these WAs is applied whenever the specific
45 * engine is reset. It's also possible that a set of engine classes share a
46 * common power domain and they are reset together. This happens on some
47 * platforms with render and compute engines. In this case (at least) one of
48 * them need to keeep the workaround programming: the approach taken in the
49 * driver is to tie those workarounds to the first compute/render engine that
50 * is registered. When executing with GuC submission, engine resets are
51 * outside of kernel driver control, hence the list of registers involved in
52 * written once, on engine initialization, and then passed to GuC, that
53 * saves/restores their values before/after the reset takes place. See
54 * ``drivers/gpu/drm/xe/xe_guc_ads.c`` for reference.
55 *
56 * - GT workarounds: the list of these WAs is applied whenever these registers
57 * revert to their default values: on GPU reset, suspend/resume [1]_, etc.
58 *
59 * - Register whitelist: some workarounds need to be implemented in userspace,
60 * but need to touch privileged registers. The whitelist in the kernel
61 * instructs the hardware to allow the access to happen. From the kernel side,
62 * this is just a special case of a MMIO workaround (as we write the list of
63 * these to/be-whitelisted registers to some special HW registers).
64 *
65 * - Workaround batchbuffers: buffers that get executed automatically by the
66 * hardware on every HW context restore. These buffers are created and
67 * programmed in the default context so the hardware always go through those
68 * programming sequences when switching contexts. The support for workaround
69 * batchbuffers is enabled these hardware mechanisms:
70 *
71 * #. INDIRECT_CTX: A batchbuffer and an offset are provided in the default
72 * context, pointing the hardware to jump to that location when that offset
73 * is reached in the context restore. Workaround batchbuffer in the driver
74 * currently uses this mechanism for all platforms.
75 *
76 * #. BB_PER_CTX_PTR: A batchbuffer is provided in the default context,
77 * pointing the hardware to a buffer to continue executing after the
78 * engine registers are restored in a context restore sequence. This is
79 * currently not used in the driver.
80 *
81 * - Other/OOB: There are WAs that, due to their nature, cannot be applied from
82 * a central place. Those are peppered around the rest of the code, as needed.
83 * Workarounds related to the display IP are the main example.
84 *
85 * .. [1] Technically, some registers are powercontext saved & restored, so they
86 * survive a suspend/resume. In practice, writing them again is not too
87 * costly and simplifies things, so it's the approach taken in the driver.
88 *
89 * .. note::
90 * Hardware workarounds in xe work the same way as in i915, with the
91 * difference of how they are maintained in the code. In xe it uses the
92 * xe_rtp infrastructure so the workarounds can be kept in tables, following
93 * a more declarative approach rather than procedural.
94 */
95
96 #undef XE_REG_MCR
97 #define XE_REG_MCR(...) XE_REG(__VA_ARGS__, .mcr = 1)
98
99 __diag_push();
100 __diag_ignore_all("-Woverride-init", "Allow field overrides in table");
101
102 static const struct xe_rtp_entry_sr gt_was[] = {
103 { XE_RTP_NAME("14011060649"),
104 XE_RTP_RULES(MEDIA_VERSION_RANGE(1200, 1255),
105 ENGINE_CLASS(VIDEO_DECODE),
106 FUNC(xe_rtp_match_even_instance)),
107 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)),
108 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
109 },
110 { XE_RTP_NAME("14011059788"),
111 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),
112 XE_RTP_ACTIONS(SET(DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE))
113 },
114 { XE_RTP_NAME("14015795083"),
115 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1260)),
116 XE_RTP_ACTIONS(CLR(MISCCPCTL, DOP_CLOCK_GATE_RENDER_ENABLE))
117 },
118
119 /* DG1 */
120
121 { XE_RTP_NAME("1409420604"),
122 XE_RTP_RULES(PLATFORM(DG1)),
123 XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE2, CPSSUNIT_CLKGATE_DIS))
124 },
125 { XE_RTP_NAME("1408615072"),
126 XE_RTP_RULES(PLATFORM(DG1)),
127 XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE2, VSUNIT_CLKGATE2_DIS))
128 },
129
130 /* DG2 */
131
132 { XE_RTP_NAME("22010523718"),
133 XE_RTP_RULES(SUBPLATFORM(DG2, G10)),
134 XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE, CG3DDISCFEG_CLKGATE_DIS))
135 },
136 { XE_RTP_NAME("14011006942"),
137 XE_RTP_RULES(SUBPLATFORM(DG2, G10)),
138 XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE, DSS_ROUTER_CLKGATE_DIS))
139 },
140 { XE_RTP_NAME("14014830051"),
141 XE_RTP_RULES(PLATFORM(DG2)),
142 XE_RTP_ACTIONS(CLR(SARB_CHICKEN1, COMP_CKN_IN))
143 },
144 { XE_RTP_NAME("18018781329"),
145 XE_RTP_RULES(PLATFORM(DG2)),
146 XE_RTP_ACTIONS(SET(RENDER_MOD_CTRL, FORCE_MISS_FTLB),
147 SET(COMP_MOD_CTRL, FORCE_MISS_FTLB),
148 SET(XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB),
149 SET(XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB))
150 },
151 { XE_RTP_NAME("1509235366"),
152 XE_RTP_RULES(PLATFORM(DG2)),
153 XE_RTP_ACTIONS(SET(XEHP_GAMCNTRL_CTRL,
154 INVALIDATION_BROADCAST_MODE_DIS |
155 GLOBAL_INVALIDATION_MODE))
156 },
157
158 /* PVC */
159
160 { XE_RTP_NAME("18018781329"),
161 XE_RTP_RULES(PLATFORM(PVC)),
162 XE_RTP_ACTIONS(SET(RENDER_MOD_CTRL, FORCE_MISS_FTLB),
163 SET(COMP_MOD_CTRL, FORCE_MISS_FTLB),
164 SET(XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB),
165 SET(XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB))
166 },
167 { XE_RTP_NAME("16016694945"),
168 XE_RTP_RULES(PLATFORM(PVC)),
169 XE_RTP_ACTIONS(SET(XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC))
170 },
171
172 /* Xe_LPG */
173
174 { XE_RTP_NAME("14015795083"),
175 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271), GRAPHICS_STEP(A0, B0)),
176 XE_RTP_ACTIONS(CLR(MISCCPCTL, DOP_CLOCK_GATE_RENDER_ENABLE))
177 },
178 { XE_RTP_NAME("14018575942"),
179 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)),
180 XE_RTP_ACTIONS(SET(COMP_MOD_CTRL, FORCE_MISS_FTLB))
181 },
182 { XE_RTP_NAME("22016670082"),
183 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)),
184 XE_RTP_ACTIONS(SET(SQCNT1, ENFORCE_RAR))
185 },
186
187 /* Xe_LPM+ */
188
189 { XE_RTP_NAME("16021867713"),
190 XE_RTP_RULES(MEDIA_VERSION(1300),
191 ENGINE_CLASS(VIDEO_DECODE)),
192 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),
193 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
194 },
195 { XE_RTP_NAME("22016670082"),
196 XE_RTP_RULES(MEDIA_VERSION(1300)),
197 XE_RTP_ACTIONS(SET(XELPMP_SQCNT1, ENFORCE_RAR))
198 },
199
200 /* Xe2_LPG */
201
202 { XE_RTP_NAME("16020975621"),
203 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0)),
204 XE_RTP_ACTIONS(SET(XEHP_SLICE_UNIT_LEVEL_CLKGATE, SBEUNIT_CLKGATE_DIS))
205 },
206 { XE_RTP_NAME("14018157293"),
207 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0)),
208 XE_RTP_ACTIONS(SET(XEHPC_L3CLOS_MASK(0), ~0),
209 SET(XEHPC_L3CLOS_MASK(1), ~0),
210 SET(XEHPC_L3CLOS_MASK(2), ~0),
211 SET(XEHPC_L3CLOS_MASK(3), ~0))
212 },
213
214 /* Xe2_LPM */
215
216 { XE_RTP_NAME("14017421178"),
217 XE_RTP_RULES(MEDIA_VERSION(2000),
218 ENGINE_CLASS(VIDEO_DECODE)),
219 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)),
220 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
221 },
222 { XE_RTP_NAME("16021867713"),
223 XE_RTP_RULES(MEDIA_VERSION(2000),
224 ENGINE_CLASS(VIDEO_DECODE)),
225 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),
226 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
227 },
228 { XE_RTP_NAME("14019449301"),
229 XE_RTP_RULES(MEDIA_VERSION(2000), ENGINE_CLASS(VIDEO_DECODE)),
230 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)),
231 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
232 },
233
234 /* Xe2_HPG */
235
236 { XE_RTP_NAME("16025250150"),
237 XE_RTP_RULES(GRAPHICS_VERSION(2001)),
238 XE_RTP_ACTIONS(SET(LSN_VC_REG2,
239 LSN_LNI_WGT(1) |
240 LSN_LNE_WGT(1) |
241 LSN_DIM_X_WGT(1) |
242 LSN_DIM_Y_WGT(1) |
243 LSN_DIM_Z_WGT(1)))
244 },
245
246 /* Xe2_HPM */
247
248 { XE_RTP_NAME("16021867713"),
249 XE_RTP_RULES(MEDIA_VERSION(1301),
250 ENGINE_CLASS(VIDEO_DECODE)),
251 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),
252 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
253 },
254 { XE_RTP_NAME("14020316580"),
255 XE_RTP_RULES(MEDIA_VERSION(1301)),
256 XE_RTP_ACTIONS(CLR(POWERGATE_ENABLE,
257 VDN_HCP_POWERGATE_ENABLE(0) |
258 VDN_MFXVDENC_POWERGATE_ENABLE(0) |
259 VDN_HCP_POWERGATE_ENABLE(2) |
260 VDN_MFXVDENC_POWERGATE_ENABLE(2))),
261 },
262 { XE_RTP_NAME("14019449301"),
263 XE_RTP_RULES(MEDIA_VERSION(1301), ENGINE_CLASS(VIDEO_DECODE)),
264 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)),
265 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
266 },
267
268 /* Xe3_LPG */
269
270 { XE_RTP_NAME("14021871409"),
271 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0)),
272 XE_RTP_ACTIONS(SET(UNSLCGCTL9454, LSCFE_CLKGATE_DIS))
273 },
274
275 /* Xe3_LPM */
276
277 { XE_RTP_NAME("16021867713"),
278 XE_RTP_RULES(MEDIA_VERSION(3000),
279 ENGINE_CLASS(VIDEO_DECODE)),
280 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),
281 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
282 },
283 { XE_RTP_NAME("16021865536"),
284 XE_RTP_RULES(MEDIA_VERSION(3000),
285 ENGINE_CLASS(VIDEO_DECODE)),
286 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)),
287 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
288 },
289 { XE_RTP_NAME("16021865536"),
290 XE_RTP_RULES(MEDIA_VERSION(3002),
291 ENGINE_CLASS(VIDEO_DECODE)),
292 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)),
293 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
294 },
295 { XE_RTP_NAME("16021867713"),
296 XE_RTP_RULES(MEDIA_VERSION(3002),
297 ENGINE_CLASS(VIDEO_DECODE)),
298 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),
299 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
300 },
301 { XE_RTP_NAME("14021486841"),
302 XE_RTP_RULES(MEDIA_VERSION(3000), MEDIA_STEP(A0, B0),
303 ENGINE_CLASS(VIDEO_DECODE)),
304 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), RAMDFTUNIT_CLKGATE_DIS)),
305 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
306 },
307 };
308
309 static const struct xe_rtp_entry_sr engine_was[] = {
310 { XE_RTP_NAME("22010931296, 18011464164, 14010919138"),
311 XE_RTP_RULES(GRAPHICS_VERSION(1200), ENGINE_CLASS(RENDER)),
312 XE_RTP_ACTIONS(SET(FF_THREAD_MODE(RENDER_RING_BASE),
313 FF_TESSELATION_DOP_GATE_DISABLE))
314 },
315 { XE_RTP_NAME("1409804808"),
316 XE_RTP_RULES(GRAPHICS_VERSION(1200),
317 ENGINE_CLASS(RENDER),
318 IS_INTEGRATED),
319 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, PUSH_CONST_DEREF_HOLD_DIS))
320 },
321 { XE_RTP_NAME("14010229206, 1409085225"),
322 XE_RTP_RULES(GRAPHICS_VERSION(1200),
323 ENGINE_CLASS(RENDER),
324 IS_INTEGRATED),
325 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH))
326 },
327 { XE_RTP_NAME("1606931601"),
328 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
329 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_EARLY_READ))
330 },
331 { XE_RTP_NAME("14010826681, 1606700617, 22010271021, 18019627453"),
332 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1255), ENGINE_CLASS(RENDER)),
333 XE_RTP_ACTIONS(SET(CS_DEBUG_MODE1(RENDER_RING_BASE),
334 FF_DOP_CLOCK_GATE_DISABLE))
335 },
336 { XE_RTP_NAME("1406941453"),
337 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
338 XE_RTP_ACTIONS(SET(SAMPLER_MODE, ENABLE_SMALLPL))
339 },
340 { XE_RTP_NAME("FtrPerCtxtPreemptionGranularityControl"),
341 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1250), ENGINE_CLASS(RENDER)),
342 XE_RTP_ACTIONS(SET(FF_SLICE_CS_CHICKEN1(RENDER_RING_BASE),
343 FFSC_PERCTX_PREEMPT_CTRL))
344 },
345
346 /* TGL */
347
348 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"),
349 XE_RTP_RULES(PLATFORM(TIGERLAKE), ENGINE_CLASS(RENDER)),
350 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),
351 WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
352 RC_SEMA_IDLE_MSG_DISABLE))
353 },
354
355 /* RKL */
356
357 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"),
358 XE_RTP_RULES(PLATFORM(ROCKETLAKE), ENGINE_CLASS(RENDER)),
359 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),
360 WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
361 RC_SEMA_IDLE_MSG_DISABLE))
362 },
363
364 /* ADL-P */
365
366 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"),
367 XE_RTP_RULES(PLATFORM(ALDERLAKE_P), ENGINE_CLASS(RENDER)),
368 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),
369 WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
370 RC_SEMA_IDLE_MSG_DISABLE))
371 },
372
373 /* DG2 */
374
375 { XE_RTP_NAME("22013037850"),
376 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)),
377 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW,
378 DISABLE_128B_EVICTION_COMMAND_UDW))
379 },
380 { XE_RTP_NAME("22014226127"),
381 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)),
382 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE))
383 },
384 { XE_RTP_NAME("18017747507"),
385 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)),
386 XE_RTP_ACTIONS(SET(VFG_PREEMPTION_CHICKEN,
387 POLYGON_TRIFAN_LINELOOP_DISABLE))
388 },
389 { XE_RTP_NAME("22012826095, 22013059131"),
390 XE_RTP_RULES(SUBPLATFORM(DG2, G11),
391 FUNC(xe_rtp_match_first_render_or_compute)),
392 XE_RTP_ACTIONS(FIELD_SET(LSC_CHICKEN_BIT_0_UDW,
393 MAXREQS_PER_BANK,
394 REG_FIELD_PREP(MAXREQS_PER_BANK, 2)))
395 },
396 { XE_RTP_NAME("22013059131"),
397 XE_RTP_RULES(SUBPLATFORM(DG2, G11),
398 FUNC(xe_rtp_match_first_render_or_compute)),
399 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, FORCE_1_SUB_MESSAGE_PER_FRAGMENT))
400 },
401 { XE_RTP_NAME("14015227452"),
402 XE_RTP_RULES(PLATFORM(DG2),
403 FUNC(xe_rtp_match_first_render_or_compute)),
404 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE))
405 },
406 { XE_RTP_NAME("18028616096"),
407 XE_RTP_RULES(PLATFORM(DG2),
408 FUNC(xe_rtp_match_first_render_or_compute)),
409 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3))
410 },
411 { XE_RTP_NAME("22015475538"),
412 XE_RTP_RULES(PLATFORM(DG2),
413 FUNC(xe_rtp_match_first_render_or_compute)),
414 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8))
415 },
416 { XE_RTP_NAME("22012654132"),
417 XE_RTP_RULES(SUBPLATFORM(DG2, G11),
418 FUNC(xe_rtp_match_first_render_or_compute)),
419 XE_RTP_ACTIONS(SET(CACHE_MODE_SS, ENABLE_PREFETCH_INTO_IC,
420 /*
421 * Register can't be read back for verification on
422 * DG2 due to Wa_14012342262
423 */
424 .read_mask = 0))
425 },
426 { XE_RTP_NAME("1509727124"),
427 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
428 XE_RTP_ACTIONS(SET(SAMPLER_MODE, SC_DISABLE_POWER_OPTIMIZATION_EBB))
429 },
430 { XE_RTP_NAME("22012856258"),
431 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
432 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_READ_SUPPRESSION))
433 },
434 { XE_RTP_NAME("22010960976, 14013347512"),
435 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
436 XE_RTP_ACTIONS(CLR(XEHP_HDC_CHICKEN0,
437 LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK))
438 },
439 { XE_RTP_NAME("14015150844"),
440 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)),
441 XE_RTP_ACTIONS(SET(XEHP_HDC_CHICKEN0, DIS_ATOMIC_CHAINING_TYPED_WRITES,
442 XE_RTP_NOCHECK))
443 },
444
445 /* PVC */
446
447 { XE_RTP_NAME("22014226127"),
448 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)),
449 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE))
450 },
451 { XE_RTP_NAME("14015227452"),
452 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)),
453 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE))
454 },
455 { XE_RTP_NAME("18020744125"),
456 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute),
457 ENGINE_CLASS(COMPUTE)),
458 XE_RTP_ACTIONS(SET(RING_HWSTAM(RENDER_RING_BASE), ~0))
459 },
460 { XE_RTP_NAME("14014999345"),
461 XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COMPUTE),
462 GRAPHICS_STEP(B0, C0)),
463 XE_RTP_ACTIONS(SET(CACHE_MODE_SS, DISABLE_ECC))
464 },
465
466 /* Xe_LPG */
467
468 { XE_RTP_NAME("14017856879"),
469 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274),
470 FUNC(xe_rtp_match_first_render_or_compute)),
471 XE_RTP_ACTIONS(SET(ROW_CHICKEN3, DIS_FIX_EOT1_FLUSH))
472 },
473 { XE_RTP_NAME("14015150844"),
474 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271),
475 FUNC(xe_rtp_match_first_render_or_compute)),
476 XE_RTP_ACTIONS(SET(XEHP_HDC_CHICKEN0, DIS_ATOMIC_CHAINING_TYPED_WRITES,
477 XE_RTP_NOCHECK))
478 },
479 { XE_RTP_NAME("14020495402"),
480 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274),
481 FUNC(xe_rtp_match_first_render_or_compute)),
482 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_TDL_SVHS_GATING))
483 },
484
485 /* Xe2_LPG */
486
487 { XE_RTP_NAME("18032247524"),
488 XE_RTP_RULES(GRAPHICS_VERSION(2004),
489 FUNC(xe_rtp_match_first_render_or_compute)),
490 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, SEQUENTIAL_ACCESS_UPGRADE_DISABLE))
491 },
492 { XE_RTP_NAME("16018712365"),
493 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
494 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, XE2_ALLOC_DPA_STARVE_FIX_DIS))
495 },
496 { XE_RTP_NAME("14018957109"),
497 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),
498 FUNC(xe_rtp_match_first_render_or_compute)),
499 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN5, DISABLE_SAMPLE_G_PERFORMANCE))
500 },
501 { XE_RTP_NAME("14020338487"),
502 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
503 XE_RTP_ACTIONS(SET(ROW_CHICKEN3, XE2_EUPEND_CHK_FLUSH_DIS))
504 },
505 { XE_RTP_NAME("18034896535, 16021540221"), /* 16021540221: GRAPHICS_STEP(A0, B0) */
506 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004),
507 FUNC(xe_rtp_match_first_render_or_compute)),
508 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH))
509 },
510 { XE_RTP_NAME("14019322943"),
511 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),
512 FUNC(xe_rtp_match_first_render_or_compute)),
513 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, TGM_WRITE_EOM_FORCE))
514 },
515 { XE_RTP_NAME("14018471104"),
516 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
517 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL))
518 },
519 /*
520 * These two workarounds are the same, just applying to different
521 * engines. Although Wa_18032095049 (for the RCS) isn't required on
522 * all steppings, disabling these reports has no impact for our
523 * driver or the GuC, so we go ahead and treat it the same as
524 * Wa_16021639441 which does apply to all steppings.
525 */
526 { XE_RTP_NAME("18032095049, 16021639441"),
527 XE_RTP_RULES(GRAPHICS_VERSION(2004)),
528 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0),
529 GHWSP_CSB_REPORT_DIS |
530 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS,
531 XE_RTP_ACTION_FLAG(ENGINE_BASE)))
532 },
533 { XE_RTP_NAME("16018610683"),
534 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
535 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, SLM_WMTP_RESTORE))
536 },
537 { XE_RTP_NAME("14021402888"),
538 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
539 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE))
540 },
541
542 /* Xe2_HPG */
543
544 { XE_RTP_NAME("16018712365"),
545 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
546 FUNC(xe_rtp_match_first_render_or_compute)),
547 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, XE2_ALLOC_DPA_STARVE_FIX_DIS))
548 },
549 { XE_RTP_NAME("16018737384"),
550 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED),
551 FUNC(xe_rtp_match_first_render_or_compute)),
552 XE_RTP_ACTIONS(SET(ROW_CHICKEN, EARLY_EOT_DIS))
553 },
554 { XE_RTP_NAME("14019988906"),
555 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
556 FUNC(xe_rtp_match_first_render_or_compute)),
557 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD))
558 },
559 { XE_RTP_NAME("14019877138"),
560 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
561 FUNC(xe_rtp_match_first_render_or_compute)),
562 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
563 },
564 { XE_RTP_NAME("14020338487"),
565 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
566 FUNC(xe_rtp_match_first_render_or_compute)),
567 XE_RTP_ACTIONS(SET(ROW_CHICKEN3, XE2_EUPEND_CHK_FLUSH_DIS))
568 },
569 { XE_RTP_NAME("18032247524"),
570 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
571 FUNC(xe_rtp_match_first_render_or_compute)),
572 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, SEQUENTIAL_ACCESS_UPGRADE_DISABLE))
573 },
574 { XE_RTP_NAME("14018471104"),
575 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
576 FUNC(xe_rtp_match_first_render_or_compute)),
577 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL))
578 },
579 /*
580 * Although this workaround isn't required for the RCS, disabling these
581 * reports has no impact for our driver or the GuC, so we go ahead and
582 * apply this to all engines for simplicity.
583 */
584 { XE_RTP_NAME("16021639441"),
585 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002)),
586 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0),
587 GHWSP_CSB_REPORT_DIS |
588 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS,
589 XE_RTP_ACTION_FLAG(ENGINE_BASE)))
590 },
591 { XE_RTP_NAME("14019811474"),
592 XE_RTP_RULES(GRAPHICS_VERSION(2001),
593 FUNC(xe_rtp_match_first_render_or_compute)),
594 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, WR_REQ_CHAINING_DIS))
595 },
596 { XE_RTP_NAME("14021402888"),
597 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)),
598 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE))
599 },
600 { XE_RTP_NAME("14021821874, 14022954250"),
601 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
602 FUNC(xe_rtp_match_first_render_or_compute)),
603 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, STK_ID_RESTRICT))
604 },
605
606 /* Xe2_LPM */
607
608 { XE_RTP_NAME("16021639441"),
609 XE_RTP_RULES(MEDIA_VERSION(2000)),
610 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0),
611 GHWSP_CSB_REPORT_DIS |
612 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS,
613 XE_RTP_ACTION_FLAG(ENGINE_BASE)))
614 },
615
616 /* Xe2_HPM */
617
618 { XE_RTP_NAME("16021639441"),
619 XE_RTP_RULES(MEDIA_VERSION(1301)),
620 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0),
621 GHWSP_CSB_REPORT_DIS |
622 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS,
623 XE_RTP_ACTION_FLAG(ENGINE_BASE)))
624 },
625
626 /* Xe3_LPG */
627
628 { XE_RTP_NAME("14021402888"),
629 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3001),
630 FUNC(xe_rtp_match_first_render_or_compute)),
631 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE))
632 },
633 { XE_RTP_NAME("18034896535"),
634 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0),
635 FUNC(xe_rtp_match_first_render_or_compute)),
636 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH))
637 },
638 { XE_RTP_NAME("16024792527"),
639 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0),
640 FUNC(xe_rtp_match_first_render_or_compute)),
641 XE_RTP_ACTIONS(FIELD_SET(SAMPLER_MODE, SMP_WAIT_FETCH_MERGING_COUNTER,
642 SMP_FORCE_128B_OVERFETCH))
643 },
644 { XE_RTP_NAME("14023061436"),
645 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3001),
646 FUNC(xe_rtp_match_first_render_or_compute)),
647 XE_RTP_ACTIONS(SET(TDL_CHICKEN, QID_WAIT_FOR_THREAD_NOT_RUN_DISABLE))
648 },
649 { XE_RTP_NAME("13012615864"),
650 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3001),
651 FUNC(xe_rtp_match_first_render_or_compute)),
652 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, RES_CHK_SPR_DIS))
653 },
654 { XE_RTP_NAME("16023105232"),
655 XE_RTP_RULES(MEDIA_VERSION_RANGE(1301, 3000), OR,
656 GRAPHICS_VERSION_RANGE(2001, 3001)),
657 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(0), RC_SEMA_IDLE_MSG_DISABLE,
658 XE_RTP_ACTION_FLAG(ENGINE_BASE)))
659 },
660 { XE_RTP_NAME("14021402888"),
661 XE_RTP_RULES(GRAPHICS_VERSION(3003), FUNC(xe_rtp_match_first_render_or_compute)),
662 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE))
663 },
664 };
665
666 static const struct xe_rtp_entry_sr lrc_was[] = {
667 { XE_RTP_NAME("16011163337"),
668 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
669 /* read verification is ignored due to 1608008084. */
670 XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(FF_MODE2,
671 FF_MODE2_GS_TIMER_MASK,
672 FF_MODE2_GS_TIMER_224))
673 },
674 { XE_RTP_NAME("1604555607"),
675 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
676 /* read verification is ignored due to 1608008084. */
677 XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(FF_MODE2,
678 FF_MODE2_TDS_TIMER_MASK,
679 FF_MODE2_TDS_TIMER_128))
680 },
681 { XE_RTP_NAME("1409342910, 14010698770, 14010443199, 1408979724, 1409178076, 1409207793, 1409217633, 1409252684, 1409347922, 1409142259"),
682 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),
683 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN3,
684 DISABLE_CPS_AWARE_COLOR_PIPE))
685 },
686 { XE_RTP_NAME("WaDisableGPGPUMidThreadPreemption"),
687 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),
688 XE_RTP_ACTIONS(FIELD_SET(CS_CHICKEN1(RENDER_RING_BASE),
689 PREEMPT_GPGPU_LEVEL_MASK,
690 PREEMPT_GPGPU_THREAD_GROUP_LEVEL))
691 },
692 { XE_RTP_NAME("1806527549"),
693 XE_RTP_RULES(GRAPHICS_VERSION(1200)),
694 XE_RTP_ACTIONS(SET(HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE))
695 },
696 { XE_RTP_NAME("1606376872"),
697 XE_RTP_RULES(GRAPHICS_VERSION(1200)),
698 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, DISABLE_TDC_LOAD_BALANCING_CALC))
699 },
700
701 /* DG1 */
702
703 { XE_RTP_NAME("1409044764"),
704 XE_RTP_RULES(PLATFORM(DG1)),
705 XE_RTP_ACTIONS(CLR(COMMON_SLICE_CHICKEN3,
706 DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN))
707 },
708 { XE_RTP_NAME("22010493298"),
709 XE_RTP_RULES(PLATFORM(DG1)),
710 XE_RTP_ACTIONS(SET(HIZ_CHICKEN,
711 DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE))
712 },
713
714 /* DG2 */
715
716 { XE_RTP_NAME("16013271637"),
717 XE_RTP_RULES(PLATFORM(DG2)),
718 XE_RTP_ACTIONS(SET(XEHP_SLICE_COMMON_ECO_CHICKEN1,
719 MSC_MSAA_REODER_BUF_BYPASS_DISABLE))
720 },
721 { XE_RTP_NAME("14014947963"),
722 XE_RTP_RULES(PLATFORM(DG2)),
723 XE_RTP_ACTIONS(FIELD_SET(VF_PREEMPTION,
724 PREEMPTION_VERTEX_COUNT,
725 0x4000))
726 },
727 { XE_RTP_NAME("18018764978"),
728 XE_RTP_RULES(PLATFORM(DG2)),
729 XE_RTP_ACTIONS(SET(XEHP_PSS_MODE2,
730 SCOREBOARD_STALL_FLUSH_CONTROL))
731 },
732 { XE_RTP_NAME("18019271663"),
733 XE_RTP_RULES(PLATFORM(DG2)),
734 XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE))
735 },
736 { XE_RTP_NAME("14019877138"),
737 XE_RTP_RULES(PLATFORM(DG2)),
738 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
739 },
740
741 /* PVC */
742
743 { XE_RTP_NAME("16017236439"),
744 XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COPY),
745 FUNC(xe_rtp_match_even_instance)),
746 XE_RTP_ACTIONS(SET(BCS_SWCTRL(0),
747 BCS_SWCTRL_DISABLE_256B,
748 XE_RTP_ACTION_FLAG(ENGINE_BASE))),
749 },
750
751 /* Xe_LPG */
752
753 { XE_RTP_NAME("18019271663"),
754 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)),
755 XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE))
756 },
757 { XE_RTP_NAME("14019877138"),
758 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274), ENGINE_CLASS(RENDER)),
759 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
760 },
761
762 /* Xe2_LPG */
763
764 { XE_RTP_NAME("16020518922"),
765 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),
766 ENGINE_CLASS(RENDER)),
767 XE_RTP_ACTIONS(SET(FF_MODE,
768 DIS_TE_AUTOSTRIP |
769 DIS_MESH_PARTIAL_AUTOSTRIP |
770 DIS_MESH_AUTOSTRIP),
771 SET(VFLSKPD,
772 DIS_PARTIAL_AUTOSTRIP |
773 DIS_AUTOSTRIP))
774 },
775 { XE_RTP_NAME("14019386621"),
776 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
777 XE_RTP_ACTIONS(SET(VF_SCRATCHPAD, XE2_VFG_TED_CREDIT_INTERFACE_DISABLE))
778 },
779 { XE_RTP_NAME("14019877138"),
780 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
781 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
782 },
783 { XE_RTP_NAME("14020013138"),
784 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),
785 ENGINE_CLASS(RENDER)),
786 XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS))
787 },
788 { XE_RTP_NAME("14019988906"),
789 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
790 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD))
791 },
792 { XE_RTP_NAME("16020183090"),
793 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),
794 ENGINE_CLASS(RENDER)),
795 XE_RTP_ACTIONS(SET(INSTPM(RENDER_RING_BASE), ENABLE_SEMAPHORE_POLL_BIT))
796 },
797 { XE_RTP_NAME("18033852989"),
798 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
799 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN1, DISABLE_BOTTOM_CLIP_RECTANGLE_TEST))
800 },
801 { XE_RTP_NAME("14021567978"),
802 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED),
803 ENGINE_CLASS(RENDER)),
804 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_2, TBIMR_FAST_CLIP))
805 },
806 { XE_RTP_NAME("14020756599"),
807 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER), OR,
808 MEDIA_VERSION_ANY_GT(2000), ENGINE_CLASS(RENDER)),
809 XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS))
810 },
811 { XE_RTP_NAME("14021490052"),
812 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
813 XE_RTP_ACTIONS(SET(FF_MODE,
814 DIS_MESH_PARTIAL_AUTOSTRIP |
815 DIS_MESH_AUTOSTRIP),
816 SET(VFLSKPD,
817 DIS_PARTIAL_AUTOSTRIP |
818 DIS_AUTOSTRIP))
819 },
820 { XE_RTP_NAME("15016589081"),
821 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
822 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_CLIP_NEGATIVE_BOUNDING_BOX))
823 },
824
825 /* Xe2_HPG */
826 { XE_RTP_NAME("15010599737"),
827 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
828 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN))
829 },
830 { XE_RTP_NAME("14019386621"),
831 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)),
832 XE_RTP_ACTIONS(SET(VF_SCRATCHPAD, XE2_VFG_TED_CREDIT_INTERFACE_DISABLE))
833 },
834 { XE_RTP_NAME("14020756599"),
835 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
836 XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS))
837 },
838 { XE_RTP_NAME("14021490052"),
839 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
840 XE_RTP_ACTIONS(SET(FF_MODE,
841 DIS_MESH_PARTIAL_AUTOSTRIP |
842 DIS_MESH_AUTOSTRIP),
843 SET(VFLSKPD,
844 DIS_PARTIAL_AUTOSTRIP |
845 DIS_AUTOSTRIP))
846 },
847 { XE_RTP_NAME("15016589081"),
848 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)),
849 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_CLIP_NEGATIVE_BOUNDING_BOX))
850 },
851 { XE_RTP_NAME("22021007897"),
852 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)),
853 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, SBE_PUSH_CONSTANT_BEHIND_FIX_ENABLE))
854 },
855 { XE_RTP_NAME("18033852989"),
856 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
857 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN1, DISABLE_BOTTOM_CLIP_RECTANGLE_TEST))
858 },
859
860 /* Xe3_LPG */
861 { XE_RTP_NAME("14021490052"),
862 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0),
863 ENGINE_CLASS(RENDER)),
864 XE_RTP_ACTIONS(SET(FF_MODE,
865 DIS_MESH_PARTIAL_AUTOSTRIP |
866 DIS_MESH_AUTOSTRIP),
867 SET(VFLSKPD,
868 DIS_PARTIAL_AUTOSTRIP |
869 DIS_AUTOSTRIP))
870 },
871 };
872
873 static __maybe_unused const struct xe_rtp_entry oob_was[] = {
874 #include <generated/xe_wa_oob.c>
875 {}
876 };
877
878 static_assert(ARRAY_SIZE(oob_was) - 1 == _XE_WA_OOB_COUNT);
879
880 static __maybe_unused const struct xe_rtp_entry device_oob_was[] = {
881 #include <generated/xe_device_wa_oob.c>
882 {}
883 };
884
885 static_assert(ARRAY_SIZE(device_oob_was) - 1 == _XE_DEVICE_WA_OOB_COUNT);
886
887 __diag_pop();
888
889 /**
890 * xe_wa_process_device_oob - process OOB workaround table
891 * @xe: device instance to process workarounds for
892 *
893 * process OOB workaround table for this device, marking in @xe the
894 * workarounds that are active.
895 */
896
xe_wa_process_device_oob(struct xe_device * xe)897 void xe_wa_process_device_oob(struct xe_device *xe)
898 {
899 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(xe);
900
901 xe_rtp_process_ctx_enable_active_tracking(&ctx, xe->wa_active.oob, ARRAY_SIZE(device_oob_was));
902
903 xe->wa_active.oob_initialized = true;
904 xe_rtp_process(&ctx, device_oob_was);
905 }
906
907 /**
908 * xe_wa_process_oob - process OOB workaround table
909 * @gt: GT instance to process workarounds for
910 *
911 * Process OOB workaround table for this platform, marking in @gt the
912 * workarounds that are active.
913 */
xe_wa_process_oob(struct xe_gt * gt)914 void xe_wa_process_oob(struct xe_gt *gt)
915 {
916 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt);
917
918 xe_rtp_process_ctx_enable_active_tracking(&ctx, gt->wa_active.oob,
919 ARRAY_SIZE(oob_was));
920 gt->wa_active.oob_initialized = true;
921 xe_rtp_process(&ctx, oob_was);
922 }
923
924 /**
925 * xe_wa_process_gt - process GT workaround table
926 * @gt: GT instance to process workarounds for
927 *
928 * Process GT workaround table for this platform, saving in @gt all the
929 * workarounds that need to be applied at the GT level.
930 */
xe_wa_process_gt(struct xe_gt * gt)931 void xe_wa_process_gt(struct xe_gt *gt)
932 {
933 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt);
934
935 xe_rtp_process_ctx_enable_active_tracking(&ctx, gt->wa_active.gt,
936 ARRAY_SIZE(gt_was));
937 xe_rtp_process_to_sr(&ctx, gt_was, ARRAY_SIZE(gt_was), >->reg_sr);
938 }
939 EXPORT_SYMBOL_IF_KUNIT(xe_wa_process_gt);
940
941 /**
942 * xe_wa_process_engine - process engine workaround table
943 * @hwe: engine instance to process workarounds for
944 *
945 * Process engine workaround table for this platform, saving in @hwe all the
946 * workarounds that need to be applied at the engine level that match this
947 * engine.
948 */
xe_wa_process_engine(struct xe_hw_engine * hwe)949 void xe_wa_process_engine(struct xe_hw_engine *hwe)
950 {
951 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
952
953 xe_rtp_process_ctx_enable_active_tracking(&ctx, hwe->gt->wa_active.engine,
954 ARRAY_SIZE(engine_was));
955 xe_rtp_process_to_sr(&ctx, engine_was, ARRAY_SIZE(engine_was), &hwe->reg_sr);
956 }
957
958 /**
959 * xe_wa_process_lrc - process context workaround table
960 * @hwe: engine instance to process workarounds for
961 *
962 * Process context workaround table for this platform, saving in @hwe all the
963 * workarounds that need to be applied on context restore. These are workarounds
964 * touching registers that are part of the HW context image.
965 */
xe_wa_process_lrc(struct xe_hw_engine * hwe)966 void xe_wa_process_lrc(struct xe_hw_engine *hwe)
967 {
968 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
969
970 xe_rtp_process_ctx_enable_active_tracking(&ctx, hwe->gt->wa_active.lrc,
971 ARRAY_SIZE(lrc_was));
972 xe_rtp_process_to_sr(&ctx, lrc_was, ARRAY_SIZE(lrc_was), &hwe->reg_lrc);
973 }
974
975 /**
976 * xe_wa_device_init - initialize device with workaround oob bookkeeping
977 * @xe: Xe device instance to initialize
978 *
979 * Returns 0 for success, negative with error code otherwise
980 */
xe_wa_device_init(struct xe_device * xe)981 int xe_wa_device_init(struct xe_device *xe)
982 {
983 unsigned long *p;
984
985 p = drmm_kzalloc(&xe->drm,
986 sizeof(*p) * BITS_TO_LONGS(ARRAY_SIZE(device_oob_was)),
987 GFP_KERNEL);
988
989 if (!p)
990 return -ENOMEM;
991
992 xe->wa_active.oob = p;
993
994 return 0;
995 }
996
997 /**
998 * xe_wa_init - initialize gt with workaround bookkeeping
999 * @gt: GT instance to initialize
1000 *
1001 * Returns 0 for success, negative error code otherwise.
1002 */
xe_wa_init(struct xe_gt * gt)1003 int xe_wa_init(struct xe_gt *gt)
1004 {
1005 struct xe_device *xe = gt_to_xe(gt);
1006 size_t n_oob, n_lrc, n_engine, n_gt, total;
1007 unsigned long *p;
1008
1009 n_gt = BITS_TO_LONGS(ARRAY_SIZE(gt_was));
1010 n_engine = BITS_TO_LONGS(ARRAY_SIZE(engine_was));
1011 n_lrc = BITS_TO_LONGS(ARRAY_SIZE(lrc_was));
1012 n_oob = BITS_TO_LONGS(ARRAY_SIZE(oob_was));
1013 total = n_gt + n_engine + n_lrc + n_oob;
1014
1015 p = drmm_kzalloc(&xe->drm, sizeof(*p) * total, GFP_KERNEL);
1016 if (!p)
1017 return -ENOMEM;
1018
1019 gt->wa_active.gt = p;
1020 p += n_gt;
1021 gt->wa_active.engine = p;
1022 p += n_engine;
1023 gt->wa_active.lrc = p;
1024 p += n_lrc;
1025 gt->wa_active.oob = p;
1026
1027 return 0;
1028 }
1029 ALLOW_ERROR_INJECTION(xe_wa_init, ERRNO); /* See xe_pci_probe() */
1030
xe_wa_device_dump(struct xe_device * xe,struct drm_printer * p)1031 void xe_wa_device_dump(struct xe_device *xe, struct drm_printer *p)
1032 {
1033 size_t idx;
1034
1035 drm_printf(p, "Device OOB Workarounds\n");
1036 for_each_set_bit(idx, xe->wa_active.oob, ARRAY_SIZE(device_oob_was))
1037 if (device_oob_was[idx].name)
1038 drm_printf_indent(p, 1, "%s\n", device_oob_was[idx].name);
1039 }
1040
xe_wa_dump(struct xe_gt * gt,struct drm_printer * p)1041 void xe_wa_dump(struct xe_gt *gt, struct drm_printer *p)
1042 {
1043 size_t idx;
1044
1045 drm_printf(p, "GT Workarounds\n");
1046 for_each_set_bit(idx, gt->wa_active.gt, ARRAY_SIZE(gt_was))
1047 drm_printf_indent(p, 1, "%s\n", gt_was[idx].name);
1048
1049 drm_printf(p, "\nEngine Workarounds\n");
1050 for_each_set_bit(idx, gt->wa_active.engine, ARRAY_SIZE(engine_was))
1051 drm_printf_indent(p, 1, "%s\n", engine_was[idx].name);
1052
1053 drm_printf(p, "\nLRC Workarounds\n");
1054 for_each_set_bit(idx, gt->wa_active.lrc, ARRAY_SIZE(lrc_was))
1055 drm_printf_indent(p, 1, "%s\n", lrc_was[idx].name);
1056
1057 drm_printf(p, "\nOOB Workarounds\n");
1058 for_each_set_bit(idx, gt->wa_active.oob, ARRAY_SIZE(oob_was))
1059 if (oob_was[idx].name)
1060 drm_printf_indent(p, 1, "%s\n", oob_was[idx].name);
1061 }
1062
1063 /*
1064 * Apply tile (non-GT, non-display) workarounds. Think very carefully before
1065 * adding anything to this function; most workarounds should be implemented
1066 * elsewhere. The programming here is primarily for sgunit/soc workarounds,
1067 * which are relatively rare. Since the registers these workarounds target are
1068 * outside the GT, they should only need to be applied once at device
1069 * probe/resume; they will not lose their values on any kind of GT or engine
1070 * reset.
1071 *
1072 * TODO: We may want to move this over to xe_rtp in the future once we have
1073 * enough workarounds to justify the work.
1074 */
xe_wa_apply_tile_workarounds(struct xe_tile * tile)1075 void xe_wa_apply_tile_workarounds(struct xe_tile *tile)
1076 {
1077 struct xe_mmio *mmio = &tile->mmio;
1078
1079 if (IS_SRIOV_VF(tile->xe))
1080 return;
1081
1082 if (XE_WA(tile->primary_gt, 22010954014))
1083 xe_mmio_rmw32(mmio, XEHP_CLOCK_GATE_DIS, 0, SGSI_SIDECLK_DIS);
1084 }
1085