1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (C) 2021 Felix Fietkau <nbd@nbd.name> */
3
4 #include <linux/kernel.h>
5 #include <linux/platform_device.h>
6 #include <linux/slab.h>
7 #include <linux/module.h>
8 #include <linux/bitfield.h>
9 #include <linux/dma-mapping.h>
10 #include <linux/skbuff.h>
11 #include <linux/of_platform.h>
12 #include <linux/of_address.h>
13 #include <linux/of_reserved_mem.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/debugfs.h>
16 #include <linux/soc/mediatek/mtk_wed.h>
17 #include <net/flow_offload.h>
18 #include <net/pkt_cls.h>
19 #include "mtk_eth_soc.h"
20 #include "mtk_wed.h"
21 #include "mtk_ppe.h"
22 #include "mtk_wed_wo.h"
23
24 #define MTK_PCIE_BASE(n) (0x1a143000 + (n) * 0x2000)
25
26 #define MTK_WED_PKT_SIZE 1920
27 #define MTK_WED_BUF_SIZE 2048
28 #define MTK_WED_PAGE_BUF_SIZE 128
29 #define MTK_WED_BUF_PER_PAGE (PAGE_SIZE / 2048)
30 #define MTK_WED_RX_BUF_PER_PAGE (PAGE_SIZE / MTK_WED_PAGE_BUF_SIZE)
31 #define MTK_WED_RX_RING_SIZE 1536
32 #define MTK_WED_RX_PG_BM_CNT 8192
33 #define MTK_WED_AMSDU_BUF_SIZE (PAGE_SIZE << 4)
34 #define MTK_WED_AMSDU_NPAGES 32
35
36 #define MTK_WED_TX_RING_SIZE 2048
37 #define MTK_WED_WDMA_RING_SIZE 1024
38 #define MTK_WED_MAX_GROUP_SIZE 0x100
39 #define MTK_WED_VLD_GROUP_SIZE 0x40
40 #define MTK_WED_PER_GROUP_PKT 128
41
42 #define MTK_WED_FBUF_SIZE 128
43 #define MTK_WED_MIOD_CNT 16
44 #define MTK_WED_FB_CMD_CNT 1024
45 #define MTK_WED_RRO_QUE_CNT 8192
46 #define MTK_WED_MIOD_ENTRY_CNT 128
47
48 #define MTK_WED_TX_BM_DMA_SIZE 65536
49 #define MTK_WED_TX_BM_PKT_CNT 32768
50
51 static struct mtk_wed_hw *hw_list[3];
52 static DEFINE_MUTEX(hw_lock);
53
54 struct mtk_wed_flow_block_priv {
55 struct mtk_wed_hw *hw;
56 struct net_device *dev;
57 };
58
59 static const struct mtk_wed_soc_data mt7622_data = {
60 .regmap = {
61 .tx_bm_tkid = 0x088,
62 .wpdma_rx_ring0 = 0x770,
63 .reset_idx_tx_mask = GENMASK(3, 0),
64 .reset_idx_rx_mask = GENMASK(17, 16),
65 },
66 .tx_ring_desc_size = sizeof(struct mtk_wdma_desc),
67 .wdma_desc_size = sizeof(struct mtk_wdma_desc),
68 };
69
70 static const struct mtk_wed_soc_data mt7986_data = {
71 .regmap = {
72 .tx_bm_tkid = 0x0c8,
73 .wpdma_rx_ring0 = 0x770,
74 .reset_idx_tx_mask = GENMASK(1, 0),
75 .reset_idx_rx_mask = GENMASK(7, 6),
76 },
77 .tx_ring_desc_size = sizeof(struct mtk_wdma_desc),
78 .wdma_desc_size = 2 * sizeof(struct mtk_wdma_desc),
79 };
80
81 static const struct mtk_wed_soc_data mt7988_data = {
82 .regmap = {
83 .tx_bm_tkid = 0x0c8,
84 .wpdma_rx_ring0 = 0x7d0,
85 .reset_idx_tx_mask = GENMASK(1, 0),
86 .reset_idx_rx_mask = GENMASK(7, 6),
87 },
88 .tx_ring_desc_size = sizeof(struct mtk_wed_bm_desc),
89 .wdma_desc_size = 2 * sizeof(struct mtk_wdma_desc),
90 };
91
92 static void
wed_m32(struct mtk_wed_device * dev,u32 reg,u32 mask,u32 val)93 wed_m32(struct mtk_wed_device *dev, u32 reg, u32 mask, u32 val)
94 {
95 regmap_update_bits(dev->hw->regs, reg, mask | val, val);
96 }
97
98 static void
wed_set(struct mtk_wed_device * dev,u32 reg,u32 mask)99 wed_set(struct mtk_wed_device *dev, u32 reg, u32 mask)
100 {
101 return wed_m32(dev, reg, 0, mask);
102 }
103
104 static void
wed_clr(struct mtk_wed_device * dev,u32 reg,u32 mask)105 wed_clr(struct mtk_wed_device *dev, u32 reg, u32 mask)
106 {
107 return wed_m32(dev, reg, mask, 0);
108 }
109
110 static void
wdma_m32(struct mtk_wed_device * dev,u32 reg,u32 mask,u32 val)111 wdma_m32(struct mtk_wed_device *dev, u32 reg, u32 mask, u32 val)
112 {
113 wdma_w32(dev, reg, (wdma_r32(dev, reg) & ~mask) | val);
114 }
115
116 static void
wdma_set(struct mtk_wed_device * dev,u32 reg,u32 mask)117 wdma_set(struct mtk_wed_device *dev, u32 reg, u32 mask)
118 {
119 wdma_m32(dev, reg, 0, mask);
120 }
121
122 static void
wdma_clr(struct mtk_wed_device * dev,u32 reg,u32 mask)123 wdma_clr(struct mtk_wed_device *dev, u32 reg, u32 mask)
124 {
125 wdma_m32(dev, reg, mask, 0);
126 }
127
128 static u32
wifi_r32(struct mtk_wed_device * dev,u32 reg)129 wifi_r32(struct mtk_wed_device *dev, u32 reg)
130 {
131 return readl(dev->wlan.base + reg);
132 }
133
134 static void
wifi_w32(struct mtk_wed_device * dev,u32 reg,u32 val)135 wifi_w32(struct mtk_wed_device *dev, u32 reg, u32 val)
136 {
137 writel(val, dev->wlan.base + reg);
138 }
139
140 static u32
mtk_wed_read_reset(struct mtk_wed_device * dev)141 mtk_wed_read_reset(struct mtk_wed_device *dev)
142 {
143 return wed_r32(dev, MTK_WED_RESET);
144 }
145
146 static u32
mtk_wdma_read_reset(struct mtk_wed_device * dev)147 mtk_wdma_read_reset(struct mtk_wed_device *dev)
148 {
149 return wdma_r32(dev, MTK_WDMA_GLO_CFG);
150 }
151
152 static void
mtk_wdma_v3_rx_reset(struct mtk_wed_device * dev)153 mtk_wdma_v3_rx_reset(struct mtk_wed_device *dev)
154 {
155 u32 status;
156
157 if (!mtk_wed_is_v3_or_greater(dev->hw))
158 return;
159
160 wdma_clr(dev, MTK_WDMA_PREF_TX_CFG, MTK_WDMA_PREF_TX_CFG_PREF_EN);
161 wdma_clr(dev, MTK_WDMA_PREF_RX_CFG, MTK_WDMA_PREF_RX_CFG_PREF_EN);
162
163 if (read_poll_timeout(wdma_r32, status,
164 !(status & MTK_WDMA_PREF_TX_CFG_PREF_BUSY),
165 0, 10000, false, dev, MTK_WDMA_PREF_TX_CFG))
166 dev_err(dev->hw->dev, "rx reset failed\n");
167
168 if (read_poll_timeout(wdma_r32, status,
169 !(status & MTK_WDMA_PREF_RX_CFG_PREF_BUSY),
170 0, 10000, false, dev, MTK_WDMA_PREF_RX_CFG))
171 dev_err(dev->hw->dev, "rx reset failed\n");
172
173 wdma_clr(dev, MTK_WDMA_WRBK_TX_CFG, MTK_WDMA_WRBK_TX_CFG_WRBK_EN);
174 wdma_clr(dev, MTK_WDMA_WRBK_RX_CFG, MTK_WDMA_WRBK_RX_CFG_WRBK_EN);
175
176 if (read_poll_timeout(wdma_r32, status,
177 !(status & MTK_WDMA_WRBK_TX_CFG_WRBK_BUSY),
178 0, 10000, false, dev, MTK_WDMA_WRBK_TX_CFG))
179 dev_err(dev->hw->dev, "rx reset failed\n");
180
181 if (read_poll_timeout(wdma_r32, status,
182 !(status & MTK_WDMA_WRBK_RX_CFG_WRBK_BUSY),
183 0, 10000, false, dev, MTK_WDMA_WRBK_RX_CFG))
184 dev_err(dev->hw->dev, "rx reset failed\n");
185
186 /* prefetch FIFO */
187 wdma_w32(dev, MTK_WDMA_PREF_RX_FIFO_CFG,
188 MTK_WDMA_PREF_RX_FIFO_CFG_RING0_CLEAR |
189 MTK_WDMA_PREF_RX_FIFO_CFG_RING1_CLEAR);
190 wdma_clr(dev, MTK_WDMA_PREF_RX_FIFO_CFG,
191 MTK_WDMA_PREF_RX_FIFO_CFG_RING0_CLEAR |
192 MTK_WDMA_PREF_RX_FIFO_CFG_RING1_CLEAR);
193
194 /* core FIFO */
195 wdma_w32(dev, MTK_WDMA_XDMA_RX_FIFO_CFG,
196 MTK_WDMA_XDMA_RX_FIFO_CFG_RX_PAR_FIFO_CLEAR |
197 MTK_WDMA_XDMA_RX_FIFO_CFG_RX_CMD_FIFO_CLEAR |
198 MTK_WDMA_XDMA_RX_FIFO_CFG_RX_DMAD_FIFO_CLEAR |
199 MTK_WDMA_XDMA_RX_FIFO_CFG_RX_ARR_FIFO_CLEAR |
200 MTK_WDMA_XDMA_RX_FIFO_CFG_RX_LEN_FIFO_CLEAR |
201 MTK_WDMA_XDMA_RX_FIFO_CFG_RX_WID_FIFO_CLEAR |
202 MTK_WDMA_XDMA_RX_FIFO_CFG_RX_BID_FIFO_CLEAR);
203 wdma_clr(dev, MTK_WDMA_XDMA_RX_FIFO_CFG,
204 MTK_WDMA_XDMA_RX_FIFO_CFG_RX_PAR_FIFO_CLEAR |
205 MTK_WDMA_XDMA_RX_FIFO_CFG_RX_CMD_FIFO_CLEAR |
206 MTK_WDMA_XDMA_RX_FIFO_CFG_RX_DMAD_FIFO_CLEAR |
207 MTK_WDMA_XDMA_RX_FIFO_CFG_RX_ARR_FIFO_CLEAR |
208 MTK_WDMA_XDMA_RX_FIFO_CFG_RX_LEN_FIFO_CLEAR |
209 MTK_WDMA_XDMA_RX_FIFO_CFG_RX_WID_FIFO_CLEAR |
210 MTK_WDMA_XDMA_RX_FIFO_CFG_RX_BID_FIFO_CLEAR);
211
212 /* writeback FIFO */
213 wdma_w32(dev, MTK_WDMA_WRBK_RX_FIFO_CFG(0),
214 MTK_WDMA_WRBK_RX_FIFO_CFG_RING_CLEAR);
215 wdma_w32(dev, MTK_WDMA_WRBK_RX_FIFO_CFG(1),
216 MTK_WDMA_WRBK_RX_FIFO_CFG_RING_CLEAR);
217
218 wdma_clr(dev, MTK_WDMA_WRBK_RX_FIFO_CFG(0),
219 MTK_WDMA_WRBK_RX_FIFO_CFG_RING_CLEAR);
220 wdma_clr(dev, MTK_WDMA_WRBK_RX_FIFO_CFG(1),
221 MTK_WDMA_WRBK_RX_FIFO_CFG_RING_CLEAR);
222
223 /* prefetch ring status */
224 wdma_w32(dev, MTK_WDMA_PREF_SIDX_CFG,
225 MTK_WDMA_PREF_SIDX_CFG_RX_RING_CLEAR);
226 wdma_clr(dev, MTK_WDMA_PREF_SIDX_CFG,
227 MTK_WDMA_PREF_SIDX_CFG_RX_RING_CLEAR);
228
229 /* writeback ring status */
230 wdma_w32(dev, MTK_WDMA_WRBK_SIDX_CFG,
231 MTK_WDMA_WRBK_SIDX_CFG_RX_RING_CLEAR);
232 wdma_clr(dev, MTK_WDMA_WRBK_SIDX_CFG,
233 MTK_WDMA_WRBK_SIDX_CFG_RX_RING_CLEAR);
234 }
235
236 static int
mtk_wdma_rx_reset(struct mtk_wed_device * dev)237 mtk_wdma_rx_reset(struct mtk_wed_device *dev)
238 {
239 u32 status, mask = MTK_WDMA_GLO_CFG_RX_DMA_BUSY;
240 int i, ret;
241
242 wdma_clr(dev, MTK_WDMA_GLO_CFG, MTK_WDMA_GLO_CFG_RX_DMA_EN);
243 ret = readx_poll_timeout(mtk_wdma_read_reset, dev, status,
244 !(status & mask), 0, 10000);
245 if (ret)
246 dev_err(dev->hw->dev, "rx reset failed\n");
247
248 mtk_wdma_v3_rx_reset(dev);
249 wdma_w32(dev, MTK_WDMA_RESET_IDX, MTK_WDMA_RESET_IDX_RX);
250 wdma_w32(dev, MTK_WDMA_RESET_IDX, 0);
251
252 for (i = 0; i < ARRAY_SIZE(dev->rx_wdma); i++) {
253 if (dev->rx_wdma[i].desc)
254 continue;
255
256 wdma_w32(dev,
257 MTK_WDMA_RING_RX(i) + MTK_WED_RING_OFS_CPU_IDX, 0);
258 }
259
260 return ret;
261 }
262
263 static u32
mtk_wed_check_busy(struct mtk_wed_device * dev,u32 reg,u32 mask)264 mtk_wed_check_busy(struct mtk_wed_device *dev, u32 reg, u32 mask)
265 {
266 return !!(wed_r32(dev, reg) & mask);
267 }
268
269 static int
mtk_wed_poll_busy(struct mtk_wed_device * dev,u32 reg,u32 mask)270 mtk_wed_poll_busy(struct mtk_wed_device *dev, u32 reg, u32 mask)
271 {
272 int sleep = 15000;
273 int timeout = 100 * sleep;
274 u32 val;
275
276 return read_poll_timeout(mtk_wed_check_busy, val, !val, sleep,
277 timeout, false, dev, reg, mask);
278 }
279
280 static void
mtk_wdma_v3_tx_reset(struct mtk_wed_device * dev)281 mtk_wdma_v3_tx_reset(struct mtk_wed_device *dev)
282 {
283 u32 status;
284
285 if (!mtk_wed_is_v3_or_greater(dev->hw))
286 return;
287
288 wdma_clr(dev, MTK_WDMA_PREF_TX_CFG, MTK_WDMA_PREF_TX_CFG_PREF_EN);
289 wdma_clr(dev, MTK_WDMA_PREF_RX_CFG, MTK_WDMA_PREF_RX_CFG_PREF_EN);
290
291 if (read_poll_timeout(wdma_r32, status,
292 !(status & MTK_WDMA_PREF_TX_CFG_PREF_BUSY),
293 0, 10000, false, dev, MTK_WDMA_PREF_TX_CFG))
294 dev_err(dev->hw->dev, "tx reset failed\n");
295
296 if (read_poll_timeout(wdma_r32, status,
297 !(status & MTK_WDMA_PREF_RX_CFG_PREF_BUSY),
298 0, 10000, false, dev, MTK_WDMA_PREF_RX_CFG))
299 dev_err(dev->hw->dev, "tx reset failed\n");
300
301 wdma_clr(dev, MTK_WDMA_WRBK_TX_CFG, MTK_WDMA_WRBK_TX_CFG_WRBK_EN);
302 wdma_clr(dev, MTK_WDMA_WRBK_RX_CFG, MTK_WDMA_WRBK_RX_CFG_WRBK_EN);
303
304 if (read_poll_timeout(wdma_r32, status,
305 !(status & MTK_WDMA_WRBK_TX_CFG_WRBK_BUSY),
306 0, 10000, false, dev, MTK_WDMA_WRBK_TX_CFG))
307 dev_err(dev->hw->dev, "tx reset failed\n");
308
309 if (read_poll_timeout(wdma_r32, status,
310 !(status & MTK_WDMA_WRBK_RX_CFG_WRBK_BUSY),
311 0, 10000, false, dev, MTK_WDMA_WRBK_RX_CFG))
312 dev_err(dev->hw->dev, "tx reset failed\n");
313
314 /* prefetch FIFO */
315 wdma_w32(dev, MTK_WDMA_PREF_TX_FIFO_CFG,
316 MTK_WDMA_PREF_TX_FIFO_CFG_RING0_CLEAR |
317 MTK_WDMA_PREF_TX_FIFO_CFG_RING1_CLEAR);
318 wdma_clr(dev, MTK_WDMA_PREF_TX_FIFO_CFG,
319 MTK_WDMA_PREF_TX_FIFO_CFG_RING0_CLEAR |
320 MTK_WDMA_PREF_TX_FIFO_CFG_RING1_CLEAR);
321
322 /* core FIFO */
323 wdma_w32(dev, MTK_WDMA_XDMA_TX_FIFO_CFG,
324 MTK_WDMA_XDMA_TX_FIFO_CFG_TX_PAR_FIFO_CLEAR |
325 MTK_WDMA_XDMA_TX_FIFO_CFG_TX_CMD_FIFO_CLEAR |
326 MTK_WDMA_XDMA_TX_FIFO_CFG_TX_DMAD_FIFO_CLEAR |
327 MTK_WDMA_XDMA_TX_FIFO_CFG_TX_ARR_FIFO_CLEAR);
328 wdma_clr(dev, MTK_WDMA_XDMA_TX_FIFO_CFG,
329 MTK_WDMA_XDMA_TX_FIFO_CFG_TX_PAR_FIFO_CLEAR |
330 MTK_WDMA_XDMA_TX_FIFO_CFG_TX_CMD_FIFO_CLEAR |
331 MTK_WDMA_XDMA_TX_FIFO_CFG_TX_DMAD_FIFO_CLEAR |
332 MTK_WDMA_XDMA_TX_FIFO_CFG_TX_ARR_FIFO_CLEAR);
333
334 /* writeback FIFO */
335 wdma_w32(dev, MTK_WDMA_WRBK_TX_FIFO_CFG(0),
336 MTK_WDMA_WRBK_TX_FIFO_CFG_RING_CLEAR);
337 wdma_w32(dev, MTK_WDMA_WRBK_TX_FIFO_CFG(1),
338 MTK_WDMA_WRBK_TX_FIFO_CFG_RING_CLEAR);
339
340 wdma_clr(dev, MTK_WDMA_WRBK_TX_FIFO_CFG(0),
341 MTK_WDMA_WRBK_TX_FIFO_CFG_RING_CLEAR);
342 wdma_clr(dev, MTK_WDMA_WRBK_TX_FIFO_CFG(1),
343 MTK_WDMA_WRBK_TX_FIFO_CFG_RING_CLEAR);
344
345 /* prefetch ring status */
346 wdma_w32(dev, MTK_WDMA_PREF_SIDX_CFG,
347 MTK_WDMA_PREF_SIDX_CFG_TX_RING_CLEAR);
348 wdma_clr(dev, MTK_WDMA_PREF_SIDX_CFG,
349 MTK_WDMA_PREF_SIDX_CFG_TX_RING_CLEAR);
350
351 /* writeback ring status */
352 wdma_w32(dev, MTK_WDMA_WRBK_SIDX_CFG,
353 MTK_WDMA_WRBK_SIDX_CFG_TX_RING_CLEAR);
354 wdma_clr(dev, MTK_WDMA_WRBK_SIDX_CFG,
355 MTK_WDMA_WRBK_SIDX_CFG_TX_RING_CLEAR);
356 }
357
358 static void
mtk_wdma_tx_reset(struct mtk_wed_device * dev)359 mtk_wdma_tx_reset(struct mtk_wed_device *dev)
360 {
361 u32 status, mask = MTK_WDMA_GLO_CFG_TX_DMA_BUSY;
362 int i;
363
364 wdma_clr(dev, MTK_WDMA_GLO_CFG, MTK_WDMA_GLO_CFG_TX_DMA_EN);
365 if (readx_poll_timeout(mtk_wdma_read_reset, dev, status,
366 !(status & mask), 0, 10000))
367 dev_err(dev->hw->dev, "tx reset failed\n");
368
369 mtk_wdma_v3_tx_reset(dev);
370 wdma_w32(dev, MTK_WDMA_RESET_IDX, MTK_WDMA_RESET_IDX_TX);
371 wdma_w32(dev, MTK_WDMA_RESET_IDX, 0);
372
373 for (i = 0; i < ARRAY_SIZE(dev->tx_wdma); i++)
374 wdma_w32(dev,
375 MTK_WDMA_RING_TX(i) + MTK_WED_RING_OFS_CPU_IDX, 0);
376 }
377
378 static void
mtk_wed_reset(struct mtk_wed_device * dev,u32 mask)379 mtk_wed_reset(struct mtk_wed_device *dev, u32 mask)
380 {
381 u32 status;
382
383 wed_w32(dev, MTK_WED_RESET, mask);
384 if (readx_poll_timeout(mtk_wed_read_reset, dev, status,
385 !(status & mask), 0, 1000))
386 WARN_ON_ONCE(1);
387 }
388
389 static u32
mtk_wed_wo_read_status(struct mtk_wed_device * dev)390 mtk_wed_wo_read_status(struct mtk_wed_device *dev)
391 {
392 return wed_r32(dev, MTK_WED_SCR0 + 4 * MTK_WED_DUMMY_CR_WO_STATUS);
393 }
394
395 static void
mtk_wed_wo_reset(struct mtk_wed_device * dev)396 mtk_wed_wo_reset(struct mtk_wed_device *dev)
397 {
398 struct mtk_wed_wo *wo = dev->hw->wed_wo;
399 u8 state = MTK_WED_WO_STATE_DISABLE;
400 void __iomem *reg;
401 u32 val;
402
403 mtk_wdma_tx_reset(dev);
404 mtk_wed_reset(dev, MTK_WED_RESET_WED);
405
406 if (mtk_wed_mcu_send_msg(wo, MTK_WED_MODULE_ID_WO,
407 MTK_WED_WO_CMD_CHANGE_STATE, &state,
408 sizeof(state), false))
409 return;
410
411 if (readx_poll_timeout(mtk_wed_wo_read_status, dev, val,
412 val == MTK_WED_WOIF_DISABLE_DONE,
413 100, MTK_WOCPU_TIMEOUT))
414 dev_err(dev->hw->dev, "failed to disable wed-wo\n");
415
416 reg = ioremap(MTK_WED_WO_CPU_MCUSYS_RESET_ADDR, 4);
417
418 val = readl(reg);
419 switch (dev->hw->index) {
420 case 0:
421 val |= MTK_WED_WO_CPU_WO0_MCUSYS_RESET_MASK;
422 writel(val, reg);
423 val &= ~MTK_WED_WO_CPU_WO0_MCUSYS_RESET_MASK;
424 writel(val, reg);
425 break;
426 case 1:
427 val |= MTK_WED_WO_CPU_WO1_MCUSYS_RESET_MASK;
428 writel(val, reg);
429 val &= ~MTK_WED_WO_CPU_WO1_MCUSYS_RESET_MASK;
430 writel(val, reg);
431 break;
432 default:
433 break;
434 }
435 iounmap(reg);
436 }
437
mtk_wed_fe_reset(void)438 void mtk_wed_fe_reset(void)
439 {
440 int i;
441
442 mutex_lock(&hw_lock);
443
444 for (i = 0; i < ARRAY_SIZE(hw_list); i++) {
445 struct mtk_wed_hw *hw = hw_list[i];
446 struct mtk_wed_device *dev;
447 int err;
448
449 if (!hw)
450 break;
451
452 dev = hw->wed_dev;
453 if (!dev || !dev->wlan.reset)
454 continue;
455
456 /* reset callback blocks until WLAN reset is completed */
457 err = dev->wlan.reset(dev);
458 if (err)
459 dev_err(dev->dev, "wlan reset failed: %d\n", err);
460 }
461
462 mutex_unlock(&hw_lock);
463 }
464
mtk_wed_fe_reset_complete(void)465 void mtk_wed_fe_reset_complete(void)
466 {
467 int i;
468
469 mutex_lock(&hw_lock);
470
471 for (i = 0; i < ARRAY_SIZE(hw_list); i++) {
472 struct mtk_wed_hw *hw = hw_list[i];
473 struct mtk_wed_device *dev;
474
475 if (!hw)
476 break;
477
478 dev = hw->wed_dev;
479 if (!dev || !dev->wlan.reset_complete)
480 continue;
481
482 dev->wlan.reset_complete(dev);
483 }
484
485 mutex_unlock(&hw_lock);
486 }
487
488 static struct mtk_wed_hw *
mtk_wed_assign(struct mtk_wed_device * dev)489 mtk_wed_assign(struct mtk_wed_device *dev)
490 {
491 struct mtk_wed_hw *hw;
492 int i;
493
494 if (dev->wlan.bus_type == MTK_WED_BUS_PCIE) {
495 hw = hw_list[pci_domain_nr(dev->wlan.pci_dev->bus)];
496 if (!hw)
497 return NULL;
498
499 if (!hw->wed_dev)
500 goto out;
501
502 if (mtk_wed_is_v1(hw))
503 return NULL;
504
505 /* MT7986 WED devices do not have any pcie slot restrictions */
506 }
507 /* MT7986 PCIE or AXI */
508 for (i = 0; i < ARRAY_SIZE(hw_list); i++) {
509 hw = hw_list[i];
510 if (hw && !hw->wed_dev)
511 goto out;
512 }
513
514 return NULL;
515
516 out:
517 hw->wed_dev = dev;
518 return hw;
519 }
520
521 static int
mtk_wed_amsdu_buffer_alloc(struct mtk_wed_device * dev)522 mtk_wed_amsdu_buffer_alloc(struct mtk_wed_device *dev)
523 {
524 struct mtk_wed_hw *hw = dev->hw;
525 struct mtk_wed_amsdu *wed_amsdu;
526 int i;
527
528 if (!mtk_wed_is_v3_or_greater(hw))
529 return 0;
530
531 wed_amsdu = devm_kcalloc(hw->dev, MTK_WED_AMSDU_NPAGES,
532 sizeof(*wed_amsdu), GFP_KERNEL);
533 if (!wed_amsdu)
534 return -ENOMEM;
535
536 for (i = 0; i < MTK_WED_AMSDU_NPAGES; i++) {
537 void *ptr;
538
539 /* each segment is 64K */
540 ptr = (void *)__get_free_pages(GFP_KERNEL | __GFP_NOWARN |
541 __GFP_ZERO | __GFP_COMP |
542 GFP_DMA32,
543 get_order(MTK_WED_AMSDU_BUF_SIZE));
544 if (!ptr)
545 goto error;
546
547 wed_amsdu[i].txd = ptr;
548 wed_amsdu[i].txd_phy = dma_map_single(hw->dev, ptr,
549 MTK_WED_AMSDU_BUF_SIZE,
550 DMA_TO_DEVICE);
551 if (dma_mapping_error(hw->dev, wed_amsdu[i].txd_phy))
552 goto error;
553 }
554 dev->hw->wed_amsdu = wed_amsdu;
555
556 return 0;
557
558 error:
559 for (i--; i >= 0; i--)
560 dma_unmap_single(hw->dev, wed_amsdu[i].txd_phy,
561 MTK_WED_AMSDU_BUF_SIZE, DMA_TO_DEVICE);
562 return -ENOMEM;
563 }
564
565 static void
mtk_wed_amsdu_free_buffer(struct mtk_wed_device * dev)566 mtk_wed_amsdu_free_buffer(struct mtk_wed_device *dev)
567 {
568 struct mtk_wed_amsdu *wed_amsdu = dev->hw->wed_amsdu;
569 int i;
570
571 if (!wed_amsdu)
572 return;
573
574 for (i = 0; i < MTK_WED_AMSDU_NPAGES; i++) {
575 dma_unmap_single(dev->hw->dev, wed_amsdu[i].txd_phy,
576 MTK_WED_AMSDU_BUF_SIZE, DMA_TO_DEVICE);
577 free_pages((unsigned long)wed_amsdu[i].txd,
578 get_order(MTK_WED_AMSDU_BUF_SIZE));
579 }
580 }
581
582 static int
mtk_wed_amsdu_init(struct mtk_wed_device * dev)583 mtk_wed_amsdu_init(struct mtk_wed_device *dev)
584 {
585 struct mtk_wed_amsdu *wed_amsdu = dev->hw->wed_amsdu;
586 int i, ret;
587
588 if (!wed_amsdu)
589 return 0;
590
591 for (i = 0; i < MTK_WED_AMSDU_NPAGES; i++)
592 wed_w32(dev, MTK_WED_AMSDU_HIFTXD_BASE_L(i),
593 wed_amsdu[i].txd_phy);
594
595 /* init all sta parameter */
596 wed_w32(dev, MTK_WED_AMSDU_STA_INFO_INIT, MTK_WED_AMSDU_STA_RMVL |
597 MTK_WED_AMSDU_STA_WTBL_HDRT_MODE |
598 FIELD_PREP(MTK_WED_AMSDU_STA_MAX_AMSDU_LEN,
599 dev->wlan.amsdu_max_len >> 8) |
600 FIELD_PREP(MTK_WED_AMSDU_STA_MAX_AMSDU_NUM,
601 dev->wlan.amsdu_max_subframes));
602
603 wed_w32(dev, MTK_WED_AMSDU_STA_INFO, MTK_WED_AMSDU_STA_INFO_DO_INIT);
604
605 ret = mtk_wed_poll_busy(dev, MTK_WED_AMSDU_STA_INFO,
606 MTK_WED_AMSDU_STA_INFO_DO_INIT);
607 if (ret) {
608 dev_err(dev->hw->dev, "amsdu initialization failed\n");
609 return ret;
610 }
611
612 /* init partial amsdu offload txd src */
613 wed_set(dev, MTK_WED_AMSDU_HIFTXD_CFG,
614 FIELD_PREP(MTK_WED_AMSDU_HIFTXD_SRC, dev->hw->index));
615
616 /* init qmem */
617 wed_set(dev, MTK_WED_AMSDU_PSE, MTK_WED_AMSDU_PSE_RESET);
618 ret = mtk_wed_poll_busy(dev, MTK_WED_MON_AMSDU_QMEM_STS1, BIT(29));
619 if (ret) {
620 pr_info("%s: amsdu qmem initialization failed\n", __func__);
621 return ret;
622 }
623
624 /* eagle E1 PCIE1 tx ring 22 flow control issue */
625 if (dev->wlan.id == 0x7991)
626 wed_clr(dev, MTK_WED_AMSDU_FIFO, MTK_WED_AMSDU_IS_PRIOR0_RING);
627
628 wed_set(dev, MTK_WED_CTRL, MTK_WED_CTRL_TX_AMSDU_EN);
629
630 return 0;
631 }
632
633 static int
mtk_wed_tx_buffer_alloc(struct mtk_wed_device * dev)634 mtk_wed_tx_buffer_alloc(struct mtk_wed_device *dev)
635 {
636 u32 desc_size = dev->hw->soc->tx_ring_desc_size;
637 int i, page_idx = 0, n_pages, ring_size;
638 int token = dev->wlan.token_start;
639 struct mtk_wed_buf *page_list;
640 dma_addr_t desc_phys;
641 void *desc_ptr;
642
643 if (!mtk_wed_is_v3_or_greater(dev->hw)) {
644 ring_size = dev->wlan.nbuf & ~(MTK_WED_BUF_PER_PAGE - 1);
645 dev->tx_buf_ring.size = ring_size;
646 } else {
647 dev->tx_buf_ring.size = MTK_WED_TX_BM_DMA_SIZE;
648 ring_size = MTK_WED_TX_BM_PKT_CNT;
649 }
650 n_pages = dev->tx_buf_ring.size / MTK_WED_BUF_PER_PAGE;
651
652 page_list = kcalloc(n_pages, sizeof(*page_list), GFP_KERNEL);
653 if (!page_list)
654 return -ENOMEM;
655
656 dev->tx_buf_ring.pages = page_list;
657
658 desc_ptr = dma_alloc_coherent(dev->hw->dev,
659 dev->tx_buf_ring.size * desc_size,
660 &desc_phys, GFP_KERNEL);
661 if (!desc_ptr)
662 return -ENOMEM;
663
664 dev->tx_buf_ring.desc = desc_ptr;
665 dev->tx_buf_ring.desc_phys = desc_phys;
666
667 for (i = 0; i < ring_size; i += MTK_WED_BUF_PER_PAGE) {
668 dma_addr_t page_phys, buf_phys;
669 struct page *page;
670 void *buf;
671 int s;
672
673 page = __dev_alloc_page(GFP_KERNEL);
674 if (!page)
675 return -ENOMEM;
676
677 page_phys = dma_map_page(dev->hw->dev, page, 0, PAGE_SIZE,
678 DMA_BIDIRECTIONAL);
679 if (dma_mapping_error(dev->hw->dev, page_phys)) {
680 __free_page(page);
681 return -ENOMEM;
682 }
683
684 page_list[page_idx].p = page;
685 page_list[page_idx++].phy_addr = page_phys;
686 dma_sync_single_for_cpu(dev->hw->dev, page_phys, PAGE_SIZE,
687 DMA_BIDIRECTIONAL);
688
689 buf = page_to_virt(page);
690 buf_phys = page_phys;
691
692 for (s = 0; s < MTK_WED_BUF_PER_PAGE; s++) {
693 struct mtk_wdma_desc *desc = desc_ptr;
694 u32 ctrl;
695
696 desc->buf0 = cpu_to_le32(buf_phys);
697 if (!mtk_wed_is_v3_or_greater(dev->hw)) {
698 u32 txd_size;
699
700 txd_size = dev->wlan.init_buf(buf, buf_phys,
701 token++);
702 desc->buf1 = cpu_to_le32(buf_phys + txd_size);
703 ctrl = FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN0, txd_size);
704 if (mtk_wed_is_v1(dev->hw))
705 ctrl |= MTK_WDMA_DESC_CTRL_LAST_SEG1 |
706 FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN1,
707 MTK_WED_BUF_SIZE - txd_size);
708 else
709 ctrl |= MTK_WDMA_DESC_CTRL_LAST_SEG0 |
710 FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN1_V2,
711 MTK_WED_BUF_SIZE - txd_size);
712 desc->info = 0;
713 } else {
714 ctrl = token << 16 | TX_DMA_PREP_ADDR64(buf_phys);
715 }
716 desc->ctrl = cpu_to_le32(ctrl);
717
718 desc_ptr += desc_size;
719 buf += MTK_WED_BUF_SIZE;
720 buf_phys += MTK_WED_BUF_SIZE;
721 }
722
723 dma_sync_single_for_device(dev->hw->dev, page_phys, PAGE_SIZE,
724 DMA_BIDIRECTIONAL);
725 }
726
727 return 0;
728 }
729
730 static void
mtk_wed_free_tx_buffer(struct mtk_wed_device * dev)731 mtk_wed_free_tx_buffer(struct mtk_wed_device *dev)
732 {
733 struct mtk_wed_buf *page_list = dev->tx_buf_ring.pages;
734 struct mtk_wed_hw *hw = dev->hw;
735 int i, page_idx = 0;
736
737 if (!page_list)
738 return;
739
740 if (!dev->tx_buf_ring.desc)
741 goto free_pagelist;
742
743 for (i = 0; i < dev->tx_buf_ring.size; i += MTK_WED_BUF_PER_PAGE) {
744 dma_addr_t page_phy = page_list[page_idx].phy_addr;
745 void *page = page_list[page_idx++].p;
746
747 if (!page)
748 break;
749
750 dma_unmap_page(dev->hw->dev, page_phy, PAGE_SIZE,
751 DMA_BIDIRECTIONAL);
752 __free_page(page);
753 }
754
755 dma_free_coherent(dev->hw->dev,
756 dev->tx_buf_ring.size * hw->soc->tx_ring_desc_size,
757 dev->tx_buf_ring.desc,
758 dev->tx_buf_ring.desc_phys);
759
760 free_pagelist:
761 kfree(page_list);
762 }
763
764 static int
mtk_wed_hwrro_buffer_alloc(struct mtk_wed_device * dev)765 mtk_wed_hwrro_buffer_alloc(struct mtk_wed_device *dev)
766 {
767 int n_pages = MTK_WED_RX_PG_BM_CNT / MTK_WED_RX_BUF_PER_PAGE;
768 struct mtk_wed_buf *page_list;
769 struct mtk_wed_bm_desc *desc;
770 dma_addr_t desc_phys;
771 int i, page_idx = 0;
772
773 if (!dev->wlan.hw_rro)
774 return 0;
775
776 page_list = kcalloc(n_pages, sizeof(*page_list), GFP_KERNEL);
777 if (!page_list)
778 return -ENOMEM;
779
780 dev->hw_rro.size = dev->wlan.rx_nbuf & ~(MTK_WED_BUF_PER_PAGE - 1);
781 dev->hw_rro.pages = page_list;
782 desc = dma_alloc_coherent(dev->hw->dev,
783 dev->wlan.rx_nbuf * sizeof(*desc),
784 &desc_phys, GFP_KERNEL);
785 if (!desc)
786 return -ENOMEM;
787
788 dev->hw_rro.desc = desc;
789 dev->hw_rro.desc_phys = desc_phys;
790
791 for (i = 0; i < MTK_WED_RX_PG_BM_CNT; i += MTK_WED_RX_BUF_PER_PAGE) {
792 dma_addr_t page_phys, buf_phys;
793 struct page *page;
794 int s;
795
796 page = __dev_alloc_page(GFP_KERNEL);
797 if (!page)
798 return -ENOMEM;
799
800 page_phys = dma_map_page(dev->hw->dev, page, 0, PAGE_SIZE,
801 DMA_BIDIRECTIONAL);
802 if (dma_mapping_error(dev->hw->dev, page_phys)) {
803 __free_page(page);
804 return -ENOMEM;
805 }
806
807 page_list[page_idx].p = page;
808 page_list[page_idx++].phy_addr = page_phys;
809 dma_sync_single_for_cpu(dev->hw->dev, page_phys, PAGE_SIZE,
810 DMA_BIDIRECTIONAL);
811
812 buf_phys = page_phys;
813 for (s = 0; s < MTK_WED_RX_BUF_PER_PAGE; s++) {
814 desc->buf0 = cpu_to_le32(buf_phys);
815 desc->token = cpu_to_le32(RX_DMA_PREP_ADDR64(buf_phys));
816 buf_phys += MTK_WED_PAGE_BUF_SIZE;
817 desc++;
818 }
819
820 dma_sync_single_for_device(dev->hw->dev, page_phys, PAGE_SIZE,
821 DMA_BIDIRECTIONAL);
822 }
823
824 return 0;
825 }
826
827 static int
mtk_wed_rx_buffer_alloc(struct mtk_wed_device * dev)828 mtk_wed_rx_buffer_alloc(struct mtk_wed_device *dev)
829 {
830 struct mtk_wed_bm_desc *desc;
831 dma_addr_t desc_phys;
832
833 dev->rx_buf_ring.size = dev->wlan.rx_nbuf;
834 desc = dma_alloc_coherent(dev->hw->dev,
835 dev->wlan.rx_nbuf * sizeof(*desc),
836 &desc_phys, GFP_KERNEL);
837 if (!desc)
838 return -ENOMEM;
839
840 dev->rx_buf_ring.desc = desc;
841 dev->rx_buf_ring.desc_phys = desc_phys;
842 dev->wlan.init_rx_buf(dev, dev->wlan.rx_npkt);
843
844 return mtk_wed_hwrro_buffer_alloc(dev);
845 }
846
847 static void
mtk_wed_hwrro_free_buffer(struct mtk_wed_device * dev)848 mtk_wed_hwrro_free_buffer(struct mtk_wed_device *dev)
849 {
850 struct mtk_wed_buf *page_list = dev->hw_rro.pages;
851 struct mtk_wed_bm_desc *desc = dev->hw_rro.desc;
852 int i, page_idx = 0;
853
854 if (!dev->wlan.hw_rro)
855 return;
856
857 if (!page_list)
858 return;
859
860 if (!desc)
861 goto free_pagelist;
862
863 for (i = 0; i < MTK_WED_RX_PG_BM_CNT; i += MTK_WED_RX_BUF_PER_PAGE) {
864 dma_addr_t buf_addr = page_list[page_idx].phy_addr;
865 void *page = page_list[page_idx++].p;
866
867 if (!page)
868 break;
869
870 dma_unmap_page(dev->hw->dev, buf_addr, PAGE_SIZE,
871 DMA_BIDIRECTIONAL);
872 __free_page(page);
873 }
874
875 dma_free_coherent(dev->hw->dev, dev->hw_rro.size * sizeof(*desc),
876 desc, dev->hw_rro.desc_phys);
877
878 free_pagelist:
879 kfree(page_list);
880 }
881
882 static void
mtk_wed_free_rx_buffer(struct mtk_wed_device * dev)883 mtk_wed_free_rx_buffer(struct mtk_wed_device *dev)
884 {
885 struct mtk_wed_bm_desc *desc = dev->rx_buf_ring.desc;
886
887 if (!desc)
888 return;
889
890 dev->wlan.release_rx_buf(dev);
891 dma_free_coherent(dev->hw->dev, dev->rx_buf_ring.size * sizeof(*desc),
892 desc, dev->rx_buf_ring.desc_phys);
893
894 mtk_wed_hwrro_free_buffer(dev);
895 }
896
897 static void
mtk_wed_hwrro_init(struct mtk_wed_device * dev)898 mtk_wed_hwrro_init(struct mtk_wed_device *dev)
899 {
900 if (!mtk_wed_get_rx_capa(dev) || !dev->wlan.hw_rro)
901 return;
902
903 wed_set(dev, MTK_WED_RRO_PG_BM_RX_DMAM,
904 FIELD_PREP(MTK_WED_RRO_PG_BM_RX_SDL0, 128));
905
906 wed_w32(dev, MTK_WED_RRO_PG_BM_BASE, dev->hw_rro.desc_phys);
907
908 wed_w32(dev, MTK_WED_RRO_PG_BM_INIT_PTR,
909 MTK_WED_RRO_PG_BM_INIT_SW_TAIL_IDX |
910 FIELD_PREP(MTK_WED_RRO_PG_BM_SW_TAIL_IDX,
911 MTK_WED_RX_PG_BM_CNT));
912
913 /* enable rx_page_bm to fetch dmad */
914 wed_set(dev, MTK_WED_CTRL, MTK_WED_CTRL_WED_RX_PG_BM_EN);
915 }
916
917 static void
mtk_wed_rx_buffer_hw_init(struct mtk_wed_device * dev)918 mtk_wed_rx_buffer_hw_init(struct mtk_wed_device *dev)
919 {
920 wed_w32(dev, MTK_WED_RX_BM_RX_DMAD,
921 FIELD_PREP(MTK_WED_RX_BM_RX_DMAD_SDL0, dev->wlan.rx_size));
922 wed_w32(dev, MTK_WED_RX_BM_BASE, dev->rx_buf_ring.desc_phys);
923 wed_w32(dev, MTK_WED_RX_BM_INIT_PTR, MTK_WED_RX_BM_INIT_SW_TAIL |
924 FIELD_PREP(MTK_WED_RX_BM_SW_TAIL, dev->wlan.rx_npkt));
925 wed_w32(dev, MTK_WED_RX_BM_DYN_ALLOC_TH,
926 FIELD_PREP(MTK_WED_RX_BM_DYN_ALLOC_TH_H, 0xffff));
927 wed_set(dev, MTK_WED_CTRL, MTK_WED_CTRL_WED_RX_BM_EN);
928
929 mtk_wed_hwrro_init(dev);
930 }
931
932 static void
mtk_wed_free_ring(struct mtk_wed_device * dev,struct mtk_wed_ring * ring)933 mtk_wed_free_ring(struct mtk_wed_device *dev, struct mtk_wed_ring *ring)
934 {
935 if (!ring->desc)
936 return;
937
938 dma_free_coherent(dev->hw->dev, ring->size * ring->desc_size,
939 ring->desc, ring->desc_phys);
940 }
941
942 static void
mtk_wed_free_rx_rings(struct mtk_wed_device * dev)943 mtk_wed_free_rx_rings(struct mtk_wed_device *dev)
944 {
945 mtk_wed_free_rx_buffer(dev);
946 mtk_wed_free_ring(dev, &dev->rro.ring);
947 }
948
949 static void
mtk_wed_free_tx_rings(struct mtk_wed_device * dev)950 mtk_wed_free_tx_rings(struct mtk_wed_device *dev)
951 {
952 int i;
953
954 for (i = 0; i < ARRAY_SIZE(dev->tx_ring); i++)
955 mtk_wed_free_ring(dev, &dev->tx_ring[i]);
956 for (i = 0; i < ARRAY_SIZE(dev->rx_wdma); i++)
957 mtk_wed_free_ring(dev, &dev->rx_wdma[i]);
958 }
959
960 static void
mtk_wed_set_ext_int(struct mtk_wed_device * dev,bool en)961 mtk_wed_set_ext_int(struct mtk_wed_device *dev, bool en)
962 {
963 u32 mask = MTK_WED_EXT_INT_STATUS_ERROR_MASK;
964
965 switch (dev->hw->version) {
966 case 1:
967 mask |= MTK_WED_EXT_INT_STATUS_TX_DRV_R_RESP_ERR;
968 break;
969 case 2:
970 mask |= MTK_WED_EXT_INT_STATUS_RX_FBUF_LO_TH |
971 MTK_WED_EXT_INT_STATUS_RX_FBUF_HI_TH |
972 MTK_WED_EXT_INT_STATUS_RX_DRV_COHERENT |
973 MTK_WED_EXT_INT_STATUS_TX_DMA_W_RESP_ERR;
974 break;
975 case 3:
976 mask = MTK_WED_EXT_INT_STATUS_RX_DRV_COHERENT |
977 MTK_WED_EXT_INT_STATUS_TKID_WO_PYLD;
978 break;
979 default:
980 break;
981 }
982
983 if (!dev->hw->num_flows)
984 mask &= ~MTK_WED_EXT_INT_STATUS_TKID_WO_PYLD;
985
986 wed_w32(dev, MTK_WED_EXT_INT_MASK, en ? mask : 0);
987 wed_r32(dev, MTK_WED_EXT_INT_MASK);
988 }
989
990 static void
mtk_wed_set_512_support(struct mtk_wed_device * dev,bool enable)991 mtk_wed_set_512_support(struct mtk_wed_device *dev, bool enable)
992 {
993 if (!mtk_wed_is_v2(dev->hw))
994 return;
995
996 if (enable) {
997 wed_w32(dev, MTK_WED_TXDP_CTRL, MTK_WED_TXDP_DW9_OVERWR);
998 wed_w32(dev, MTK_WED_TXP_DW1,
999 FIELD_PREP(MTK_WED_WPDMA_WRITE_TXP, 0x0103));
1000 } else {
1001 wed_w32(dev, MTK_WED_TXP_DW1,
1002 FIELD_PREP(MTK_WED_WPDMA_WRITE_TXP, 0x0100));
1003 wed_clr(dev, MTK_WED_TXDP_CTRL, MTK_WED_TXDP_DW9_OVERWR);
1004 }
1005 }
1006
1007 static int
mtk_wed_check_wfdma_rx_fill(struct mtk_wed_device * dev,struct mtk_wed_ring * ring)1008 mtk_wed_check_wfdma_rx_fill(struct mtk_wed_device *dev,
1009 struct mtk_wed_ring *ring)
1010 {
1011 int i;
1012
1013 for (i = 0; i < 3; i++) {
1014 u32 cur_idx = readl(ring->wpdma + MTK_WED_RING_OFS_CPU_IDX);
1015
1016 if (cur_idx == MTK_WED_RX_RING_SIZE - 1)
1017 break;
1018
1019 usleep_range(100000, 200000);
1020 }
1021
1022 if (i == 3) {
1023 dev_err(dev->hw->dev, "rx dma enable failed\n");
1024 return -ETIMEDOUT;
1025 }
1026
1027 return 0;
1028 }
1029
1030 static void
mtk_wed_dma_disable(struct mtk_wed_device * dev)1031 mtk_wed_dma_disable(struct mtk_wed_device *dev)
1032 {
1033 wed_clr(dev, MTK_WED_WPDMA_GLO_CFG,
1034 MTK_WED_WPDMA_GLO_CFG_TX_DRV_EN |
1035 MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN);
1036
1037 wed_clr(dev, MTK_WED_WDMA_GLO_CFG, MTK_WED_WDMA_GLO_CFG_RX_DRV_EN);
1038
1039 wed_clr(dev, MTK_WED_GLO_CFG,
1040 MTK_WED_GLO_CFG_TX_DMA_EN |
1041 MTK_WED_GLO_CFG_RX_DMA_EN);
1042
1043 wdma_clr(dev, MTK_WDMA_GLO_CFG,
1044 MTK_WDMA_GLO_CFG_TX_DMA_EN |
1045 MTK_WDMA_GLO_CFG_RX_INFO1_PRERES |
1046 MTK_WDMA_GLO_CFG_RX_INFO2_PRERES);
1047
1048 if (mtk_wed_is_v1(dev->hw)) {
1049 regmap_write(dev->hw->mirror, dev->hw->index * 4, 0);
1050 wdma_clr(dev, MTK_WDMA_GLO_CFG,
1051 MTK_WDMA_GLO_CFG_RX_INFO3_PRERES);
1052 } else {
1053 wed_clr(dev, MTK_WED_WPDMA_GLO_CFG,
1054 MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_PKT_PROC |
1055 MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_CRX_SYNC);
1056
1057 wed_clr(dev, MTK_WED_WPDMA_RX_D_GLO_CFG,
1058 MTK_WED_WPDMA_RX_D_RX_DRV_EN);
1059 wed_clr(dev, MTK_WED_WDMA_GLO_CFG,
1060 MTK_WED_WDMA_GLO_CFG_TX_DDONE_CHK);
1061
1062 if (mtk_wed_is_v3_or_greater(dev->hw) &&
1063 mtk_wed_get_rx_capa(dev)) {
1064 wdma_clr(dev, MTK_WDMA_PREF_TX_CFG,
1065 MTK_WDMA_PREF_TX_CFG_PREF_EN);
1066 wdma_clr(dev, MTK_WDMA_PREF_RX_CFG,
1067 MTK_WDMA_PREF_RX_CFG_PREF_EN);
1068 }
1069 }
1070
1071 mtk_wed_set_512_support(dev, false);
1072 }
1073
1074 static void
mtk_wed_stop(struct mtk_wed_device * dev)1075 mtk_wed_stop(struct mtk_wed_device *dev)
1076 {
1077 mtk_wed_dma_disable(dev);
1078 mtk_wed_set_ext_int(dev, false);
1079
1080 wed_w32(dev, MTK_WED_WPDMA_INT_TRIGGER, 0);
1081 wed_w32(dev, MTK_WED_WDMA_INT_TRIGGER, 0);
1082 wdma_w32(dev, MTK_WDMA_INT_MASK, 0);
1083 wdma_w32(dev, MTK_WDMA_INT_GRP2, 0);
1084
1085 if (!mtk_wed_get_rx_capa(dev))
1086 return;
1087
1088 wed_w32(dev, MTK_WED_EXT_INT_MASK1, 0);
1089 wed_w32(dev, MTK_WED_EXT_INT_MASK2, 0);
1090 }
1091
1092 static void
mtk_wed_deinit(struct mtk_wed_device * dev)1093 mtk_wed_deinit(struct mtk_wed_device *dev)
1094 {
1095 mtk_wed_stop(dev);
1096
1097 wed_clr(dev, MTK_WED_CTRL,
1098 MTK_WED_CTRL_WDMA_INT_AGENT_EN |
1099 MTK_WED_CTRL_WPDMA_INT_AGENT_EN |
1100 MTK_WED_CTRL_WED_TX_BM_EN |
1101 MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
1102
1103 if (mtk_wed_is_v1(dev->hw))
1104 return;
1105
1106 wed_clr(dev, MTK_WED_CTRL,
1107 MTK_WED_CTRL_RX_ROUTE_QM_EN |
1108 MTK_WED_CTRL_WED_RX_BM_EN |
1109 MTK_WED_CTRL_RX_RRO_QM_EN);
1110
1111 if (mtk_wed_is_v3_or_greater(dev->hw)) {
1112 wed_clr(dev, MTK_WED_CTRL, MTK_WED_CTRL_TX_AMSDU_EN);
1113 wed_clr(dev, MTK_WED_RESET, MTK_WED_RESET_TX_AMSDU);
1114 wed_clr(dev, MTK_WED_PCIE_INT_CTRL,
1115 MTK_WED_PCIE_INT_CTRL_MSK_EN_POLA |
1116 MTK_WED_PCIE_INT_CTRL_MSK_IRQ_FILTER);
1117 }
1118 }
1119
1120 static void
__mtk_wed_detach(struct mtk_wed_device * dev)1121 __mtk_wed_detach(struct mtk_wed_device *dev)
1122 {
1123 struct mtk_wed_hw *hw = dev->hw;
1124
1125 mtk_wed_deinit(dev);
1126
1127 mtk_wdma_rx_reset(dev);
1128 mtk_wed_reset(dev, MTK_WED_RESET_WED);
1129 mtk_wed_amsdu_free_buffer(dev);
1130 mtk_wed_free_tx_buffer(dev);
1131 mtk_wed_free_tx_rings(dev);
1132
1133 if (mtk_wed_get_rx_capa(dev)) {
1134 if (hw->wed_wo)
1135 mtk_wed_wo_reset(dev);
1136 mtk_wed_free_rx_rings(dev);
1137 if (hw->wed_wo)
1138 mtk_wed_wo_deinit(hw);
1139 }
1140
1141 if (dev->wlan.bus_type == MTK_WED_BUS_PCIE) {
1142 struct device_node *wlan_node;
1143
1144 wlan_node = dev->wlan.pci_dev->dev.of_node;
1145 if (of_dma_is_coherent(wlan_node) && hw->hifsys)
1146 regmap_update_bits(hw->hifsys, HIFSYS_DMA_AG_MAP,
1147 BIT(hw->index), BIT(hw->index));
1148 }
1149
1150 if ((!hw_list[!hw->index] || !hw_list[!hw->index]->wed_dev) &&
1151 hw->eth->dma_dev != hw->eth->dev)
1152 mtk_eth_set_dma_device(hw->eth, hw->eth->dev);
1153
1154 memset(dev, 0, sizeof(*dev));
1155 module_put(THIS_MODULE);
1156
1157 hw->wed_dev = NULL;
1158 }
1159
1160 static void
mtk_wed_detach(struct mtk_wed_device * dev)1161 mtk_wed_detach(struct mtk_wed_device *dev)
1162 {
1163 mutex_lock(&hw_lock);
1164 __mtk_wed_detach(dev);
1165 mutex_unlock(&hw_lock);
1166 }
1167
1168 static void
mtk_wed_bus_init(struct mtk_wed_device * dev)1169 mtk_wed_bus_init(struct mtk_wed_device *dev)
1170 {
1171 switch (dev->wlan.bus_type) {
1172 case MTK_WED_BUS_PCIE: {
1173 struct device_node *np = dev->hw->eth->dev->of_node;
1174
1175 if (mtk_wed_is_v2(dev->hw)) {
1176 struct regmap *regs;
1177
1178 regs = syscon_regmap_lookup_by_phandle(np,
1179 "mediatek,wed-pcie");
1180 if (IS_ERR(regs))
1181 break;
1182
1183 regmap_update_bits(regs, 0, BIT(0), BIT(0));
1184 }
1185
1186 if (dev->wlan.msi) {
1187 wed_w32(dev, MTK_WED_PCIE_CFG_INTM,
1188 dev->hw->pcie_base | 0xc08);
1189 wed_w32(dev, MTK_WED_PCIE_CFG_BASE,
1190 dev->hw->pcie_base | 0xc04);
1191 wed_w32(dev, MTK_WED_PCIE_INT_TRIGGER, BIT(8));
1192 } else {
1193 wed_w32(dev, MTK_WED_PCIE_CFG_INTM,
1194 dev->hw->pcie_base | 0x180);
1195 wed_w32(dev, MTK_WED_PCIE_CFG_BASE,
1196 dev->hw->pcie_base | 0x184);
1197 wed_w32(dev, MTK_WED_PCIE_INT_TRIGGER, BIT(24));
1198 }
1199
1200 wed_w32(dev, MTK_WED_PCIE_INT_CTRL,
1201 FIELD_PREP(MTK_WED_PCIE_INT_CTRL_POLL_EN, 2));
1202
1203 /* pcie interrupt control: pola/source selection */
1204 wed_set(dev, MTK_WED_PCIE_INT_CTRL,
1205 MTK_WED_PCIE_INT_CTRL_MSK_EN_POLA |
1206 MTK_WED_PCIE_INT_CTRL_MSK_IRQ_FILTER |
1207 FIELD_PREP(MTK_WED_PCIE_INT_CTRL_SRC_SEL,
1208 dev->hw->index));
1209 break;
1210 }
1211 case MTK_WED_BUS_AXI:
1212 wed_set(dev, MTK_WED_WPDMA_INT_CTRL,
1213 MTK_WED_WPDMA_INT_CTRL_SIG_SRC |
1214 FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_SRC_SEL, 0));
1215 break;
1216 default:
1217 break;
1218 }
1219 }
1220
1221 static void
mtk_wed_set_wpdma(struct mtk_wed_device * dev)1222 mtk_wed_set_wpdma(struct mtk_wed_device *dev)
1223 {
1224 int i;
1225
1226 if (mtk_wed_is_v1(dev->hw)) {
1227 wed_w32(dev, MTK_WED_WPDMA_CFG_BASE, dev->wlan.wpdma_phys);
1228 return;
1229 }
1230
1231 mtk_wed_bus_init(dev);
1232
1233 wed_w32(dev, MTK_WED_WPDMA_CFG_BASE, dev->wlan.wpdma_int);
1234 wed_w32(dev, MTK_WED_WPDMA_CFG_INT_MASK, dev->wlan.wpdma_mask);
1235 wed_w32(dev, MTK_WED_WPDMA_CFG_TX, dev->wlan.wpdma_tx);
1236 wed_w32(dev, MTK_WED_WPDMA_CFG_TX_FREE, dev->wlan.wpdma_txfree);
1237
1238 if (!mtk_wed_get_rx_capa(dev))
1239 return;
1240
1241 wed_w32(dev, MTK_WED_WPDMA_RX_GLO_CFG, dev->wlan.wpdma_rx_glo);
1242 wed_w32(dev, dev->hw->soc->regmap.wpdma_rx_ring0, dev->wlan.wpdma_rx);
1243
1244 if (!dev->wlan.hw_rro)
1245 return;
1246
1247 wed_w32(dev, MTK_WED_RRO_RX_D_CFG(0), dev->wlan.wpdma_rx_rro[0]);
1248 wed_w32(dev, MTK_WED_RRO_RX_D_CFG(1), dev->wlan.wpdma_rx_rro[1]);
1249 for (i = 0; i < MTK_WED_RX_PAGE_QUEUES; i++)
1250 wed_w32(dev, MTK_WED_RRO_MSDU_PG_RING_CFG(i),
1251 dev->wlan.wpdma_rx_pg + i * 0x10);
1252 }
1253
1254 static void
mtk_wed_hw_init_early(struct mtk_wed_device * dev)1255 mtk_wed_hw_init_early(struct mtk_wed_device *dev)
1256 {
1257 u32 set = FIELD_PREP(MTK_WED_WDMA_GLO_CFG_BT_SIZE, 2);
1258 u32 mask = MTK_WED_WDMA_GLO_CFG_BT_SIZE;
1259
1260 mtk_wed_deinit(dev);
1261 mtk_wed_reset(dev, MTK_WED_RESET_WED);
1262 mtk_wed_set_wpdma(dev);
1263
1264 if (!mtk_wed_is_v3_or_greater(dev->hw)) {
1265 mask |= MTK_WED_WDMA_GLO_CFG_DYNAMIC_DMAD_RECYCLE |
1266 MTK_WED_WDMA_GLO_CFG_RX_DIS_FSM_AUTO_IDLE;
1267 set |= MTK_WED_WDMA_GLO_CFG_DYNAMIC_SKIP_DMAD_PREP |
1268 MTK_WED_WDMA_GLO_CFG_IDLE_DMAD_SUPPLY;
1269 }
1270 wed_m32(dev, MTK_WED_WDMA_GLO_CFG, mask, set);
1271
1272 if (mtk_wed_is_v1(dev->hw)) {
1273 u32 offset = dev->hw->index ? 0x04000400 : 0;
1274
1275 wdma_set(dev, MTK_WDMA_GLO_CFG,
1276 MTK_WDMA_GLO_CFG_RX_INFO1_PRERES |
1277 MTK_WDMA_GLO_CFG_RX_INFO2_PRERES |
1278 MTK_WDMA_GLO_CFG_RX_INFO3_PRERES);
1279
1280 wed_w32(dev, MTK_WED_WDMA_OFFSET0, 0x2a042a20 + offset);
1281 wed_w32(dev, MTK_WED_WDMA_OFFSET1, 0x29002800 + offset);
1282 wed_w32(dev, MTK_WED_PCIE_CFG_BASE,
1283 MTK_PCIE_BASE(dev->hw->index));
1284 } else {
1285 wed_w32(dev, MTK_WED_WDMA_CFG_BASE, dev->hw->wdma_phy);
1286 wed_set(dev, MTK_WED_CTRL, MTK_WED_CTRL_ETH_DMAD_FMT);
1287 wed_w32(dev, MTK_WED_WDMA_OFFSET0,
1288 FIELD_PREP(MTK_WED_WDMA_OFST0_GLO_INTS,
1289 MTK_WDMA_INT_STATUS) |
1290 FIELD_PREP(MTK_WED_WDMA_OFST0_GLO_CFG,
1291 MTK_WDMA_GLO_CFG));
1292
1293 wed_w32(dev, MTK_WED_WDMA_OFFSET1,
1294 FIELD_PREP(MTK_WED_WDMA_OFST1_TX_CTRL,
1295 MTK_WDMA_RING_TX(0)) |
1296 FIELD_PREP(MTK_WED_WDMA_OFST1_RX_CTRL,
1297 MTK_WDMA_RING_RX(0)));
1298 }
1299 }
1300
1301 static int
mtk_wed_rro_ring_alloc(struct mtk_wed_device * dev,struct mtk_wed_ring * ring,int size)1302 mtk_wed_rro_ring_alloc(struct mtk_wed_device *dev, struct mtk_wed_ring *ring,
1303 int size)
1304 {
1305 ring->desc = dma_alloc_coherent(dev->hw->dev,
1306 size * sizeof(*ring->desc),
1307 &ring->desc_phys, GFP_KERNEL);
1308 if (!ring->desc)
1309 return -ENOMEM;
1310
1311 ring->desc_size = sizeof(*ring->desc);
1312 ring->size = size;
1313
1314 return 0;
1315 }
1316
1317 #define MTK_WED_MIOD_COUNT (MTK_WED_MIOD_ENTRY_CNT * MTK_WED_MIOD_CNT)
1318 static int
mtk_wed_rro_alloc(struct mtk_wed_device * dev)1319 mtk_wed_rro_alloc(struct mtk_wed_device *dev)
1320 {
1321 struct resource res;
1322 int ret;
1323
1324 ret = of_reserved_mem_region_to_resource_byname(dev->hw->node, "wo-dlm", &res);
1325 if (ret)
1326 return ret;
1327
1328 dev->rro.miod_phys = res.start;
1329 dev->rro.fdbk_phys = MTK_WED_MIOD_COUNT + dev->rro.miod_phys;
1330
1331 return mtk_wed_rro_ring_alloc(dev, &dev->rro.ring,
1332 MTK_WED_RRO_QUE_CNT);
1333 }
1334
1335 static int
mtk_wed_rro_cfg(struct mtk_wed_device * dev)1336 mtk_wed_rro_cfg(struct mtk_wed_device *dev)
1337 {
1338 struct mtk_wed_wo *wo = dev->hw->wed_wo;
1339 struct {
1340 struct {
1341 __le32 base;
1342 __le32 cnt;
1343 __le32 unit;
1344 } ring[2];
1345 __le32 wed;
1346 u8 version;
1347 } req = {
1348 .ring[0] = {
1349 .base = cpu_to_le32(MTK_WED_WOCPU_VIEW_MIOD_BASE),
1350 .cnt = cpu_to_le32(MTK_WED_MIOD_CNT),
1351 .unit = cpu_to_le32(MTK_WED_MIOD_ENTRY_CNT),
1352 },
1353 .ring[1] = {
1354 .base = cpu_to_le32(MTK_WED_WOCPU_VIEW_MIOD_BASE +
1355 MTK_WED_MIOD_COUNT),
1356 .cnt = cpu_to_le32(MTK_WED_FB_CMD_CNT),
1357 .unit = cpu_to_le32(4),
1358 },
1359 };
1360
1361 return mtk_wed_mcu_send_msg(wo, MTK_WED_MODULE_ID_WO,
1362 MTK_WED_WO_CMD_WED_CFG,
1363 &req, sizeof(req), true);
1364 }
1365
1366 static void
mtk_wed_rro_hw_init(struct mtk_wed_device * dev)1367 mtk_wed_rro_hw_init(struct mtk_wed_device *dev)
1368 {
1369 wed_w32(dev, MTK_WED_RROQM_MIOD_CFG,
1370 FIELD_PREP(MTK_WED_RROQM_MIOD_MID_DW, 0x70 >> 2) |
1371 FIELD_PREP(MTK_WED_RROQM_MIOD_MOD_DW, 0x10 >> 2) |
1372 FIELD_PREP(MTK_WED_RROQM_MIOD_ENTRY_DW,
1373 MTK_WED_MIOD_ENTRY_CNT >> 2));
1374
1375 wed_w32(dev, MTK_WED_RROQM_MIOD_CTRL0, dev->rro.miod_phys);
1376 wed_w32(dev, MTK_WED_RROQM_MIOD_CTRL1,
1377 FIELD_PREP(MTK_WED_RROQM_MIOD_CNT, MTK_WED_MIOD_CNT));
1378 wed_w32(dev, MTK_WED_RROQM_FDBK_CTRL0, dev->rro.fdbk_phys);
1379 wed_w32(dev, MTK_WED_RROQM_FDBK_CTRL1,
1380 FIELD_PREP(MTK_WED_RROQM_FDBK_CNT, MTK_WED_FB_CMD_CNT));
1381 wed_w32(dev, MTK_WED_RROQM_FDBK_CTRL2, 0);
1382 wed_w32(dev, MTK_WED_RROQ_BASE_L, dev->rro.ring.desc_phys);
1383
1384 wed_set(dev, MTK_WED_RROQM_RST_IDX,
1385 MTK_WED_RROQM_RST_IDX_MIOD |
1386 MTK_WED_RROQM_RST_IDX_FDBK);
1387
1388 wed_w32(dev, MTK_WED_RROQM_RST_IDX, 0);
1389 wed_w32(dev, MTK_WED_RROQM_MIOD_CTRL2, MTK_WED_MIOD_CNT - 1);
1390 wed_set(dev, MTK_WED_CTRL, MTK_WED_CTRL_RX_RRO_QM_EN);
1391 }
1392
1393 static void
mtk_wed_route_qm_hw_init(struct mtk_wed_device * dev)1394 mtk_wed_route_qm_hw_init(struct mtk_wed_device *dev)
1395 {
1396 wed_w32(dev, MTK_WED_RESET, MTK_WED_RESET_RX_ROUTE_QM);
1397
1398 for (;;) {
1399 usleep_range(100, 200);
1400 if (!(wed_r32(dev, MTK_WED_RESET) & MTK_WED_RESET_RX_ROUTE_QM))
1401 break;
1402 }
1403
1404 /* configure RX_ROUTE_QM */
1405 if (mtk_wed_is_v2(dev->hw)) {
1406 wed_clr(dev, MTK_WED_RTQM_GLO_CFG, MTK_WED_RTQM_Q_RST);
1407 wed_clr(dev, MTK_WED_RTQM_GLO_CFG, MTK_WED_RTQM_TXDMAD_FPORT);
1408 wed_set(dev, MTK_WED_RTQM_GLO_CFG,
1409 FIELD_PREP(MTK_WED_RTQM_TXDMAD_FPORT,
1410 0x3 + dev->hw->index));
1411 wed_clr(dev, MTK_WED_RTQM_GLO_CFG, MTK_WED_RTQM_Q_RST);
1412 } else {
1413 wed_set(dev, MTK_WED_RTQM_ENQ_CFG0,
1414 FIELD_PREP(MTK_WED_RTQM_ENQ_CFG_TXDMAD_FPORT,
1415 0x3 + dev->hw->index));
1416 }
1417 /* enable RX_ROUTE_QM */
1418 wed_set(dev, MTK_WED_CTRL, MTK_WED_CTRL_RX_ROUTE_QM_EN);
1419 }
1420
1421 static void
mtk_wed_hw_init(struct mtk_wed_device * dev)1422 mtk_wed_hw_init(struct mtk_wed_device *dev)
1423 {
1424 if (dev->init_done)
1425 return;
1426
1427 dev->init_done = true;
1428 mtk_wed_set_ext_int(dev, false);
1429
1430 wed_w32(dev, MTK_WED_TX_BM_BASE, dev->tx_buf_ring.desc_phys);
1431 wed_w32(dev, MTK_WED_TX_BM_BUF_LEN, MTK_WED_PKT_SIZE);
1432
1433 if (mtk_wed_is_v1(dev->hw)) {
1434 wed_w32(dev, MTK_WED_TX_BM_CTRL,
1435 MTK_WED_TX_BM_CTRL_PAUSE |
1436 FIELD_PREP(MTK_WED_TX_BM_CTRL_VLD_GRP_NUM,
1437 dev->tx_buf_ring.size / 128) |
1438 FIELD_PREP(MTK_WED_TX_BM_CTRL_RSV_GRP_NUM,
1439 MTK_WED_TX_RING_SIZE / 256));
1440 wed_w32(dev, MTK_WED_TX_BM_DYN_THR,
1441 FIELD_PREP(MTK_WED_TX_BM_DYN_THR_LO, 1) |
1442 MTK_WED_TX_BM_DYN_THR_HI);
1443 } else if (mtk_wed_is_v2(dev->hw)) {
1444 wed_w32(dev, MTK_WED_TX_BM_CTRL,
1445 MTK_WED_TX_BM_CTRL_PAUSE |
1446 FIELD_PREP(MTK_WED_TX_BM_CTRL_VLD_GRP_NUM,
1447 dev->tx_buf_ring.size / 128) |
1448 FIELD_PREP(MTK_WED_TX_BM_CTRL_RSV_GRP_NUM,
1449 MTK_WED_TX_RING_SIZE / 256));
1450 wed_w32(dev, MTK_WED_TX_TKID_DYN_THR,
1451 FIELD_PREP(MTK_WED_TX_TKID_DYN_THR_LO, 0) |
1452 MTK_WED_TX_TKID_DYN_THR_HI);
1453 wed_w32(dev, MTK_WED_TX_BM_DYN_THR,
1454 FIELD_PREP(MTK_WED_TX_BM_DYN_THR_LO_V2, 0) |
1455 MTK_WED_TX_BM_DYN_THR_HI_V2);
1456 wed_w32(dev, MTK_WED_TX_TKID_CTRL,
1457 MTK_WED_TX_TKID_CTRL_PAUSE |
1458 FIELD_PREP(MTK_WED_TX_TKID_CTRL_VLD_GRP_NUM,
1459 dev->tx_buf_ring.size / 128) |
1460 FIELD_PREP(MTK_WED_TX_TKID_CTRL_RSV_GRP_NUM,
1461 dev->tx_buf_ring.size / 128));
1462 }
1463
1464 wed_w32(dev, dev->hw->soc->regmap.tx_bm_tkid,
1465 FIELD_PREP(MTK_WED_TX_BM_TKID_START, dev->wlan.token_start) |
1466 FIELD_PREP(MTK_WED_TX_BM_TKID_END,
1467 dev->wlan.token_start + dev->wlan.nbuf - 1));
1468
1469 mtk_wed_reset(dev, MTK_WED_RESET_TX_BM);
1470
1471 if (mtk_wed_is_v3_or_greater(dev->hw)) {
1472 /* switch to new bm architecture */
1473 wed_clr(dev, MTK_WED_TX_BM_CTRL,
1474 MTK_WED_TX_BM_CTRL_LEGACY_EN);
1475
1476 wed_w32(dev, MTK_WED_TX_TKID_CTRL,
1477 MTK_WED_TX_TKID_CTRL_PAUSE |
1478 FIELD_PREP(MTK_WED_TX_TKID_CTRL_VLD_GRP_NUM_V3,
1479 dev->wlan.nbuf / 128) |
1480 FIELD_PREP(MTK_WED_TX_TKID_CTRL_RSV_GRP_NUM_V3,
1481 dev->wlan.nbuf / 128));
1482 /* return SKBID + SDP back to bm */
1483 wed_set(dev, MTK_WED_TX_TKID_CTRL,
1484 MTK_WED_TX_TKID_CTRL_FREE_FORMAT);
1485
1486 wed_w32(dev, MTK_WED_TX_BM_INIT_PTR,
1487 MTK_WED_TX_BM_PKT_CNT |
1488 MTK_WED_TX_BM_INIT_SW_TAIL_IDX);
1489 }
1490
1491 if (mtk_wed_is_v1(dev->hw)) {
1492 wed_set(dev, MTK_WED_CTRL,
1493 MTK_WED_CTRL_WED_TX_BM_EN |
1494 MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
1495 } else if (mtk_wed_get_rx_capa(dev)) {
1496 /* rx hw init */
1497 wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX,
1498 MTK_WED_WPDMA_RX_D_RST_CRX_IDX |
1499 MTK_WED_WPDMA_RX_D_RST_DRV_IDX);
1500 wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX, 0);
1501
1502 /* reset prefetch index of ring */
1503 wed_set(dev, MTK_WED_WPDMA_RX_D_PREF_RX0_SIDX,
1504 MTK_WED_WPDMA_RX_D_PREF_SIDX_IDX_CLR);
1505 wed_clr(dev, MTK_WED_WPDMA_RX_D_PREF_RX0_SIDX,
1506 MTK_WED_WPDMA_RX_D_PREF_SIDX_IDX_CLR);
1507
1508 wed_set(dev, MTK_WED_WPDMA_RX_D_PREF_RX1_SIDX,
1509 MTK_WED_WPDMA_RX_D_PREF_SIDX_IDX_CLR);
1510 wed_clr(dev, MTK_WED_WPDMA_RX_D_PREF_RX1_SIDX,
1511 MTK_WED_WPDMA_RX_D_PREF_SIDX_IDX_CLR);
1512
1513 /* reset prefetch FIFO of ring */
1514 wed_set(dev, MTK_WED_WPDMA_RX_D_PREF_FIFO_CFG,
1515 MTK_WED_WPDMA_RX_D_PREF_FIFO_CFG_R0_CLR |
1516 MTK_WED_WPDMA_RX_D_PREF_FIFO_CFG_R1_CLR);
1517 wed_w32(dev, MTK_WED_WPDMA_RX_D_PREF_FIFO_CFG, 0);
1518
1519 mtk_wed_rx_buffer_hw_init(dev);
1520 mtk_wed_rro_hw_init(dev);
1521 mtk_wed_route_qm_hw_init(dev);
1522 }
1523
1524 wed_clr(dev, MTK_WED_TX_BM_CTRL, MTK_WED_TX_BM_CTRL_PAUSE);
1525 if (!mtk_wed_is_v1(dev->hw))
1526 wed_clr(dev, MTK_WED_TX_TKID_CTRL, MTK_WED_TX_TKID_CTRL_PAUSE);
1527 }
1528
1529 static void
mtk_wed_ring_reset(struct mtk_wed_ring * ring,int size,bool tx)1530 mtk_wed_ring_reset(struct mtk_wed_ring *ring, int size, bool tx)
1531 {
1532 void *head = (void *)ring->desc;
1533 int i;
1534
1535 for (i = 0; i < size; i++) {
1536 struct mtk_wdma_desc *desc;
1537
1538 desc = (struct mtk_wdma_desc *)(head + i * ring->desc_size);
1539 desc->buf0 = 0;
1540 if (tx)
1541 desc->ctrl = cpu_to_le32(MTK_WDMA_DESC_CTRL_DMA_DONE);
1542 else
1543 desc->ctrl = cpu_to_le32(MTK_WFDMA_DESC_CTRL_TO_HOST);
1544 desc->buf1 = 0;
1545 desc->info = 0;
1546 }
1547 }
1548
1549 static int
mtk_wed_rx_reset(struct mtk_wed_device * dev)1550 mtk_wed_rx_reset(struct mtk_wed_device *dev)
1551 {
1552 struct mtk_wed_wo *wo = dev->hw->wed_wo;
1553 u8 val = MTK_WED_WO_STATE_SER_RESET;
1554 int i, ret;
1555
1556 ret = mtk_wed_mcu_send_msg(wo, MTK_WED_MODULE_ID_WO,
1557 MTK_WED_WO_CMD_CHANGE_STATE, &val,
1558 sizeof(val), true);
1559 if (ret)
1560 return ret;
1561
1562 if (dev->wlan.hw_rro) {
1563 wed_clr(dev, MTK_WED_CTRL, MTK_WED_CTRL_WED_RX_IND_CMD_EN);
1564 mtk_wed_poll_busy(dev, MTK_WED_RRO_RX_HW_STS,
1565 MTK_WED_RX_IND_CMD_BUSY);
1566 mtk_wed_reset(dev, MTK_WED_RESET_RRO_RX_TO_PG);
1567 }
1568
1569 wed_clr(dev, MTK_WED_WPDMA_RX_D_GLO_CFG, MTK_WED_WPDMA_RX_D_RX_DRV_EN);
1570 ret = mtk_wed_poll_busy(dev, MTK_WED_WPDMA_RX_D_GLO_CFG,
1571 MTK_WED_WPDMA_RX_D_RX_DRV_BUSY);
1572 if (!ret && mtk_wed_is_v3_or_greater(dev->hw))
1573 ret = mtk_wed_poll_busy(dev, MTK_WED_WPDMA_RX_D_PREF_CFG,
1574 MTK_WED_WPDMA_RX_D_PREF_BUSY);
1575 if (ret) {
1576 mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_INT_AGENT);
1577 mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_RX_D_DRV);
1578 } else {
1579 if (mtk_wed_is_v3_or_greater(dev->hw)) {
1580 /* 1.a. disable prefetch HW */
1581 wed_clr(dev, MTK_WED_WPDMA_RX_D_PREF_CFG,
1582 MTK_WED_WPDMA_RX_D_PREF_EN);
1583 mtk_wed_poll_busy(dev, MTK_WED_WPDMA_RX_D_PREF_CFG,
1584 MTK_WED_WPDMA_RX_D_PREF_BUSY);
1585 wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX,
1586 MTK_WED_WPDMA_RX_D_RST_DRV_IDX_ALL);
1587 }
1588
1589 wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX,
1590 MTK_WED_WPDMA_RX_D_RST_CRX_IDX |
1591 MTK_WED_WPDMA_RX_D_RST_DRV_IDX);
1592
1593 wed_set(dev, MTK_WED_WPDMA_RX_D_GLO_CFG,
1594 MTK_WED_WPDMA_RX_D_RST_INIT_COMPLETE |
1595 MTK_WED_WPDMA_RX_D_FSM_RETURN_IDLE);
1596 wed_clr(dev, MTK_WED_WPDMA_RX_D_GLO_CFG,
1597 MTK_WED_WPDMA_RX_D_RST_INIT_COMPLETE |
1598 MTK_WED_WPDMA_RX_D_FSM_RETURN_IDLE);
1599
1600 wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX, 0);
1601 }
1602
1603 /* reset rro qm */
1604 wed_clr(dev, MTK_WED_CTRL, MTK_WED_CTRL_RX_RRO_QM_EN);
1605 ret = mtk_wed_poll_busy(dev, MTK_WED_CTRL,
1606 MTK_WED_CTRL_RX_RRO_QM_BUSY);
1607 if (ret) {
1608 mtk_wed_reset(dev, MTK_WED_RESET_RX_RRO_QM);
1609 } else {
1610 wed_set(dev, MTK_WED_RROQM_RST_IDX,
1611 MTK_WED_RROQM_RST_IDX_MIOD |
1612 MTK_WED_RROQM_RST_IDX_FDBK);
1613 wed_w32(dev, MTK_WED_RROQM_RST_IDX, 0);
1614 }
1615
1616 if (dev->wlan.hw_rro) {
1617 /* disable rro msdu page drv */
1618 wed_clr(dev, MTK_WED_RRO_MSDU_PG_RING2_CFG,
1619 MTK_WED_RRO_MSDU_PG_DRV_EN);
1620
1621 /* disable rro data drv */
1622 wed_clr(dev, MTK_WED_RRO_RX_D_CFG(2), MTK_WED_RRO_RX_D_DRV_EN);
1623
1624 /* rro msdu page drv reset */
1625 wed_w32(dev, MTK_WED_RRO_MSDU_PG_RING2_CFG,
1626 MTK_WED_RRO_MSDU_PG_DRV_CLR);
1627 mtk_wed_poll_busy(dev, MTK_WED_RRO_MSDU_PG_RING2_CFG,
1628 MTK_WED_RRO_MSDU_PG_DRV_CLR);
1629
1630 /* rro data drv reset */
1631 wed_w32(dev, MTK_WED_RRO_RX_D_CFG(2),
1632 MTK_WED_RRO_RX_D_DRV_CLR);
1633 mtk_wed_poll_busy(dev, MTK_WED_RRO_RX_D_CFG(2),
1634 MTK_WED_RRO_RX_D_DRV_CLR);
1635 }
1636
1637 /* reset route qm */
1638 wed_clr(dev, MTK_WED_CTRL, MTK_WED_CTRL_RX_ROUTE_QM_EN);
1639 ret = mtk_wed_poll_busy(dev, MTK_WED_CTRL,
1640 MTK_WED_CTRL_RX_ROUTE_QM_BUSY);
1641 if (ret) {
1642 mtk_wed_reset(dev, MTK_WED_RESET_RX_ROUTE_QM);
1643 } else if (mtk_wed_is_v3_or_greater(dev->hw)) {
1644 wed_set(dev, MTK_WED_RTQM_RST, BIT(0));
1645 wed_clr(dev, MTK_WED_RTQM_RST, BIT(0));
1646 mtk_wed_reset(dev, MTK_WED_RESET_RX_ROUTE_QM);
1647 } else {
1648 wed_set(dev, MTK_WED_RTQM_GLO_CFG, MTK_WED_RTQM_Q_RST);
1649 }
1650
1651 /* reset tx wdma */
1652 mtk_wdma_tx_reset(dev);
1653
1654 /* reset tx wdma drv */
1655 wed_clr(dev, MTK_WED_WDMA_GLO_CFG, MTK_WED_WDMA_GLO_CFG_TX_DRV_EN);
1656 if (mtk_wed_is_v3_or_greater(dev->hw))
1657 mtk_wed_poll_busy(dev, MTK_WED_WPDMA_STATUS,
1658 MTK_WED_WPDMA_STATUS_TX_DRV);
1659 else
1660 mtk_wed_poll_busy(dev, MTK_WED_CTRL,
1661 MTK_WED_CTRL_WDMA_INT_AGENT_BUSY);
1662 mtk_wed_reset(dev, MTK_WED_RESET_WDMA_TX_DRV);
1663
1664 /* reset wed rx dma */
1665 ret = mtk_wed_poll_busy(dev, MTK_WED_GLO_CFG,
1666 MTK_WED_GLO_CFG_RX_DMA_BUSY);
1667 wed_clr(dev, MTK_WED_GLO_CFG, MTK_WED_GLO_CFG_RX_DMA_EN);
1668 if (ret) {
1669 mtk_wed_reset(dev, MTK_WED_RESET_WED_RX_DMA);
1670 } else {
1671 wed_set(dev, MTK_WED_RESET_IDX,
1672 dev->hw->soc->regmap.reset_idx_rx_mask);
1673 wed_w32(dev, MTK_WED_RESET_IDX, 0);
1674 }
1675
1676 /* reset rx bm */
1677 wed_clr(dev, MTK_WED_CTRL, MTK_WED_CTRL_WED_RX_BM_EN);
1678 mtk_wed_poll_busy(dev, MTK_WED_CTRL,
1679 MTK_WED_CTRL_WED_RX_BM_BUSY);
1680 mtk_wed_reset(dev, MTK_WED_RESET_RX_BM);
1681
1682 if (dev->wlan.hw_rro) {
1683 wed_clr(dev, MTK_WED_CTRL, MTK_WED_CTRL_WED_RX_PG_BM_EN);
1684 mtk_wed_poll_busy(dev, MTK_WED_CTRL,
1685 MTK_WED_CTRL_WED_RX_PG_BM_BUSY);
1686 wed_set(dev, MTK_WED_RESET, MTK_WED_RESET_RX_PG_BM);
1687 wed_clr(dev, MTK_WED_RESET, MTK_WED_RESET_RX_PG_BM);
1688 }
1689
1690 /* wo change to enable state */
1691 val = MTK_WED_WO_STATE_ENABLE;
1692 ret = mtk_wed_mcu_send_msg(wo, MTK_WED_MODULE_ID_WO,
1693 MTK_WED_WO_CMD_CHANGE_STATE, &val,
1694 sizeof(val), true);
1695 if (ret)
1696 return ret;
1697
1698 /* wed_rx_ring_reset */
1699 for (i = 0; i < ARRAY_SIZE(dev->rx_ring); i++) {
1700 if (!dev->rx_ring[i].desc)
1701 continue;
1702
1703 mtk_wed_ring_reset(&dev->rx_ring[i], MTK_WED_RX_RING_SIZE,
1704 false);
1705 }
1706 mtk_wed_free_rx_buffer(dev);
1707 mtk_wed_hwrro_free_buffer(dev);
1708
1709 return 0;
1710 }
1711
1712 static void
mtk_wed_reset_dma(struct mtk_wed_device * dev)1713 mtk_wed_reset_dma(struct mtk_wed_device *dev)
1714 {
1715 bool busy = false;
1716 u32 val;
1717 int i;
1718
1719 for (i = 0; i < ARRAY_SIZE(dev->tx_ring); i++) {
1720 if (!dev->tx_ring[i].desc)
1721 continue;
1722
1723 mtk_wed_ring_reset(&dev->tx_ring[i], MTK_WED_TX_RING_SIZE,
1724 true);
1725 }
1726
1727 /* 1. reset WED tx DMA */
1728 wed_clr(dev, MTK_WED_GLO_CFG, MTK_WED_GLO_CFG_TX_DMA_EN);
1729 busy = mtk_wed_poll_busy(dev, MTK_WED_GLO_CFG,
1730 MTK_WED_GLO_CFG_TX_DMA_BUSY);
1731 if (busy) {
1732 mtk_wed_reset(dev, MTK_WED_RESET_WED_TX_DMA);
1733 } else {
1734 wed_w32(dev, MTK_WED_RESET_IDX,
1735 dev->hw->soc->regmap.reset_idx_tx_mask);
1736 wed_w32(dev, MTK_WED_RESET_IDX, 0);
1737 }
1738
1739 /* 2. reset WDMA rx DMA */
1740 busy = !!mtk_wdma_rx_reset(dev);
1741 if (mtk_wed_is_v3_or_greater(dev->hw)) {
1742 val = MTK_WED_WDMA_GLO_CFG_RX_DIS_FSM_AUTO_IDLE |
1743 wed_r32(dev, MTK_WED_WDMA_GLO_CFG);
1744 val &= ~MTK_WED_WDMA_GLO_CFG_RX_DRV_EN;
1745 wed_w32(dev, MTK_WED_WDMA_GLO_CFG, val);
1746 } else {
1747 wed_clr(dev, MTK_WED_WDMA_GLO_CFG,
1748 MTK_WED_WDMA_GLO_CFG_RX_DRV_EN);
1749 }
1750
1751 if (!busy)
1752 busy = mtk_wed_poll_busy(dev, MTK_WED_WDMA_GLO_CFG,
1753 MTK_WED_WDMA_GLO_CFG_RX_DRV_BUSY);
1754 if (!busy && mtk_wed_is_v3_or_greater(dev->hw))
1755 busy = mtk_wed_poll_busy(dev, MTK_WED_WDMA_RX_PREF_CFG,
1756 MTK_WED_WDMA_RX_PREF_BUSY);
1757
1758 if (busy) {
1759 mtk_wed_reset(dev, MTK_WED_RESET_WDMA_INT_AGENT);
1760 mtk_wed_reset(dev, MTK_WED_RESET_WDMA_RX_DRV);
1761 } else {
1762 if (mtk_wed_is_v3_or_greater(dev->hw)) {
1763 /* 1.a. disable prefetch HW */
1764 wed_clr(dev, MTK_WED_WDMA_RX_PREF_CFG,
1765 MTK_WED_WDMA_RX_PREF_EN);
1766 mtk_wed_poll_busy(dev, MTK_WED_WDMA_RX_PREF_CFG,
1767 MTK_WED_WDMA_RX_PREF_BUSY);
1768 wed_clr(dev, MTK_WED_WDMA_RX_PREF_CFG,
1769 MTK_WED_WDMA_RX_PREF_DDONE2_EN);
1770
1771 /* 2. Reset dma index */
1772 wed_w32(dev, MTK_WED_WDMA_RESET_IDX,
1773 MTK_WED_WDMA_RESET_IDX_RX_ALL);
1774 }
1775
1776 wed_w32(dev, MTK_WED_WDMA_RESET_IDX,
1777 MTK_WED_WDMA_RESET_IDX_RX | MTK_WED_WDMA_RESET_IDX_DRV);
1778 wed_w32(dev, MTK_WED_WDMA_RESET_IDX, 0);
1779
1780 wed_set(dev, MTK_WED_WDMA_GLO_CFG,
1781 MTK_WED_WDMA_GLO_CFG_RST_INIT_COMPLETE);
1782
1783 wed_clr(dev, MTK_WED_WDMA_GLO_CFG,
1784 MTK_WED_WDMA_GLO_CFG_RST_INIT_COMPLETE);
1785 }
1786
1787 /* 3. reset WED WPDMA tx */
1788 wed_clr(dev, MTK_WED_CTRL, MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
1789
1790 for (i = 0; i < 100; i++) {
1791 if (mtk_wed_is_v1(dev->hw))
1792 val = FIELD_GET(MTK_WED_TX_BM_INTF_TKFIFO_FDEP,
1793 wed_r32(dev, MTK_WED_TX_BM_INTF));
1794 else
1795 val = FIELD_GET(MTK_WED_TX_TKID_INTF_TKFIFO_FDEP,
1796 wed_r32(dev, MTK_WED_TX_TKID_INTF));
1797 if (val == 0x40)
1798 break;
1799 }
1800
1801 mtk_wed_reset(dev, MTK_WED_RESET_TX_FREE_AGENT);
1802 wed_clr(dev, MTK_WED_CTRL, MTK_WED_CTRL_WED_TX_BM_EN);
1803 mtk_wed_reset(dev, MTK_WED_RESET_TX_BM);
1804
1805 /* 4. reset WED WPDMA tx */
1806 busy = mtk_wed_poll_busy(dev, MTK_WED_WPDMA_GLO_CFG,
1807 MTK_WED_WPDMA_GLO_CFG_TX_DRV_BUSY);
1808 wed_clr(dev, MTK_WED_WPDMA_GLO_CFG,
1809 MTK_WED_WPDMA_GLO_CFG_TX_DRV_EN |
1810 MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN);
1811 if (!busy)
1812 busy = mtk_wed_poll_busy(dev, MTK_WED_WPDMA_GLO_CFG,
1813 MTK_WED_WPDMA_GLO_CFG_RX_DRV_BUSY);
1814
1815 if (busy) {
1816 mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_INT_AGENT);
1817 mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_TX_DRV);
1818 mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_RX_DRV);
1819 if (mtk_wed_is_v3_or_greater(dev->hw))
1820 wed_w32(dev, MTK_WED_RX1_CTRL2, 0);
1821 } else {
1822 wed_w32(dev, MTK_WED_WPDMA_RESET_IDX,
1823 MTK_WED_WPDMA_RESET_IDX_TX |
1824 MTK_WED_WPDMA_RESET_IDX_RX);
1825 wed_w32(dev, MTK_WED_WPDMA_RESET_IDX, 0);
1826 }
1827
1828 dev->init_done = false;
1829 if (mtk_wed_is_v1(dev->hw))
1830 return;
1831
1832 if (!busy) {
1833 wed_w32(dev, MTK_WED_RESET_IDX, MTK_WED_RESET_WPDMA_IDX_RX);
1834 wed_w32(dev, MTK_WED_RESET_IDX, 0);
1835 }
1836
1837 if (mtk_wed_is_v3_or_greater(dev->hw)) {
1838 /* reset amsdu engine */
1839 wed_clr(dev, MTK_WED_CTRL, MTK_WED_CTRL_TX_AMSDU_EN);
1840 mtk_wed_reset(dev, MTK_WED_RESET_TX_AMSDU);
1841 }
1842
1843 if (mtk_wed_get_rx_capa(dev))
1844 mtk_wed_rx_reset(dev);
1845 }
1846
1847 static int
mtk_wed_ring_alloc(struct mtk_wed_device * dev,struct mtk_wed_ring * ring,int size,u32 desc_size,bool tx)1848 mtk_wed_ring_alloc(struct mtk_wed_device *dev, struct mtk_wed_ring *ring,
1849 int size, u32 desc_size, bool tx)
1850 {
1851 ring->desc = dma_alloc_coherent(dev->hw->dev, size * desc_size,
1852 &ring->desc_phys, GFP_KERNEL);
1853 if (!ring->desc)
1854 return -ENOMEM;
1855
1856 ring->desc_size = desc_size;
1857 ring->size = size;
1858 mtk_wed_ring_reset(ring, size, tx);
1859
1860 return 0;
1861 }
1862
1863 static int
mtk_wed_wdma_rx_ring_setup(struct mtk_wed_device * dev,int idx,int size,bool reset)1864 mtk_wed_wdma_rx_ring_setup(struct mtk_wed_device *dev, int idx, int size,
1865 bool reset)
1866 {
1867 struct mtk_wed_ring *wdma;
1868
1869 if (idx >= ARRAY_SIZE(dev->rx_wdma))
1870 return -EINVAL;
1871
1872 wdma = &dev->rx_wdma[idx];
1873 if (!reset && mtk_wed_ring_alloc(dev, wdma, MTK_WED_WDMA_RING_SIZE,
1874 dev->hw->soc->wdma_desc_size, true))
1875 return -ENOMEM;
1876
1877 wdma_w32(dev, MTK_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_BASE,
1878 wdma->desc_phys);
1879 wdma_w32(dev, MTK_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_COUNT,
1880 size);
1881 wdma_w32(dev, MTK_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_CPU_IDX, 0);
1882
1883 wed_w32(dev, MTK_WED_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_BASE,
1884 wdma->desc_phys);
1885 wed_w32(dev, MTK_WED_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_COUNT,
1886 size);
1887
1888 return 0;
1889 }
1890
1891 static int
mtk_wed_wdma_tx_ring_setup(struct mtk_wed_device * dev,int idx,int size,bool reset)1892 mtk_wed_wdma_tx_ring_setup(struct mtk_wed_device *dev, int idx, int size,
1893 bool reset)
1894 {
1895 struct mtk_wed_ring *wdma;
1896
1897 if (idx >= ARRAY_SIZE(dev->tx_wdma))
1898 return -EINVAL;
1899
1900 wdma = &dev->tx_wdma[idx];
1901 if (!reset && mtk_wed_ring_alloc(dev, wdma, MTK_WED_WDMA_RING_SIZE,
1902 dev->hw->soc->wdma_desc_size, true))
1903 return -ENOMEM;
1904
1905 if (mtk_wed_is_v3_or_greater(dev->hw)) {
1906 struct mtk_wdma_desc *desc = wdma->desc;
1907 int i;
1908
1909 for (i = 0; i < MTK_WED_WDMA_RING_SIZE; i++) {
1910 desc->buf0 = 0;
1911 desc->ctrl = cpu_to_le32(MTK_WDMA_DESC_CTRL_DMA_DONE);
1912 desc->buf1 = 0;
1913 desc->info = cpu_to_le32(MTK_WDMA_TXD0_DESC_INFO_DMA_DONE);
1914 desc++;
1915 desc->buf0 = 0;
1916 desc->ctrl = cpu_to_le32(MTK_WDMA_DESC_CTRL_DMA_DONE);
1917 desc->buf1 = 0;
1918 desc->info = cpu_to_le32(MTK_WDMA_TXD1_DESC_INFO_DMA_DONE);
1919 desc++;
1920 }
1921 }
1922
1923 wdma_w32(dev, MTK_WDMA_RING_TX(idx) + MTK_WED_RING_OFS_BASE,
1924 wdma->desc_phys);
1925 wdma_w32(dev, MTK_WDMA_RING_TX(idx) + MTK_WED_RING_OFS_COUNT,
1926 size);
1927 wdma_w32(dev, MTK_WDMA_RING_TX(idx) + MTK_WED_RING_OFS_CPU_IDX, 0);
1928 wdma_w32(dev, MTK_WDMA_RING_TX(idx) + MTK_WED_RING_OFS_DMA_IDX, 0);
1929
1930 if (reset)
1931 mtk_wed_ring_reset(wdma, MTK_WED_WDMA_RING_SIZE, true);
1932
1933 if (!idx) {
1934 wed_w32(dev, MTK_WED_WDMA_RING_TX + MTK_WED_RING_OFS_BASE,
1935 wdma->desc_phys);
1936 wed_w32(dev, MTK_WED_WDMA_RING_TX + MTK_WED_RING_OFS_COUNT,
1937 size);
1938 wed_w32(dev, MTK_WED_WDMA_RING_TX + MTK_WED_RING_OFS_CPU_IDX,
1939 0);
1940 wed_w32(dev, MTK_WED_WDMA_RING_TX + MTK_WED_RING_OFS_DMA_IDX,
1941 0);
1942 }
1943
1944 return 0;
1945 }
1946
1947 static void
mtk_wed_ppe_check(struct mtk_wed_device * dev,struct sk_buff * skb,u32 reason,u32 hash)1948 mtk_wed_ppe_check(struct mtk_wed_device *dev, struct sk_buff *skb,
1949 u32 reason, u32 hash)
1950 {
1951 struct mtk_eth *eth = dev->hw->eth;
1952 struct ethhdr *eh;
1953
1954 if (!skb)
1955 return;
1956
1957 if (reason != MTK_PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED)
1958 return;
1959
1960 skb_set_mac_header(skb, 0);
1961 eh = eth_hdr(skb);
1962 skb->protocol = eh->h_proto;
1963 mtk_ppe_check_skb(eth->ppe[dev->hw->index], skb, hash);
1964 }
1965
1966 static void
mtk_wed_configure_irq(struct mtk_wed_device * dev,u32 irq_mask)1967 mtk_wed_configure_irq(struct mtk_wed_device *dev, u32 irq_mask)
1968 {
1969 u32 wdma_mask = FIELD_PREP(MTK_WDMA_INT_MASK_RX_DONE, GENMASK(1, 0));
1970
1971 /* wed control cr set */
1972 wed_set(dev, MTK_WED_CTRL,
1973 MTK_WED_CTRL_WDMA_INT_AGENT_EN |
1974 MTK_WED_CTRL_WPDMA_INT_AGENT_EN |
1975 MTK_WED_CTRL_WED_TX_BM_EN |
1976 MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
1977
1978 if (mtk_wed_is_v1(dev->hw)) {
1979 wed_w32(dev, MTK_WED_PCIE_INT_TRIGGER,
1980 MTK_WED_PCIE_INT_TRIGGER_STATUS);
1981
1982 wed_w32(dev, MTK_WED_WPDMA_INT_TRIGGER,
1983 MTK_WED_WPDMA_INT_TRIGGER_RX_DONE |
1984 MTK_WED_WPDMA_INT_TRIGGER_TX_DONE);
1985
1986 wed_clr(dev, MTK_WED_WDMA_INT_CTRL, wdma_mask);
1987 } else {
1988 if (mtk_wed_is_v3_or_greater(dev->hw))
1989 wed_set(dev, MTK_WED_CTRL, MTK_WED_CTRL_TX_TKID_ALI_EN);
1990
1991 /* initial tx interrupt trigger */
1992 wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_TX,
1993 MTK_WED_WPDMA_INT_CTRL_TX0_DONE_EN |
1994 MTK_WED_WPDMA_INT_CTRL_TX0_DONE_CLR |
1995 MTK_WED_WPDMA_INT_CTRL_TX1_DONE_EN |
1996 MTK_WED_WPDMA_INT_CTRL_TX1_DONE_CLR |
1997 FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_TX0_DONE_TRIG,
1998 dev->wlan.tx_tbit[0]) |
1999 FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_TX1_DONE_TRIG,
2000 dev->wlan.tx_tbit[1]));
2001
2002 /* initial txfree interrupt trigger */
2003 wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_TX_FREE,
2004 MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_EN |
2005 MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_CLR |
2006 FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_TRIG,
2007 dev->wlan.txfree_tbit));
2008
2009 if (mtk_wed_get_rx_capa(dev)) {
2010 wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_RX,
2011 MTK_WED_WPDMA_INT_CTRL_RX0_EN |
2012 MTK_WED_WPDMA_INT_CTRL_RX0_CLR |
2013 MTK_WED_WPDMA_INT_CTRL_RX1_EN |
2014 MTK_WED_WPDMA_INT_CTRL_RX1_CLR |
2015 FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_RX0_DONE_TRIG,
2016 dev->wlan.rx_tbit[0]) |
2017 FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_RX1_DONE_TRIG,
2018 dev->wlan.rx_tbit[1]));
2019
2020 wdma_mask |= FIELD_PREP(MTK_WDMA_INT_MASK_TX_DONE,
2021 GENMASK(1, 0));
2022 }
2023
2024 wed_w32(dev, MTK_WED_WDMA_INT_CLR, wdma_mask);
2025 wed_set(dev, MTK_WED_WDMA_INT_CTRL,
2026 FIELD_PREP(MTK_WED_WDMA_INT_CTRL_POLL_SRC_SEL,
2027 dev->wdma_idx));
2028 }
2029
2030 wed_w32(dev, MTK_WED_WDMA_INT_TRIGGER, wdma_mask);
2031
2032 wdma_w32(dev, MTK_WDMA_INT_MASK, wdma_mask);
2033 wdma_w32(dev, MTK_WDMA_INT_GRP2, wdma_mask);
2034 wed_w32(dev, MTK_WED_WPDMA_INT_MASK, irq_mask);
2035 wed_w32(dev, MTK_WED_INT_MASK, irq_mask);
2036 }
2037
2038 #define MTK_WFMDA_RX_DMA_EN BIT(2)
2039 static void
mtk_wed_dma_enable(struct mtk_wed_device * dev)2040 mtk_wed_dma_enable(struct mtk_wed_device *dev)
2041 {
2042 int i;
2043
2044 if (!mtk_wed_is_v3_or_greater(dev->hw)) {
2045 wed_set(dev, MTK_WED_WPDMA_INT_CTRL,
2046 MTK_WED_WPDMA_INT_CTRL_SUBRT_ADV);
2047 wed_set(dev, MTK_WED_WPDMA_GLO_CFG,
2048 MTK_WED_WPDMA_GLO_CFG_TX_DRV_EN |
2049 MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN);
2050 wdma_set(dev, MTK_WDMA_GLO_CFG,
2051 MTK_WDMA_GLO_CFG_TX_DMA_EN |
2052 MTK_WDMA_GLO_CFG_RX_INFO1_PRERES |
2053 MTK_WDMA_GLO_CFG_RX_INFO2_PRERES);
2054 wed_set(dev, MTK_WED_WPDMA_CTRL, MTK_WED_WPDMA_CTRL_SDL1_FIXED);
2055 } else {
2056 wed_set(dev, MTK_WED_WPDMA_GLO_CFG,
2057 MTK_WED_WPDMA_GLO_CFG_TX_DRV_EN |
2058 MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN |
2059 MTK_WED_WPDMA_GLO_CFG_RX_DDONE2_WR);
2060 wdma_set(dev, MTK_WDMA_GLO_CFG, MTK_WDMA_GLO_CFG_TX_DMA_EN);
2061 }
2062
2063 wed_set(dev, MTK_WED_GLO_CFG,
2064 MTK_WED_GLO_CFG_TX_DMA_EN |
2065 MTK_WED_GLO_CFG_RX_DMA_EN);
2066
2067 wed_set(dev, MTK_WED_WDMA_GLO_CFG,
2068 MTK_WED_WDMA_GLO_CFG_RX_DRV_EN);
2069
2070 if (mtk_wed_is_v1(dev->hw)) {
2071 wdma_set(dev, MTK_WDMA_GLO_CFG,
2072 MTK_WDMA_GLO_CFG_RX_INFO3_PRERES);
2073 return;
2074 }
2075
2076 wed_set(dev, MTK_WED_WPDMA_GLO_CFG,
2077 MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_PKT_PROC |
2078 MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_CRX_SYNC);
2079
2080 if (mtk_wed_is_v3_or_greater(dev->hw)) {
2081 wed_set(dev, MTK_WED_WDMA_RX_PREF_CFG,
2082 FIELD_PREP(MTK_WED_WDMA_RX_PREF_BURST_SIZE, 0x10) |
2083 FIELD_PREP(MTK_WED_WDMA_RX_PREF_LOW_THRES, 0x8));
2084 wed_clr(dev, MTK_WED_WDMA_RX_PREF_CFG,
2085 MTK_WED_WDMA_RX_PREF_DDONE2_EN);
2086 wed_set(dev, MTK_WED_WDMA_RX_PREF_CFG, MTK_WED_WDMA_RX_PREF_EN);
2087
2088 wed_clr(dev, MTK_WED_WPDMA_GLO_CFG,
2089 MTK_WED_WPDMA_GLO_CFG_TX_DDONE_CHK_LAST);
2090 wed_set(dev, MTK_WED_WPDMA_GLO_CFG,
2091 MTK_WED_WPDMA_GLO_CFG_TX_DDONE_CHK |
2092 MTK_WED_WPDMA_GLO_CFG_RX_DRV_EVENT_PKT_FMT_CHK |
2093 MTK_WED_WPDMA_GLO_CFG_RX_DRV_UNS_VER_FORCE_4);
2094
2095 wdma_set(dev, MTK_WDMA_PREF_RX_CFG, MTK_WDMA_PREF_RX_CFG_PREF_EN);
2096 wdma_set(dev, MTK_WDMA_WRBK_RX_CFG, MTK_WDMA_WRBK_RX_CFG_WRBK_EN);
2097 }
2098
2099 wed_clr(dev, MTK_WED_WPDMA_GLO_CFG,
2100 MTK_WED_WPDMA_GLO_CFG_TX_TKID_KEEP |
2101 MTK_WED_WPDMA_GLO_CFG_TX_DMAD_DW3_PREV);
2102
2103 if (!mtk_wed_get_rx_capa(dev))
2104 return;
2105
2106 wed_set(dev, MTK_WED_WDMA_GLO_CFG,
2107 MTK_WED_WDMA_GLO_CFG_TX_DRV_EN |
2108 MTK_WED_WDMA_GLO_CFG_TX_DDONE_CHK);
2109
2110 wed_clr(dev, MTK_WED_WPDMA_RX_D_GLO_CFG, MTK_WED_WPDMA_RX_D_RXD_READ_LEN);
2111 wed_set(dev, MTK_WED_WPDMA_RX_D_GLO_CFG,
2112 MTK_WED_WPDMA_RX_D_RX_DRV_EN |
2113 FIELD_PREP(MTK_WED_WPDMA_RX_D_RXD_READ_LEN, 0x18) |
2114 FIELD_PREP(MTK_WED_WPDMA_RX_D_INIT_PHASE_RXEN_SEL, 0x2));
2115
2116 if (mtk_wed_is_v3_or_greater(dev->hw)) {
2117 wed_set(dev, MTK_WED_WPDMA_RX_D_PREF_CFG,
2118 MTK_WED_WPDMA_RX_D_PREF_EN |
2119 FIELD_PREP(MTK_WED_WPDMA_RX_D_PREF_BURST_SIZE, 0x10) |
2120 FIELD_PREP(MTK_WED_WPDMA_RX_D_PREF_LOW_THRES, 0x8));
2121
2122 wed_set(dev, MTK_WED_RRO_RX_D_CFG(2), MTK_WED_RRO_RX_D_DRV_EN);
2123 wdma_set(dev, MTK_WDMA_PREF_TX_CFG, MTK_WDMA_PREF_TX_CFG_PREF_EN);
2124 wdma_set(dev, MTK_WDMA_WRBK_TX_CFG, MTK_WDMA_WRBK_TX_CFG_WRBK_EN);
2125 }
2126
2127 for (i = 0; i < MTK_WED_RX_QUEUES; i++) {
2128 struct mtk_wed_ring *ring = &dev->rx_ring[i];
2129 u32 val;
2130
2131 if (!(ring->flags & MTK_WED_RING_CONFIGURED))
2132 continue; /* queue is not configured by mt76 */
2133
2134 if (mtk_wed_check_wfdma_rx_fill(dev, ring)) {
2135 dev_err(dev->hw->dev,
2136 "rx_ring(%d) dma enable failed\n", i);
2137 continue;
2138 }
2139
2140 val = wifi_r32(dev,
2141 dev->wlan.wpdma_rx_glo -
2142 dev->wlan.phy_base) | MTK_WFMDA_RX_DMA_EN;
2143 wifi_w32(dev,
2144 dev->wlan.wpdma_rx_glo - dev->wlan.phy_base,
2145 val);
2146 }
2147 }
2148
2149 static void
mtk_wed_start_hw_rro(struct mtk_wed_device * dev,u32 irq_mask,bool reset)2150 mtk_wed_start_hw_rro(struct mtk_wed_device *dev, u32 irq_mask, bool reset)
2151 {
2152 int i;
2153
2154 wed_w32(dev, MTK_WED_WPDMA_INT_MASK, irq_mask);
2155 wed_w32(dev, MTK_WED_INT_MASK, irq_mask);
2156
2157 if (!mtk_wed_get_rx_capa(dev) || !dev->wlan.hw_rro)
2158 return;
2159
2160 if (reset) {
2161 wed_set(dev, MTK_WED_RRO_MSDU_PG_RING2_CFG,
2162 MTK_WED_RRO_MSDU_PG_DRV_EN);
2163 return;
2164 }
2165
2166 wed_set(dev, MTK_WED_RRO_RX_D_CFG(2), MTK_WED_RRO_MSDU_PG_DRV_CLR);
2167 wed_w32(dev, MTK_WED_RRO_MSDU_PG_RING2_CFG,
2168 MTK_WED_RRO_MSDU_PG_DRV_CLR);
2169
2170 wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_RRO_RX,
2171 MTK_WED_WPDMA_INT_CTRL_RRO_RX0_EN |
2172 MTK_WED_WPDMA_INT_CTRL_RRO_RX0_CLR |
2173 MTK_WED_WPDMA_INT_CTRL_RRO_RX1_EN |
2174 MTK_WED_WPDMA_INT_CTRL_RRO_RX1_CLR |
2175 FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_RRO_RX0_DONE_TRIG,
2176 dev->wlan.rro_rx_tbit[0]) |
2177 FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_RRO_RX1_DONE_TRIG,
2178 dev->wlan.rro_rx_tbit[1]));
2179
2180 wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_RRO_MSDU_PG,
2181 MTK_WED_WPDMA_INT_CTRL_RRO_PG0_EN |
2182 MTK_WED_WPDMA_INT_CTRL_RRO_PG0_CLR |
2183 MTK_WED_WPDMA_INT_CTRL_RRO_PG1_EN |
2184 MTK_WED_WPDMA_INT_CTRL_RRO_PG1_CLR |
2185 MTK_WED_WPDMA_INT_CTRL_RRO_PG2_EN |
2186 MTK_WED_WPDMA_INT_CTRL_RRO_PG2_CLR |
2187 FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_RRO_PG0_DONE_TRIG,
2188 dev->wlan.rx_pg_tbit[0]) |
2189 FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_RRO_PG1_DONE_TRIG,
2190 dev->wlan.rx_pg_tbit[1]) |
2191 FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_RRO_PG2_DONE_TRIG,
2192 dev->wlan.rx_pg_tbit[2]));
2193
2194 /* RRO_MSDU_PG_RING2_CFG1_FLD_DRV_EN should be enabled after
2195 * WM FWDL completed, otherwise RRO_MSDU_PG ring may broken
2196 */
2197 wed_set(dev, MTK_WED_RRO_MSDU_PG_RING2_CFG,
2198 MTK_WED_RRO_MSDU_PG_DRV_EN);
2199
2200 for (i = 0; i < MTK_WED_RX_QUEUES; i++) {
2201 struct mtk_wed_ring *ring = &dev->rx_rro_ring[i];
2202
2203 if (!(ring->flags & MTK_WED_RING_CONFIGURED))
2204 continue;
2205
2206 if (mtk_wed_check_wfdma_rx_fill(dev, ring))
2207 dev_err(dev->hw->dev,
2208 "rx_rro_ring(%d) initialization failed\n", i);
2209 }
2210
2211 for (i = 0; i < MTK_WED_RX_PAGE_QUEUES; i++) {
2212 struct mtk_wed_ring *ring = &dev->rx_page_ring[i];
2213
2214 if (!(ring->flags & MTK_WED_RING_CONFIGURED))
2215 continue;
2216
2217 if (mtk_wed_check_wfdma_rx_fill(dev, ring))
2218 dev_err(dev->hw->dev,
2219 "rx_page_ring(%d) initialization failed\n", i);
2220 }
2221 }
2222
2223 static void
mtk_wed_rro_rx_ring_setup(struct mtk_wed_device * dev,int idx,void __iomem * regs)2224 mtk_wed_rro_rx_ring_setup(struct mtk_wed_device *dev, int idx,
2225 void __iomem *regs)
2226 {
2227 struct mtk_wed_ring *ring = &dev->rx_rro_ring[idx];
2228
2229 ring->wpdma = regs;
2230 wed_w32(dev, MTK_WED_RRO_RX_D_RX(idx) + MTK_WED_RING_OFS_BASE,
2231 readl(regs));
2232 wed_w32(dev, MTK_WED_RRO_RX_D_RX(idx) + MTK_WED_RING_OFS_COUNT,
2233 readl(regs + MTK_WED_RING_OFS_COUNT));
2234 ring->flags |= MTK_WED_RING_CONFIGURED;
2235 }
2236
2237 static void
mtk_wed_msdu_pg_rx_ring_setup(struct mtk_wed_device * dev,int idx,void __iomem * regs)2238 mtk_wed_msdu_pg_rx_ring_setup(struct mtk_wed_device *dev, int idx, void __iomem *regs)
2239 {
2240 struct mtk_wed_ring *ring = &dev->rx_page_ring[idx];
2241
2242 ring->wpdma = regs;
2243 wed_w32(dev, MTK_WED_RRO_MSDU_PG_CTRL0(idx) + MTK_WED_RING_OFS_BASE,
2244 readl(regs));
2245 wed_w32(dev, MTK_WED_RRO_MSDU_PG_CTRL0(idx) + MTK_WED_RING_OFS_COUNT,
2246 readl(regs + MTK_WED_RING_OFS_COUNT));
2247 ring->flags |= MTK_WED_RING_CONFIGURED;
2248 }
2249
2250 static int
mtk_wed_ind_rx_ring_setup(struct mtk_wed_device * dev,void __iomem * regs)2251 mtk_wed_ind_rx_ring_setup(struct mtk_wed_device *dev, void __iomem *regs)
2252 {
2253 struct mtk_wed_ring *ring = &dev->ind_cmd_ring;
2254 u32 val = readl(regs + MTK_WED_RING_OFS_COUNT);
2255 int i, count = 0;
2256
2257 ring->wpdma = regs;
2258 wed_w32(dev, MTK_WED_IND_CMD_RX_CTRL1 + MTK_WED_RING_OFS_BASE,
2259 readl(regs) & 0xfffffff0);
2260
2261 wed_w32(dev, MTK_WED_IND_CMD_RX_CTRL1 + MTK_WED_RING_OFS_COUNT,
2262 readl(regs + MTK_WED_RING_OFS_COUNT));
2263
2264 /* ack sn cr */
2265 wed_w32(dev, MTK_WED_RRO_CFG0, dev->wlan.phy_base +
2266 dev->wlan.ind_cmd.ack_sn_addr);
2267 wed_w32(dev, MTK_WED_RRO_CFG1,
2268 FIELD_PREP(MTK_WED_RRO_CFG1_MAX_WIN_SZ,
2269 dev->wlan.ind_cmd.win_size) |
2270 FIELD_PREP(MTK_WED_RRO_CFG1_PARTICL_SE_ID,
2271 dev->wlan.ind_cmd.particular_sid));
2272
2273 /* particular session addr element */
2274 wed_w32(dev, MTK_WED_ADDR_ELEM_CFG0,
2275 dev->wlan.ind_cmd.particular_se_phys);
2276
2277 for (i = 0; i < dev->wlan.ind_cmd.se_group_nums; i++) {
2278 wed_w32(dev, MTK_WED_RADDR_ELEM_TBL_WDATA,
2279 dev->wlan.ind_cmd.addr_elem_phys[i] >> 4);
2280 wed_w32(dev, MTK_WED_ADDR_ELEM_TBL_CFG,
2281 MTK_WED_ADDR_ELEM_TBL_WR | (i & 0x7f));
2282
2283 val = wed_r32(dev, MTK_WED_ADDR_ELEM_TBL_CFG);
2284 while (!(val & MTK_WED_ADDR_ELEM_TBL_WR_RDY) && count++ < 100)
2285 val = wed_r32(dev, MTK_WED_ADDR_ELEM_TBL_CFG);
2286 if (count >= 100)
2287 dev_err(dev->hw->dev,
2288 "write ba session base failed\n");
2289 }
2290
2291 /* pn check init */
2292 for (i = 0; i < dev->wlan.ind_cmd.particular_sid; i++) {
2293 wed_w32(dev, MTK_WED_PN_CHECK_WDATA_M,
2294 MTK_WED_PN_CHECK_IS_FIRST);
2295
2296 wed_w32(dev, MTK_WED_PN_CHECK_CFG, MTK_WED_PN_CHECK_WR |
2297 FIELD_PREP(MTK_WED_PN_CHECK_SE_ID, i));
2298
2299 count = 0;
2300 val = wed_r32(dev, MTK_WED_PN_CHECK_CFG);
2301 while (!(val & MTK_WED_PN_CHECK_WR_RDY) && count++ < 100)
2302 val = wed_r32(dev, MTK_WED_PN_CHECK_CFG);
2303 if (count >= 100)
2304 dev_err(dev->hw->dev,
2305 "session(%d) initialization failed\n", i);
2306 }
2307
2308 wed_w32(dev, MTK_WED_RX_IND_CMD_CNT0, MTK_WED_RX_IND_CMD_DBG_CNT_EN);
2309 wed_set(dev, MTK_WED_CTRL, MTK_WED_CTRL_WED_RX_IND_CMD_EN);
2310
2311 return 0;
2312 }
2313
2314 static void
mtk_wed_start(struct mtk_wed_device * dev,u32 irq_mask)2315 mtk_wed_start(struct mtk_wed_device *dev, u32 irq_mask)
2316 {
2317 int i;
2318
2319 if (mtk_wed_get_rx_capa(dev) && mtk_wed_rx_buffer_alloc(dev))
2320 return;
2321
2322 for (i = 0; i < ARRAY_SIZE(dev->rx_wdma); i++)
2323 if (!dev->rx_wdma[i].desc)
2324 mtk_wed_wdma_rx_ring_setup(dev, i, 16, false);
2325
2326 mtk_wed_hw_init(dev);
2327 mtk_wed_configure_irq(dev, irq_mask);
2328
2329 mtk_wed_set_ext_int(dev, true);
2330
2331 if (mtk_wed_is_v1(dev->hw)) {
2332 u32 val = dev->wlan.wpdma_phys | MTK_PCIE_MIRROR_MAP_EN |
2333 FIELD_PREP(MTK_PCIE_MIRROR_MAP_WED_ID,
2334 dev->hw->index);
2335
2336 val |= BIT(0) | (BIT(1) * !!dev->hw->index);
2337 regmap_write(dev->hw->mirror, dev->hw->index * 4, val);
2338 } else if (mtk_wed_get_rx_capa(dev)) {
2339 /* driver set mid ready and only once */
2340 wed_w32(dev, MTK_WED_EXT_INT_MASK1,
2341 MTK_WED_EXT_INT_STATUS_WPDMA_MID_RDY);
2342 wed_w32(dev, MTK_WED_EXT_INT_MASK2,
2343 MTK_WED_EXT_INT_STATUS_WPDMA_MID_RDY);
2344
2345 wed_r32(dev, MTK_WED_EXT_INT_MASK1);
2346 wed_r32(dev, MTK_WED_EXT_INT_MASK2);
2347
2348 if (mtk_wed_is_v3_or_greater(dev->hw)) {
2349 wed_w32(dev, MTK_WED_EXT_INT_MASK3,
2350 MTK_WED_EXT_INT_STATUS_WPDMA_MID_RDY);
2351 wed_r32(dev, MTK_WED_EXT_INT_MASK3);
2352 }
2353
2354 if (mtk_wed_rro_cfg(dev))
2355 return;
2356 }
2357
2358 mtk_wed_set_512_support(dev, dev->wlan.wcid_512);
2359 mtk_wed_amsdu_init(dev);
2360
2361 mtk_wed_dma_enable(dev);
2362 dev->running = true;
2363 }
2364
2365 static int
mtk_wed_attach(struct mtk_wed_device * dev)2366 mtk_wed_attach(struct mtk_wed_device *dev)
2367 __releases(RCU)
2368 {
2369 struct mtk_wed_hw *hw;
2370 struct device *device;
2371 int ret = 0;
2372
2373 RCU_LOCKDEP_WARN(!rcu_read_lock_held(),
2374 "mtk_wed_attach without holding the RCU read lock");
2375
2376 if ((dev->wlan.bus_type == MTK_WED_BUS_PCIE &&
2377 pci_domain_nr(dev->wlan.pci_dev->bus) > 1) ||
2378 !try_module_get(THIS_MODULE))
2379 ret = -ENODEV;
2380
2381 rcu_read_unlock();
2382
2383 if (ret)
2384 return ret;
2385
2386 mutex_lock(&hw_lock);
2387
2388 hw = mtk_wed_assign(dev);
2389 if (!hw) {
2390 module_put(THIS_MODULE);
2391 ret = -ENODEV;
2392 goto unlock;
2393 }
2394
2395 device = dev->wlan.bus_type == MTK_WED_BUS_PCIE
2396 ? &dev->wlan.pci_dev->dev
2397 : &dev->wlan.platform_dev->dev;
2398 dev_info(device, "attaching wed device %d version %d\n",
2399 hw->index, hw->version);
2400
2401 dev->hw = hw;
2402 dev->dev = hw->dev;
2403 dev->irq = hw->irq;
2404 dev->wdma_idx = hw->index;
2405 dev->version = hw->version;
2406 dev->hw->pcie_base = mtk_wed_get_pcie_base(dev);
2407
2408 if (hw->eth->dma_dev == hw->eth->dev &&
2409 of_dma_is_coherent(hw->eth->dev->of_node))
2410 mtk_eth_set_dma_device(hw->eth, hw->dev);
2411
2412 ret = mtk_wed_tx_buffer_alloc(dev);
2413 if (ret)
2414 goto out;
2415
2416 ret = mtk_wed_amsdu_buffer_alloc(dev);
2417 if (ret)
2418 goto out;
2419
2420 if (mtk_wed_get_rx_capa(dev)) {
2421 ret = mtk_wed_rro_alloc(dev);
2422 if (ret)
2423 goto out;
2424 }
2425
2426 mtk_wed_hw_init_early(dev);
2427 if (mtk_wed_is_v1(hw))
2428 regmap_update_bits(hw->hifsys, HIFSYS_DMA_AG_MAP,
2429 BIT(hw->index), 0);
2430 else
2431 dev->rev_id = wed_r32(dev, MTK_WED_REV_ID);
2432
2433 if (mtk_wed_get_rx_capa(dev))
2434 ret = mtk_wed_wo_init(hw);
2435 out:
2436 if (ret) {
2437 dev_err(dev->hw->dev, "failed to attach wed device\n");
2438 __mtk_wed_detach(dev);
2439 }
2440 unlock:
2441 mutex_unlock(&hw_lock);
2442
2443 return ret;
2444 }
2445
2446 static int
mtk_wed_tx_ring_setup(struct mtk_wed_device * dev,int idx,void __iomem * regs,bool reset)2447 mtk_wed_tx_ring_setup(struct mtk_wed_device *dev, int idx, void __iomem *regs,
2448 bool reset)
2449 {
2450 struct mtk_wed_ring *ring = &dev->tx_ring[idx];
2451
2452 /*
2453 * Tx ring redirection:
2454 * Instead of configuring the WLAN PDMA TX ring directly, the WLAN
2455 * driver allocated DMA ring gets configured into WED MTK_WED_RING_TX(n)
2456 * registers.
2457 *
2458 * WED driver posts its own DMA ring as WLAN PDMA TX and configures it
2459 * into MTK_WED_WPDMA_RING_TX(n) registers.
2460 * It gets filled with packets picked up from WED TX ring and from
2461 * WDMA RX.
2462 */
2463
2464 if (WARN_ON(idx >= ARRAY_SIZE(dev->tx_ring)))
2465 return -EINVAL;
2466
2467 if (!reset && mtk_wed_ring_alloc(dev, ring, MTK_WED_TX_RING_SIZE,
2468 sizeof(*ring->desc), true))
2469 return -ENOMEM;
2470
2471 if (mtk_wed_wdma_rx_ring_setup(dev, idx, MTK_WED_WDMA_RING_SIZE,
2472 reset))
2473 return -ENOMEM;
2474
2475 ring->reg_base = MTK_WED_RING_TX(idx);
2476 ring->wpdma = regs;
2477
2478 if (mtk_wed_is_v3_or_greater(dev->hw) && idx == 1) {
2479 /* reset prefetch index */
2480 wed_set(dev, MTK_WED_WDMA_RX_PREF_CFG,
2481 MTK_WED_WDMA_RX_PREF_RX0_SIDX_CLR |
2482 MTK_WED_WDMA_RX_PREF_RX1_SIDX_CLR);
2483
2484 wed_clr(dev, MTK_WED_WDMA_RX_PREF_CFG,
2485 MTK_WED_WDMA_RX_PREF_RX0_SIDX_CLR |
2486 MTK_WED_WDMA_RX_PREF_RX1_SIDX_CLR);
2487
2488 /* reset prefetch FIFO */
2489 wed_w32(dev, MTK_WED_WDMA_RX_PREF_FIFO_CFG,
2490 MTK_WED_WDMA_RX_PREF_FIFO_RX0_CLR |
2491 MTK_WED_WDMA_RX_PREF_FIFO_RX1_CLR);
2492 wed_w32(dev, MTK_WED_WDMA_RX_PREF_FIFO_CFG, 0);
2493 }
2494
2495 /* WED -> WPDMA */
2496 wpdma_tx_w32(dev, idx, MTK_WED_RING_OFS_BASE, ring->desc_phys);
2497 wpdma_tx_w32(dev, idx, MTK_WED_RING_OFS_COUNT, MTK_WED_TX_RING_SIZE);
2498 wpdma_tx_w32(dev, idx, MTK_WED_RING_OFS_CPU_IDX, 0);
2499
2500 wed_w32(dev, MTK_WED_WPDMA_RING_TX(idx) + MTK_WED_RING_OFS_BASE,
2501 ring->desc_phys);
2502 wed_w32(dev, MTK_WED_WPDMA_RING_TX(idx) + MTK_WED_RING_OFS_COUNT,
2503 MTK_WED_TX_RING_SIZE);
2504 wed_w32(dev, MTK_WED_WPDMA_RING_TX(idx) + MTK_WED_RING_OFS_CPU_IDX, 0);
2505
2506 return 0;
2507 }
2508
2509 static int
mtk_wed_txfree_ring_setup(struct mtk_wed_device * dev,void __iomem * regs)2510 mtk_wed_txfree_ring_setup(struct mtk_wed_device *dev, void __iomem *regs)
2511 {
2512 struct mtk_wed_ring *ring = &dev->txfree_ring;
2513 int i, index = mtk_wed_is_v1(dev->hw);
2514
2515 /*
2516 * For txfree event handling, the same DMA ring is shared between WED
2517 * and WLAN. The WLAN driver accesses the ring index registers through
2518 * WED
2519 */
2520 ring->reg_base = MTK_WED_RING_RX(index);
2521 ring->wpdma = regs;
2522
2523 for (i = 0; i < 12; i += 4) {
2524 u32 val = readl(regs + i);
2525
2526 wed_w32(dev, MTK_WED_RING_RX(index) + i, val);
2527 wed_w32(dev, MTK_WED_WPDMA_RING_RX(index) + i, val);
2528 }
2529
2530 return 0;
2531 }
2532
2533 static int
mtk_wed_rx_ring_setup(struct mtk_wed_device * dev,int idx,void __iomem * regs,bool reset)2534 mtk_wed_rx_ring_setup(struct mtk_wed_device *dev, int idx, void __iomem *regs,
2535 bool reset)
2536 {
2537 struct mtk_wed_ring *ring = &dev->rx_ring[idx];
2538
2539 if (WARN_ON(idx >= ARRAY_SIZE(dev->rx_ring)))
2540 return -EINVAL;
2541
2542 if (!reset && mtk_wed_ring_alloc(dev, ring, MTK_WED_RX_RING_SIZE,
2543 sizeof(*ring->desc), false))
2544 return -ENOMEM;
2545
2546 if (mtk_wed_wdma_tx_ring_setup(dev, idx, MTK_WED_WDMA_RING_SIZE,
2547 reset))
2548 return -ENOMEM;
2549
2550 ring->reg_base = MTK_WED_RING_RX_DATA(idx);
2551 ring->wpdma = regs;
2552 ring->flags |= MTK_WED_RING_CONFIGURED;
2553
2554 /* WPDMA -> WED */
2555 wpdma_rx_w32(dev, idx, MTK_WED_RING_OFS_BASE, ring->desc_phys);
2556 wpdma_rx_w32(dev, idx, MTK_WED_RING_OFS_COUNT, MTK_WED_RX_RING_SIZE);
2557
2558 wed_w32(dev, MTK_WED_WPDMA_RING_RX_DATA(idx) + MTK_WED_RING_OFS_BASE,
2559 ring->desc_phys);
2560 wed_w32(dev, MTK_WED_WPDMA_RING_RX_DATA(idx) + MTK_WED_RING_OFS_COUNT,
2561 MTK_WED_RX_RING_SIZE);
2562
2563 return 0;
2564 }
2565
2566 static u32
mtk_wed_irq_get(struct mtk_wed_device * dev,u32 mask)2567 mtk_wed_irq_get(struct mtk_wed_device *dev, u32 mask)
2568 {
2569 u32 val, ext_mask;
2570
2571 if (mtk_wed_is_v3_or_greater(dev->hw))
2572 ext_mask = MTK_WED_EXT_INT_STATUS_RX_DRV_COHERENT |
2573 MTK_WED_EXT_INT_STATUS_TKID_WO_PYLD;
2574 else
2575 ext_mask = MTK_WED_EXT_INT_STATUS_ERROR_MASK;
2576
2577 val = wed_r32(dev, MTK_WED_EXT_INT_STATUS);
2578 wed_w32(dev, MTK_WED_EXT_INT_STATUS, val);
2579 val &= ext_mask;
2580 if (!dev->hw->num_flows)
2581 val &= ~MTK_WED_EXT_INT_STATUS_TKID_WO_PYLD;
2582 if (val && net_ratelimit())
2583 pr_err("mtk_wed%d: error status=%08x\n", dev->hw->index, val);
2584
2585 val = wed_r32(dev, MTK_WED_INT_STATUS);
2586 val &= mask;
2587 wed_w32(dev, MTK_WED_INT_STATUS, val); /* ACK */
2588
2589 return val;
2590 }
2591
2592 static void
mtk_wed_irq_set_mask(struct mtk_wed_device * dev,u32 mask)2593 mtk_wed_irq_set_mask(struct mtk_wed_device *dev, u32 mask)
2594 {
2595 mtk_wed_set_ext_int(dev, !!mask);
2596 wed_w32(dev, MTK_WED_INT_MASK, mask);
2597 }
2598
mtk_wed_flow_add(int index)2599 int mtk_wed_flow_add(int index)
2600 {
2601 struct mtk_wed_hw *hw = hw_list[index];
2602 int ret = 0;
2603
2604 mutex_lock(&hw_lock);
2605
2606 if (!hw || !hw->wed_dev) {
2607 ret = -ENODEV;
2608 goto out;
2609 }
2610
2611 if (!hw->wed_dev->wlan.offload_enable)
2612 goto out;
2613
2614 if (hw->num_flows) {
2615 hw->num_flows++;
2616 goto out;
2617 }
2618
2619 ret = hw->wed_dev->wlan.offload_enable(hw->wed_dev);
2620 if (!ret)
2621 hw->num_flows++;
2622 mtk_wed_set_ext_int(hw->wed_dev, true);
2623
2624 out:
2625 mutex_unlock(&hw_lock);
2626
2627 return ret;
2628 }
2629
mtk_wed_flow_remove(int index)2630 void mtk_wed_flow_remove(int index)
2631 {
2632 struct mtk_wed_hw *hw = hw_list[index];
2633
2634 mutex_lock(&hw_lock);
2635
2636 if (!hw || !hw->wed_dev)
2637 goto out;
2638
2639 if (!hw->wed_dev->wlan.offload_disable)
2640 goto out;
2641
2642 if (--hw->num_flows)
2643 goto out;
2644
2645 hw->wed_dev->wlan.offload_disable(hw->wed_dev);
2646 mtk_wed_set_ext_int(hw->wed_dev, true);
2647
2648 out:
2649 mutex_unlock(&hw_lock);
2650 }
2651
2652 static int
mtk_wed_setup_tc_block_cb(enum tc_setup_type type,void * type_data,void * cb_priv)2653 mtk_wed_setup_tc_block_cb(enum tc_setup_type type, void *type_data, void *cb_priv)
2654 {
2655 struct mtk_wed_flow_block_priv *priv = cb_priv;
2656 struct flow_cls_offload *cls = type_data;
2657 struct mtk_wed_hw *hw = NULL;
2658
2659 if (!priv || !tc_can_offload(priv->dev))
2660 return -EOPNOTSUPP;
2661
2662 if (type != TC_SETUP_CLSFLOWER)
2663 return -EOPNOTSUPP;
2664
2665 hw = priv->hw;
2666 return mtk_flow_offload_cmd(hw->eth, cls, hw->index);
2667 }
2668
2669 static int
mtk_wed_setup_tc_block(struct mtk_wed_hw * hw,struct net_device * dev,struct flow_block_offload * f)2670 mtk_wed_setup_tc_block(struct mtk_wed_hw *hw, struct net_device *dev,
2671 struct flow_block_offload *f)
2672 {
2673 struct mtk_wed_flow_block_priv *priv;
2674 static LIST_HEAD(block_cb_list);
2675 struct flow_block_cb *block_cb;
2676 struct mtk_eth *eth = hw->eth;
2677 flow_setup_cb_t *cb;
2678
2679 if (!eth->soc->offload_version)
2680 return -EOPNOTSUPP;
2681
2682 if (f->binder_type != FLOW_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
2683 return -EOPNOTSUPP;
2684
2685 cb = mtk_wed_setup_tc_block_cb;
2686 f->driver_block_list = &block_cb_list;
2687
2688 switch (f->command) {
2689 case FLOW_BLOCK_BIND:
2690 block_cb = flow_block_cb_lookup(f->block, cb, dev);
2691 if (block_cb) {
2692 flow_block_cb_incref(block_cb);
2693 return 0;
2694 }
2695
2696 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
2697 if (!priv)
2698 return -ENOMEM;
2699
2700 priv->hw = hw;
2701 priv->dev = dev;
2702 block_cb = flow_block_cb_alloc(cb, dev, priv, NULL);
2703 if (IS_ERR(block_cb)) {
2704 kfree(priv);
2705 return PTR_ERR(block_cb);
2706 }
2707
2708 flow_block_cb_incref(block_cb);
2709 flow_block_cb_add(block_cb, f);
2710 list_add_tail(&block_cb->driver_list, &block_cb_list);
2711 return 0;
2712 case FLOW_BLOCK_UNBIND:
2713 block_cb = flow_block_cb_lookup(f->block, cb, dev);
2714 if (!block_cb)
2715 return -ENOENT;
2716
2717 if (!flow_block_cb_decref(block_cb)) {
2718 flow_block_cb_remove(block_cb, f);
2719 list_del(&block_cb->driver_list);
2720 kfree(block_cb->cb_priv);
2721 block_cb->cb_priv = NULL;
2722 }
2723 return 0;
2724 default:
2725 return -EOPNOTSUPP;
2726 }
2727 }
2728
2729 static int
mtk_wed_setup_tc(struct mtk_wed_device * wed,struct net_device * dev,enum tc_setup_type type,void * type_data)2730 mtk_wed_setup_tc(struct mtk_wed_device *wed, struct net_device *dev,
2731 enum tc_setup_type type, void *type_data)
2732 {
2733 struct mtk_wed_hw *hw = wed->hw;
2734
2735 if (mtk_wed_is_v1(hw))
2736 return -EOPNOTSUPP;
2737
2738 switch (type) {
2739 case TC_SETUP_BLOCK:
2740 case TC_SETUP_FT:
2741 return mtk_wed_setup_tc_block(hw, dev, type_data);
2742 default:
2743 return -EOPNOTSUPP;
2744 }
2745 }
2746
mtk_wed_add_hw(struct device_node * np,struct mtk_eth * eth,void __iomem * wdma,phys_addr_t wdma_phy,int index)2747 void mtk_wed_add_hw(struct device_node *np, struct mtk_eth *eth,
2748 void __iomem *wdma, phys_addr_t wdma_phy,
2749 int index)
2750 {
2751 static const struct mtk_wed_ops wed_ops = {
2752 .attach = mtk_wed_attach,
2753 .tx_ring_setup = mtk_wed_tx_ring_setup,
2754 .rx_ring_setup = mtk_wed_rx_ring_setup,
2755 .txfree_ring_setup = mtk_wed_txfree_ring_setup,
2756 .msg_update = mtk_wed_mcu_msg_update,
2757 .start = mtk_wed_start,
2758 .stop = mtk_wed_stop,
2759 .reset_dma = mtk_wed_reset_dma,
2760 .reg_read = wed_r32,
2761 .reg_write = wed_w32,
2762 .irq_get = mtk_wed_irq_get,
2763 .irq_set_mask = mtk_wed_irq_set_mask,
2764 .detach = mtk_wed_detach,
2765 .ppe_check = mtk_wed_ppe_check,
2766 .setup_tc = mtk_wed_setup_tc,
2767 .start_hw_rro = mtk_wed_start_hw_rro,
2768 .rro_rx_ring_setup = mtk_wed_rro_rx_ring_setup,
2769 .msdu_pg_rx_ring_setup = mtk_wed_msdu_pg_rx_ring_setup,
2770 .ind_rx_ring_setup = mtk_wed_ind_rx_ring_setup,
2771 };
2772 struct device_node *eth_np = eth->dev->of_node;
2773 struct platform_device *pdev;
2774 struct mtk_wed_hw *hw;
2775 struct regmap *regs;
2776 int irq;
2777
2778 if (!np)
2779 return;
2780
2781 pdev = of_find_device_by_node(np);
2782 if (!pdev)
2783 goto err_of_node_put;
2784
2785 irq = platform_get_irq(pdev, 0);
2786 if (irq < 0)
2787 goto err_put_device;
2788
2789 regs = syscon_regmap_lookup_by_phandle(np, NULL);
2790 if (IS_ERR(regs))
2791 goto err_put_device;
2792
2793 rcu_assign_pointer(mtk_soc_wed_ops, &wed_ops);
2794
2795 mutex_lock(&hw_lock);
2796
2797 if (WARN_ON(hw_list[index]))
2798 goto unlock;
2799
2800 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
2801 if (!hw)
2802 goto unlock;
2803
2804 hw->node = np;
2805 hw->regs = regs;
2806 hw->eth = eth;
2807 hw->dev = &pdev->dev;
2808 hw->wdma_phy = wdma_phy;
2809 hw->wdma = wdma;
2810 hw->index = index;
2811 hw->irq = irq;
2812 hw->version = eth->soc->version;
2813
2814 switch (hw->version) {
2815 case 2:
2816 hw->soc = &mt7986_data;
2817 break;
2818 case 3:
2819 hw->soc = &mt7988_data;
2820 break;
2821 default:
2822 case 1:
2823 hw->mirror = syscon_regmap_lookup_by_phandle(eth_np,
2824 "mediatek,pcie-mirror");
2825 hw->hifsys = syscon_regmap_lookup_by_phandle(eth_np,
2826 "mediatek,hifsys");
2827 if (IS_ERR(hw->mirror) || IS_ERR(hw->hifsys)) {
2828 kfree(hw);
2829 goto unlock;
2830 }
2831
2832 if (!index) {
2833 regmap_write(hw->mirror, 0, 0);
2834 regmap_write(hw->mirror, 4, 0);
2835 }
2836 hw->soc = &mt7622_data;
2837 break;
2838 }
2839
2840 mtk_wed_hw_add_debugfs(hw);
2841
2842 hw_list[index] = hw;
2843
2844 mutex_unlock(&hw_lock);
2845
2846 return;
2847
2848 unlock:
2849 mutex_unlock(&hw_lock);
2850 err_put_device:
2851 put_device(&pdev->dev);
2852 err_of_node_put:
2853 of_node_put(np);
2854 }
2855
mtk_wed_exit(void)2856 void mtk_wed_exit(void)
2857 {
2858 int i;
2859
2860 rcu_assign_pointer(mtk_soc_wed_ops, NULL);
2861
2862 synchronize_rcu();
2863
2864 for (i = 0; i < ARRAY_SIZE(hw_list); i++) {
2865 struct mtk_wed_hw *hw;
2866
2867 hw = hw_list[i];
2868 if (!hw)
2869 continue;
2870
2871 hw_list[i] = NULL;
2872 debugfs_remove(hw->debugfs_dir);
2873 put_device(hw->dev);
2874 of_node_put(hw->node);
2875 kfree(hw);
2876 }
2877 }
2878