1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Rockchip Video Decoder VDPU383 H264 backend
4 *
5 * Copyright (C) 2024 Collabora, Ltd.
6 * Detlev Casanova <detlev.casanova@collabora.com>
7 */
8
9 #include <media/v4l2-h264.h>
10 #include <media/v4l2-mem2mem.h>
11
12 #include <linux/iopoll.h>
13
14 #include "rkvdec-rcb.h"
15 #include "rkvdec-cabac.h"
16 #include "rkvdec-vdpu383-regs.h"
17 #include "rkvdec-h264-common.h"
18
19 struct rkvdec_sps {
20 u16 seq_parameter_set_id: 4;
21 u16 profile_idc: 8;
22 u16 constraint_set3_flag: 1;
23 u16 chroma_format_idc: 2;
24 u16 bit_depth_luma: 3;
25 u16 bit_depth_chroma: 3;
26 u16 qpprime_y_zero_transform_bypass_flag: 1;
27 u16 log2_max_frame_num_minus4: 4;
28 u16 max_num_ref_frames: 5;
29 u16 pic_order_cnt_type: 2;
30 u16 log2_max_pic_order_cnt_lsb_minus4: 4;
31 u16 delta_pic_order_always_zero_flag: 1;
32
33 u16 pic_width_in_mbs: 16;
34 u16 pic_height_in_mbs: 16;
35
36 u16 frame_mbs_only_flag: 1;
37 u16 mb_adaptive_frame_field_flag: 1;
38 u16 direct_8x8_inference_flag: 1;
39 u16 mvc_extension_enable: 1;
40 u16 num_views: 2;
41 u16 view_id0: 10;
42 u16 view_id1: 10;
43 } __packed;
44
45 struct rkvdec_pps {
46 u32 pic_parameter_set_id: 8;
47 u32 pps_seq_parameter_set_id: 5;
48 u32 entropy_coding_mode_flag: 1;
49 u32 bottom_field_pic_order_in_frame_present_flag: 1;
50 u32 num_ref_idx_l0_default_active_minus1: 5;
51 u32 num_ref_idx_l1_default_active_minus1: 5;
52 u32 weighted_pred_flag: 1;
53 u32 weighted_bipred_idc: 2;
54 u32 pic_init_qp_minus26: 7;
55 u32 pic_init_qs_minus26: 6;
56 u32 chroma_qp_index_offset: 5;
57 u32 deblocking_filter_control_present_flag: 1;
58 u32 constrained_intra_pred_flag: 1;
59 u32 redundant_pic_cnt_present: 1;
60 u32 transform_8x8_mode_flag: 1;
61 u32 second_chroma_qp_index_offset: 5;
62 u32 scaling_list_enable_flag: 1;
63 u32 is_longterm: 16;
64 u32 voidx: 16;
65
66 // dpb
67 u32 pic_field_flag: 1;
68 u32 pic_associated_flag: 1;
69 u32 cur_top_field: 32;
70 u32 cur_bot_field: 32;
71
72 u32 top_field_order_cnt0: 32;
73 u32 bot_field_order_cnt0: 32;
74 u32 top_field_order_cnt1: 32;
75 u32 bot_field_order_cnt1: 32;
76 u32 top_field_order_cnt2: 32;
77 u32 bot_field_order_cnt2: 32;
78 u32 top_field_order_cnt3: 32;
79 u32 bot_field_order_cnt3: 32;
80 u32 top_field_order_cnt4: 32;
81 u32 bot_field_order_cnt4: 32;
82 u32 top_field_order_cnt5: 32;
83 u32 bot_field_order_cnt5: 32;
84 u32 top_field_order_cnt6: 32;
85 u32 bot_field_order_cnt6: 32;
86 u32 top_field_order_cnt7: 32;
87 u32 bot_field_order_cnt7: 32;
88 u32 top_field_order_cnt8: 32;
89 u32 bot_field_order_cnt8: 32;
90 u32 top_field_order_cnt9: 32;
91 u32 bot_field_order_cnt9: 32;
92 u32 top_field_order_cnt10: 32;
93 u32 bot_field_order_cnt10: 32;
94 u32 top_field_order_cnt11: 32;
95 u32 bot_field_order_cnt11: 32;
96 u32 top_field_order_cnt12: 32;
97 u32 bot_field_order_cnt12: 32;
98 u32 top_field_order_cnt13: 32;
99 u32 bot_field_order_cnt13: 32;
100 u32 top_field_order_cnt14: 32;
101 u32 bot_field_order_cnt14: 32;
102 u32 top_field_order_cnt15: 32;
103 u32 bot_field_order_cnt15: 32;
104
105 u32 ref_field_flags: 16;
106 u32 ref_topfield_used: 16;
107 u32 ref_botfield_used: 16;
108 u32 ref_colmv_use_flag: 16;
109
110 u32 reserved0: 30;
111 u32 reserved[3];
112 } __packed;
113
114 struct rkvdec_sps_pps {
115 struct rkvdec_sps sps;
116 struct rkvdec_pps pps;
117 } __packed;
118
119 /* Data structure describing auxiliary buffer format. */
120 struct rkvdec_h264_priv_tbl {
121 s8 cabac_table[4][464][2];
122 struct rkvdec_h264_scaling_list scaling_list;
123 struct rkvdec_sps_pps param_set[256];
124 struct rkvdec_rps rps;
125 } __packed;
126
127 struct rkvdec_h264_ctx {
128 struct rkvdec_aux_buf priv_tbl;
129 struct rkvdec_h264_reflists reflists;
130 struct vdpu383_regs_h26x regs;
131 };
132
set_field_order_cnt(struct rkvdec_pps * pps,const struct v4l2_h264_dpb_entry * dpb)133 static noinline_for_stack void set_field_order_cnt(struct rkvdec_pps *pps, const struct v4l2_h264_dpb_entry *dpb)
134 {
135 pps->top_field_order_cnt0 = dpb[0].top_field_order_cnt;
136 pps->bot_field_order_cnt0 = dpb[0].bottom_field_order_cnt;
137 pps->top_field_order_cnt1 = dpb[1].top_field_order_cnt;
138 pps->bot_field_order_cnt1 = dpb[1].bottom_field_order_cnt;
139 pps->top_field_order_cnt2 = dpb[2].top_field_order_cnt;
140 pps->bot_field_order_cnt2 = dpb[2].bottom_field_order_cnt;
141 pps->top_field_order_cnt3 = dpb[3].top_field_order_cnt;
142 pps->bot_field_order_cnt3 = dpb[3].bottom_field_order_cnt;
143 pps->top_field_order_cnt4 = dpb[4].top_field_order_cnt;
144 pps->bot_field_order_cnt4 = dpb[4].bottom_field_order_cnt;
145 pps->top_field_order_cnt5 = dpb[5].top_field_order_cnt;
146 pps->bot_field_order_cnt5 = dpb[5].bottom_field_order_cnt;
147 pps->top_field_order_cnt6 = dpb[6].top_field_order_cnt;
148 pps->bot_field_order_cnt6 = dpb[6].bottom_field_order_cnt;
149 pps->top_field_order_cnt7 = dpb[7].top_field_order_cnt;
150 pps->bot_field_order_cnt7 = dpb[7].bottom_field_order_cnt;
151 pps->top_field_order_cnt8 = dpb[8].top_field_order_cnt;
152 pps->bot_field_order_cnt8 = dpb[8].bottom_field_order_cnt;
153 pps->top_field_order_cnt9 = dpb[9].top_field_order_cnt;
154 pps->bot_field_order_cnt9 = dpb[9].bottom_field_order_cnt;
155 pps->top_field_order_cnt10 = dpb[10].top_field_order_cnt;
156 pps->bot_field_order_cnt10 = dpb[10].bottom_field_order_cnt;
157 pps->top_field_order_cnt11 = dpb[11].top_field_order_cnt;
158 pps->bot_field_order_cnt11 = dpb[11].bottom_field_order_cnt;
159 pps->top_field_order_cnt12 = dpb[12].top_field_order_cnt;
160 pps->bot_field_order_cnt12 = dpb[12].bottom_field_order_cnt;
161 pps->top_field_order_cnt13 = dpb[13].top_field_order_cnt;
162 pps->bot_field_order_cnt13 = dpb[13].bottom_field_order_cnt;
163 pps->top_field_order_cnt14 = dpb[14].top_field_order_cnt;
164 pps->bot_field_order_cnt14 = dpb[14].bottom_field_order_cnt;
165 pps->top_field_order_cnt15 = dpb[15].top_field_order_cnt;
166 pps->bot_field_order_cnt15 = dpb[15].bottom_field_order_cnt;
167 }
168
set_dec_params(struct rkvdec_pps * pps,const struct v4l2_ctrl_h264_decode_params * dec_params)169 static noinline_for_stack void set_dec_params(struct rkvdec_pps *pps, const struct v4l2_ctrl_h264_decode_params *dec_params)
170 {
171 const struct v4l2_h264_dpb_entry *dpb = dec_params->dpb;
172
173 for (int i = 0; i < ARRAY_SIZE(dec_params->dpb); i++) {
174 if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM)
175 pps->is_longterm |= (1 << i);
176 pps->ref_field_flags |=
177 (!!(dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_FIELD)) << i;
178 pps->ref_colmv_use_flag |=
179 (!!(dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)) << i;
180 pps->ref_topfield_used |=
181 (!!(dpb[i].fields & V4L2_H264_TOP_FIELD_REF)) << i;
182 pps->ref_botfield_used |=
183 (!!(dpb[i].fields & V4L2_H264_BOTTOM_FIELD_REF)) << i;
184 }
185 pps->pic_field_flag =
186 !!(dec_params->flags & V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC);
187 pps->pic_associated_flag =
188 !!(dec_params->flags & V4L2_H264_DECODE_PARAM_FLAG_BOTTOM_FIELD);
189
190 pps->cur_top_field = dec_params->top_field_order_cnt;
191 pps->cur_bot_field = dec_params->bottom_field_order_cnt;
192 }
193
assemble_hw_pps(struct rkvdec_ctx * ctx,struct rkvdec_h264_run * run)194 static void assemble_hw_pps(struct rkvdec_ctx *ctx,
195 struct rkvdec_h264_run *run)
196 {
197 struct rkvdec_h264_ctx *h264_ctx = ctx->priv;
198 const struct v4l2_ctrl_h264_sps *sps = run->sps;
199 const struct v4l2_ctrl_h264_pps *pps = run->pps;
200 const struct v4l2_ctrl_h264_decode_params *dec_params = run->decode_params;
201 const struct v4l2_h264_dpb_entry *dpb = dec_params->dpb;
202 struct rkvdec_h264_priv_tbl *priv_tbl = h264_ctx->priv_tbl.cpu;
203 struct rkvdec_sps_pps *hw_ps;
204 u32 pic_width, pic_height;
205
206 /*
207 * HW read the SPS/PPS information from PPS packet index by PPS id.
208 * offset from the base can be calculated by PPS_id * 32 (size per PPS
209 * packet unit). so the driver copy SPS/PPS information to the exact PPS
210 * packet unit for HW accessing.
211 */
212 hw_ps = &priv_tbl->param_set[pps->pic_parameter_set_id];
213 memset(hw_ps, 0, sizeof(*hw_ps));
214
215 /* write sps */
216 hw_ps->sps.seq_parameter_set_id = sps->seq_parameter_set_id;
217 hw_ps->sps.profile_idc = sps->profile_idc;
218 hw_ps->sps.constraint_set3_flag = !!(sps->constraint_set_flags & (1 << 3));
219 hw_ps->sps.chroma_format_idc = sps->chroma_format_idc;
220 hw_ps->sps.bit_depth_luma = sps->bit_depth_luma_minus8;
221 hw_ps->sps.bit_depth_chroma = sps->bit_depth_chroma_minus8;
222 hw_ps->sps.qpprime_y_zero_transform_bypass_flag =
223 !!(sps->flags & V4L2_H264_SPS_FLAG_QPPRIME_Y_ZERO_TRANSFORM_BYPASS);
224 hw_ps->sps.log2_max_frame_num_minus4 = sps->log2_max_frame_num_minus4;
225 hw_ps->sps.max_num_ref_frames = sps->max_num_ref_frames;
226 hw_ps->sps.pic_order_cnt_type = sps->pic_order_cnt_type;
227 hw_ps->sps.log2_max_pic_order_cnt_lsb_minus4 =
228 sps->log2_max_pic_order_cnt_lsb_minus4;
229 hw_ps->sps.delta_pic_order_always_zero_flag =
230 !!(sps->flags & V4L2_H264_SPS_FLAG_DELTA_PIC_ORDER_ALWAYS_ZERO);
231 hw_ps->sps.mvc_extension_enable = 0;
232 hw_ps->sps.num_views = 0;
233
234 /*
235 * Use the SPS values since they are already in macroblocks
236 * dimensions, height can be field height (halved) if
237 * V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY is not set and also it allows
238 * decoding smaller images into larger allocation which can be used
239 * to implementing SVC spatial layer support.
240 */
241 pic_width = 16 * (sps->pic_width_in_mbs_minus1 + 1);
242 pic_height = 16 * (sps->pic_height_in_map_units_minus1 + 1);
243 if (!(sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY))
244 pic_height *= 2;
245 if (!!(dec_params->flags & V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC))
246 pic_height /= 2;
247
248 hw_ps->sps.pic_width_in_mbs = pic_width;
249 hw_ps->sps.pic_height_in_mbs = pic_height;
250
251 hw_ps->sps.frame_mbs_only_flag =
252 !!(sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY);
253 hw_ps->sps.mb_adaptive_frame_field_flag =
254 !!(sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD);
255 hw_ps->sps.direct_8x8_inference_flag =
256 !!(sps->flags & V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE);
257
258 /* write pps */
259 hw_ps->pps.pic_parameter_set_id = pps->pic_parameter_set_id;
260 hw_ps->pps.pps_seq_parameter_set_id = pps->seq_parameter_set_id;
261 hw_ps->pps.entropy_coding_mode_flag =
262 !!(pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE);
263 hw_ps->pps.bottom_field_pic_order_in_frame_present_flag =
264 !!(pps->flags & V4L2_H264_PPS_FLAG_BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT);
265 hw_ps->pps.num_ref_idx_l0_default_active_minus1 =
266 pps->num_ref_idx_l0_default_active_minus1;
267 hw_ps->pps.num_ref_idx_l1_default_active_minus1 =
268 pps->num_ref_idx_l1_default_active_minus1;
269 hw_ps->pps.weighted_pred_flag =
270 !!(pps->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED);
271 hw_ps->pps.weighted_bipred_idc = pps->weighted_bipred_idc;
272 hw_ps->pps.pic_init_qp_minus26 = pps->pic_init_qp_minus26;
273 hw_ps->pps.pic_init_qs_minus26 = pps->pic_init_qs_minus26;
274 hw_ps->pps.chroma_qp_index_offset = pps->chroma_qp_index_offset;
275 hw_ps->pps.deblocking_filter_control_present_flag =
276 !!(pps->flags & V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT);
277 hw_ps->pps.constrained_intra_pred_flag =
278 !!(pps->flags & V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED);
279 hw_ps->pps.redundant_pic_cnt_present =
280 !!(pps->flags & V4L2_H264_PPS_FLAG_REDUNDANT_PIC_CNT_PRESENT);
281 hw_ps->pps.transform_8x8_mode_flag =
282 !!(pps->flags & V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE);
283 hw_ps->pps.second_chroma_qp_index_offset = pps->second_chroma_qp_index_offset;
284 hw_ps->pps.scaling_list_enable_flag =
285 !!(pps->flags & V4L2_H264_PPS_FLAG_SCALING_MATRIX_PRESENT);
286
287 set_field_order_cnt(&hw_ps->pps, dpb);
288 set_dec_params(&hw_ps->pps, dec_params);
289
290 }
291
rkvdec_write_regs(struct rkvdec_ctx * ctx)292 static void rkvdec_write_regs(struct rkvdec_ctx *ctx)
293 {
294 struct rkvdec_dev *rkvdec = ctx->dev;
295 struct rkvdec_h264_ctx *h264_ctx = ctx->priv;
296
297 rkvdec_memcpy_toio(rkvdec->regs + VDPU383_OFFSET_COMMON_REGS,
298 &h264_ctx->regs.common,
299 sizeof(h264_ctx->regs.common));
300 rkvdec_memcpy_toio(rkvdec->regs + VDPU383_OFFSET_COMMON_ADDR_REGS,
301 &h264_ctx->regs.common_addr,
302 sizeof(h264_ctx->regs.common_addr));
303 rkvdec_memcpy_toio(rkvdec->regs + VDPU383_OFFSET_CODEC_PARAMS_REGS,
304 &h264_ctx->regs.h26x_params,
305 sizeof(h264_ctx->regs.h26x_params));
306 rkvdec_memcpy_toio(rkvdec->regs + VDPU383_OFFSET_CODEC_ADDR_REGS,
307 &h264_ctx->regs.h26x_addr,
308 sizeof(h264_ctx->regs.h26x_addr));
309 }
310
config_registers(struct rkvdec_ctx * ctx,struct rkvdec_h264_run * run)311 static void config_registers(struct rkvdec_ctx *ctx,
312 struct rkvdec_h264_run *run)
313 {
314 const struct v4l2_ctrl_h264_decode_params *dec_params = run->decode_params;
315 struct rkvdec_h264_ctx *h264_ctx = ctx->priv;
316 dma_addr_t priv_start_addr = h264_ctx->priv_tbl.dma;
317 const struct v4l2_pix_format_mplane *dst_fmt;
318 struct vb2_v4l2_buffer *src_buf = run->base.bufs.src;
319 struct vb2_v4l2_buffer *dst_buf = run->base.bufs.dst;
320 struct vdpu383_regs_h26x *regs = &h264_ctx->regs;
321 const struct v4l2_format *f;
322 dma_addr_t rlc_addr;
323 dma_addr_t dst_addr;
324 u32 hor_virstride;
325 u32 ver_virstride;
326 u32 y_virstride;
327 u32 offset;
328 u32 pixels;
329 u32 i;
330
331 memset(regs, 0, sizeof(*regs));
332
333 /* Set H264 mode */
334 regs->common.reg008_dec_mode = VDPU383_MODE_H264;
335
336 /* Set input stream length */
337 regs->h26x_params.reg066_stream_len = vb2_get_plane_payload(&src_buf->vb2_buf, 0);
338
339 /* Set strides */
340 f = &ctx->decoded_fmt;
341 dst_fmt = &f->fmt.pix_mp;
342 hor_virstride = dst_fmt->plane_fmt[0].bytesperline;
343 ver_virstride = dst_fmt->height;
344 y_virstride = hor_virstride * ver_virstride;
345
346 pixels = dst_fmt->height * dst_fmt->width;
347
348 regs->h26x_params.reg068_hor_virstride = hor_virstride / 16;
349 regs->h26x_params.reg069_raster_uv_hor_virstride = hor_virstride / 16;
350 regs->h26x_params.reg070_y_virstride = y_virstride / 16;
351
352 /* Activate block gating */
353 regs->common.reg010_block_gating_en.strmd_auto_gating_e = 1;
354 regs->common.reg010_block_gating_en.inter_auto_gating_e = 1;
355 regs->common.reg010_block_gating_en.intra_auto_gating_e = 1;
356 regs->common.reg010_block_gating_en.transd_auto_gating_e = 1;
357 regs->common.reg010_block_gating_en.recon_auto_gating_e = 1;
358 regs->common.reg010_block_gating_en.filterd_auto_gating_e = 1;
359 regs->common.reg010_block_gating_en.bus_auto_gating_e = 1;
360 regs->common.reg010_block_gating_en.ctrl_auto_gating_e = 1;
361 regs->common.reg010_block_gating_en.rcb_auto_gating_e = 1;
362 regs->common.reg010_block_gating_en.err_prc_auto_gating_e = 1;
363
364 /* Set timeout threshold */
365 if (pixels < RKVDEC_1080P_PIXELS)
366 regs->common.reg013_core_timeout_threshold = VDPU383_TIMEOUT_1080p;
367 else if (pixels < RKVDEC_4K_PIXELS)
368 regs->common.reg013_core_timeout_threshold = VDPU383_TIMEOUT_4K;
369 else if (pixels < RKVDEC_8K_PIXELS)
370 regs->common.reg013_core_timeout_threshold = VDPU383_TIMEOUT_8K;
371 else
372 regs->common.reg013_core_timeout_threshold = VDPU383_TIMEOUT_MAX;
373
374 regs->common.reg016_error_ctrl_set.error_proc_disable = 1;
375
376 /* Set ref pic address & poc */
377 for (i = 0; i < ARRAY_SIZE(dec_params->dpb); i++) {
378 struct vb2_buffer *vb_buf = run->ref_buf[i];
379 dma_addr_t buf_dma;
380
381 /*
382 * If a DPB entry is unused or invalid, address of current destination
383 * buffer is returned.
384 */
385 if (!vb_buf)
386 vb_buf = &dst_buf->vb2_buf;
387
388 buf_dma = vb2_dma_contig_plane_dma_addr(vb_buf, 0);
389
390 /* Set reference addresses */
391 regs->h26x_addr.reg170_185_ref_base[i] = buf_dma;
392 regs->h26x_addr.reg195_210_payload_st_ref_base[i] = buf_dma;
393
394 /* Set COLMV addresses */
395 regs->h26x_addr.reg217_232_colmv_ref_base[i] = buf_dma + ctx->colmv_offset;
396 }
397
398 /* Set rlc base address (input stream) */
399 rlc_addr = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0);
400 regs->common_addr.reg128_strm_base = rlc_addr;
401
402 /* Set output base address */
403 dst_addr = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0);
404 regs->h26x_addr.reg168_decout_base = dst_addr;
405 regs->h26x_addr.reg169_error_ref_base = dst_addr;
406 regs->h26x_addr.reg192_payload_st_cur_base = dst_addr;
407
408 /* Set colmv address */
409 regs->h26x_addr.reg216_colmv_cur_base = dst_addr + ctx->colmv_offset;
410
411 /* Set RCB addresses */
412 for (i = 0; i < rkvdec_rcb_buf_count(ctx); i++) {
413 regs->common_addr.reg140_162_rcb_info[i].offset = rkvdec_rcb_buf_dma_addr(ctx, i);
414 regs->common_addr.reg140_162_rcb_info[i].size = rkvdec_rcb_buf_size(ctx, i);
415 }
416
417 /* Set hw pps address */
418 offset = offsetof(struct rkvdec_h264_priv_tbl, param_set);
419 regs->common_addr.reg131_gbl_base = priv_start_addr + offset;
420 regs->h26x_params.reg067_global_len = sizeof(struct rkvdec_sps_pps) / 16;
421
422 /* Set hw rps address */
423 offset = offsetof(struct rkvdec_h264_priv_tbl, rps);
424 regs->common_addr.reg129_rps_base = priv_start_addr + offset;
425
426 /* Set cabac table */
427 offset = offsetof(struct rkvdec_h264_priv_tbl, cabac_table);
428 regs->common_addr.reg130_cabactbl_base = priv_start_addr + offset;
429
430 /* Set scaling list address */
431 offset = offsetof(struct rkvdec_h264_priv_tbl, scaling_list);
432 regs->common_addr.reg132_scanlist_addr = priv_start_addr + offset;
433
434 rkvdec_write_regs(ctx);
435 }
436
rkvdec_h264_start(struct rkvdec_ctx * ctx)437 static int rkvdec_h264_start(struct rkvdec_ctx *ctx)
438 {
439 struct rkvdec_dev *rkvdec = ctx->dev;
440 struct rkvdec_h264_priv_tbl *priv_tbl;
441 struct rkvdec_h264_ctx *h264_ctx;
442 struct v4l2_ctrl *ctrl;
443 int ret;
444
445 ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl,
446 V4L2_CID_STATELESS_H264_SPS);
447 if (!ctrl)
448 return -EINVAL;
449
450 ret = rkvdec_h264_validate_sps(ctx, ctrl->p_new.p_h264_sps);
451 if (ret)
452 return ret;
453
454 h264_ctx = kzalloc_obj(*h264_ctx);
455 if (!h264_ctx)
456 return -ENOMEM;
457
458 priv_tbl = dma_alloc_coherent(rkvdec->dev, sizeof(*priv_tbl),
459 &h264_ctx->priv_tbl.dma, GFP_KERNEL);
460 if (!priv_tbl) {
461 ret = -ENOMEM;
462 goto err_free_ctx;
463 }
464
465 h264_ctx->priv_tbl.size = sizeof(*priv_tbl);
466 h264_ctx->priv_tbl.cpu = priv_tbl;
467 memcpy(priv_tbl->cabac_table, rkvdec_h264_cabac_table,
468 sizeof(rkvdec_h264_cabac_table));
469
470 ctx->priv = h264_ctx;
471
472 return 0;
473
474 err_free_ctx:
475 kfree(h264_ctx);
476 return ret;
477 }
478
rkvdec_h264_stop(struct rkvdec_ctx * ctx)479 static void rkvdec_h264_stop(struct rkvdec_ctx *ctx)
480 {
481 struct rkvdec_h264_ctx *h264_ctx = ctx->priv;
482 struct rkvdec_dev *rkvdec = ctx->dev;
483
484 dma_free_coherent(rkvdec->dev, h264_ctx->priv_tbl.size,
485 h264_ctx->priv_tbl.cpu, h264_ctx->priv_tbl.dma);
486 kfree(h264_ctx);
487 }
488
rkvdec_h264_run(struct rkvdec_ctx * ctx)489 static int rkvdec_h264_run(struct rkvdec_ctx *ctx)
490 {
491 struct v4l2_h264_reflist_builder reflist_builder;
492 struct rkvdec_dev *rkvdec = ctx->dev;
493 struct rkvdec_h264_ctx *h264_ctx = ctx->priv;
494 struct rkvdec_h264_run run;
495 struct rkvdec_h264_priv_tbl *tbl = h264_ctx->priv_tbl.cpu;
496 u32 timeout_threshold;
497
498 rkvdec_h264_run_preamble(ctx, &run);
499
500 /* Build the P/B{0,1} ref lists. */
501 v4l2_h264_init_reflist_builder(&reflist_builder, run.decode_params,
502 run.sps, run.decode_params->dpb);
503 v4l2_h264_build_p_ref_list(&reflist_builder, h264_ctx->reflists.p);
504 v4l2_h264_build_b_ref_lists(&reflist_builder, h264_ctx->reflists.b0,
505 h264_ctx->reflists.b1);
506
507 assemble_hw_scaling_list(&run, &tbl->scaling_list);
508 assemble_hw_pps(ctx, &run);
509 lookup_ref_buf_idx(ctx, &run);
510 assemble_hw_rps(&reflist_builder, &run, &h264_ctx->reflists, &tbl->rps);
511
512 config_registers(ctx, &run);
513
514 rkvdec_run_postamble(ctx, &run.base);
515
516 timeout_threshold = h264_ctx->regs.common.reg013_core_timeout_threshold;
517 rkvdec_schedule_watchdog(rkvdec, timeout_threshold);
518
519 /* Start decoding! */
520 writel(timeout_threshold, rkvdec->link + VDPU383_LINK_TIMEOUT_THRESHOLD);
521 writel(0, rkvdec->link + VDPU383_LINK_IP_ENABLE);
522 writel(VDPU383_DEC_E_BIT, rkvdec->link + VDPU383_LINK_DEC_ENABLE);
523
524 return 0;
525 }
526
rkvdec_h264_try_ctrl(struct rkvdec_ctx * ctx,struct v4l2_ctrl * ctrl)527 static int rkvdec_h264_try_ctrl(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl)
528 {
529 if (ctrl->id == V4L2_CID_STATELESS_H264_SPS)
530 return rkvdec_h264_validate_sps(ctx, ctrl->p_new.p_h264_sps);
531
532 return 0;
533 }
534
535 const struct rkvdec_coded_fmt_ops rkvdec_vdpu383_h264_fmt_ops = {
536 .adjust_fmt = rkvdec_h264_adjust_fmt,
537 .get_image_fmt = rkvdec_h264_get_image_fmt,
538 .start = rkvdec_h264_start,
539 .stop = rkvdec_h264_stop,
540 .run = rkvdec_h264_run,
541 .try_ctrl = rkvdec_h264_try_ctrl,
542 };
543