| /linux/drivers/gpu/drm/amd/amdgpu/ ! |
| H A D | umc_v8_7.c | 44 uint32_t umc_inst, in get_umc_v8_7_reg_offset() argument
51 uint32_t umc_inst, uint32_t ch_inst, in umc_v8_7_ecc_info_query_correctable_error_count() argument
70 uint32_t umc_inst, uint32_t ch_inst, in umc_v8_7_ecc_info_querry_uncorrectable_error_count() argument
95 uint32_t umc_inst = 0; in umc_v8_7_ecc_info_query_ras_error_count() local
113 umc_v8_7_convert_error_address(struct amdgpu_device * adev,struct ras_err_data * err_data,uint64_t err_addr,uint32_t ch_inst,uint32_t umc_inst) umc_v8_7_convert_error_address() argument
133 umc_v8_7_ecc_info_query_error_address(struct amdgpu_device * adev,struct ras_err_data * err_data,uint32_t ch_inst,uint32_t umc_inst) umc_v8_7_ecc_info_query_error_address() argument
165 uint32_t umc_inst = 0; umc_v8_7_ecc_info_query_ras_error_address() local
220 uint32_t umc_inst = 0; umc_v8_7_clear_error_count() local
306 uint32_t umc_inst = 0; umc_v8_7_query_ras_error_count() local
330 umc_v8_7_query_error_address(struct amdgpu_device * adev,struct ras_err_data * err_data,uint32_t umc_reg_offset,uint32_t ch_inst,uint32_t umc_inst) umc_v8_7_query_error_address() argument
373 uint32_t umc_inst = 0; umc_v8_7_query_ras_error_address() local
421 uint32_t umc_inst = 0; umc_v8_7_err_cnt_init() local
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| H A D | umc_v8_10.c | 72 uint32_t umc_inst, in get_umc_v8_10_reg_offset() argument
80 uint32_t node_inst, uint32_t umc_inst, in umc_v8_10_clear_error_count_per_channel() argument
144 uint32_t node_inst, uint32_t umc_inst, in umc_v8_10_query_ecc_error_count() argument
207 uint32_t ch_inst, uint32_t umc_inst, in umc_v8_10_convert_error_address() argument
245 uint32_t node_inst, uint32_t umc_inst, in umc_v8_10_query_error_address() argument
295 umc_v8_10_err_cnt_init_per_channel(struct amdgpu_device * adev,uint32_t node_inst,uint32_t umc_inst,uint32_t ch_inst,void * data) umc_v8_10_err_cnt_init_per_channel() argument
336 umc_v8_10_ecc_info_query_correctable_error_count(struct amdgpu_device * adev,uint32_t node_inst,uint32_t umc_inst,uint32_t ch_inst,unsigned long * error_count) umc_v8_10_ecc_info_query_correctable_error_count() argument
355 umc_v8_10_ecc_info_query_uncorrectable_error_count(struct amdgpu_device * adev,uint32_t node_inst,uint32_t umc_inst,uint32_t ch_inst,unsigned long * error_count) umc_v8_10_ecc_info_query_uncorrectable_error_count() argument
380 umc_v8_10_ecc_info_query_ecc_error_count(struct amdgpu_device * adev,uint32_t node_inst,uint32_t umc_inst,uint32_t ch_inst,void * data) umc_v8_10_ecc_info_query_ecc_error_count() argument
402 umc_v8_10_ecc_info_query_error_address(struct amdgpu_device * adev,uint32_t node_inst,uint32_t umc_inst,uint32_t ch_inst,void * data) umc_v8_10_ecc_info_query_error_address() argument
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| H A D | umc_v6_1.c | 88 uint32_t umc_inst, in get_umc_6_reg_offset() argument
147 uint32_t umc_inst = 0; in umc_v6_1_clear_error_count() local
259 uint32_t umc_inst = 0; in umc_v6_1_query_ras_error_count() local
299 uint32_t umc_inst) in umc_v6_1_query_error_address() argument
358 uint32_t umc_inst = 0; umc_v6_1_query_ras_error_address() local
431 uint32_t umc_inst = 0; umc_v6_1_err_cnt_init() local
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| H A D | umc_v8_14.c | 31 uint32_t umc_inst, in get_umc_v8_14_reg_offset() argument
38 uint32_t node_inst, uint32_t umc_inst, in umc_v8_14_clear_error_count_per_channel() argument
93 uint32_t node_inst, uint32_t umc_inst, in umc_v8_14_query_error_count_per_channel() argument
120 uint32_t node_inst, uint32_t umc_inst, in umc_v8_14_err_cnt_init_per_channel() argument
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| H A D | amdgpu_umc.c | 33 uint32_t ch_inst, uint32_t umc_inst) in amdgpu_umc_convert_error_address() argument
50 uint64_t err_addr, uint32_t ch_inst, uint32_t umc_inst) in amdgpu_umc_page_retirement_mca() argument
365 uint32_t umc_inst) in amdgpu_umc_fill_error_record() argument
395 uint32_t umc_inst; in amdgpu_umc_loop_all_aid() local
433 uint32_t umc_inst = 0; amdgpu_umc_loop_channels() local
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| H A D | umc_v12_0.c | 36 uint32_t umc_inst, in get_umc_v12_0_reg_offset() argument
50 uint32_t node_inst, uint32_t umc_inst, in umc_v12_0_reset_error_count_per_channel() argument
138 uint32_t node_inst, uint32_t umc_inst, in umc_v12_0_query_error_count() argument
242 uint32_t channel_index = 0, umc_inst = 0; in umc_v12_0_convert_error_address() local
327 umc_v12_0_query_error_address(struct amdgpu_device * adev,uint32_t node_inst,uint32_t umc_inst,uint32_t ch_inst,void * data) umc_v12_0_query_error_address() argument
392 umc_v12_0_err_cnt_init_per_channel(struct amdgpu_device * adev,uint32_t node_inst,uint32_t umc_inst,uint32_t ch_inst,void * data) umc_v12_0_err_cnt_init_per_channel() argument
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| H A D | amdgpu_umc.h | 45 #define LOOP_UMC_INST(umc_inst) for ((umc_inst) = 0; (umc_inst) < adev->umc.umc_inst_num; (umc_inst)++) argument
47 #define LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) LOOP_UMC_INST((umc_inst)) LOOP_UMC_CH_INST((ch_inst)) argument
52 #define LOOP_UMC_EACH_NODE_INST_AND_CH(node_inst, umc_inst, ch_inst) \ argument
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| H A D | ta_ras_if.h | 163 uint32_t umc_inst; member
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| H A D | amdgpu_ras.c | 4615 uint32_t umc_inst = 0, ch_inst = 0; in amdgpu_bad_page_notifier() local
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