1// SPDX-License-Identifier: BSD-3-Clause 2/* Copyright (c) 2022, The Linux Foundation. All rights reserved. */ 3 4#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 5#include <dt-bindings/clock/qcom,gcc-msm8953.h> 6#include <dt-bindings/clock/qcom,rpmcc.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interconnect/qcom,msm8953.h> 9#include <dt-bindings/interconnect/qcom,rpm-icc.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/power/qcom-rpmpd.h> 12#include <dt-bindings/soc/qcom,apr.h> 13#include <dt-bindings/sound/qcom,q6afe.h> 14#include <dt-bindings/sound/qcom,q6asm.h> 15#include <dt-bindings/thermal/thermal.h> 16 17/ { 18 interrupt-parent = <&intc>; 19 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 chosen { }; 24 25 clocks { 26 sleep_clk: sleep-clk { 27 compatible = "fixed-clock"; 28 #clock-cells = <0>; 29 clock-frequency = <32768>; 30 }; 31 32 xo_board: xo-board { 33 compatible = "fixed-clock"; 34 #clock-cells = <0>; 35 clock-frequency = <19200000>; 36 clock-output-names = "xo"; 37 }; 38 }; 39 40 cpus { 41 #address-cells = <1>; 42 #size-cells = <0>; 43 44 cpu0: cpu@0 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a53"; 47 reg = <0x0>; 48 enable-method = "psci"; 49 capacity-dmips-mhz = <1024>; 50 interconnects = <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG 51 &bimc SLV_EBI RPM_ACTIVE_TAG>; 52 next-level-cache = <&l2_0>; 53 #cooling-cells = <2>; 54 }; 55 56 cpu1: cpu@1 { 57 device_type = "cpu"; 58 compatible = "arm,cortex-a53"; 59 reg = <0x1>; 60 enable-method = "psci"; 61 capacity-dmips-mhz = <1024>; 62 interconnects = <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG 63 &bimc SLV_EBI RPM_ACTIVE_TAG>; 64 next-level-cache = <&l2_0>; 65 #cooling-cells = <2>; 66 }; 67 68 cpu2: cpu@2 { 69 device_type = "cpu"; 70 compatible = "arm,cortex-a53"; 71 reg = <0x2>; 72 enable-method = "psci"; 73 capacity-dmips-mhz = <1024>; 74 interconnects = <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG 75 &bimc SLV_EBI RPM_ACTIVE_TAG>; 76 next-level-cache = <&l2_0>; 77 #cooling-cells = <2>; 78 }; 79 80 cpu3: cpu@3 { 81 device_type = "cpu"; 82 compatible = "arm,cortex-a53"; 83 reg = <0x3>; 84 enable-method = "psci"; 85 capacity-dmips-mhz = <1024>; 86 interconnects = <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG 87 &bimc SLV_EBI RPM_ACTIVE_TAG>; 88 next-level-cache = <&l2_0>; 89 #cooling-cells = <2>; 90 }; 91 92 cpu4: cpu@100 { 93 device_type = "cpu"; 94 compatible = "arm,cortex-a53"; 95 reg = <0x100>; 96 enable-method = "psci"; 97 capacity-dmips-mhz = <1024>; 98 interconnects = <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG 99 &bimc SLV_EBI RPM_ACTIVE_TAG>; 100 next-level-cache = <&l2_1>; 101 #cooling-cells = <2>; 102 }; 103 104 cpu5: cpu@101 { 105 device_type = "cpu"; 106 compatible = "arm,cortex-a53"; 107 reg = <0x101>; 108 enable-method = "psci"; 109 capacity-dmips-mhz = <1024>; 110 interconnects = <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG 111 &bimc SLV_EBI RPM_ACTIVE_TAG>; 112 next-level-cache = <&l2_1>; 113 #cooling-cells = <2>; 114 }; 115 116 cpu6: cpu@102 { 117 device_type = "cpu"; 118 compatible = "arm,cortex-a53"; 119 reg = <0x102>; 120 enable-method = "psci"; 121 capacity-dmips-mhz = <1024>; 122 interconnects = <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG 123 &bimc SLV_EBI RPM_ACTIVE_TAG>; 124 next-level-cache = <&l2_1>; 125 #cooling-cells = <2>; 126 }; 127 128 cpu7: cpu@103 { 129 device_type = "cpu"; 130 compatible = "arm,cortex-a53"; 131 reg = <0x103>; 132 enable-method = "psci"; 133 capacity-dmips-mhz = <1024>; 134 interconnects = <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG 135 &bimc SLV_EBI RPM_ACTIVE_TAG>; 136 next-level-cache = <&l2_1>; 137 #cooling-cells = <2>; 138 }; 139 140 cpu-map { 141 cluster0 { 142 core0 { 143 cpu = <&cpu0>; 144 }; 145 core1 { 146 cpu = <&cpu1>; 147 }; 148 core2 { 149 cpu = <&cpu2>; 150 }; 151 core3 { 152 cpu = <&cpu3>; 153 }; 154 }; 155 156 cluster1 { 157 core0 { 158 cpu = <&cpu4>; 159 }; 160 core1 { 161 cpu = <&cpu5>; 162 }; 163 core2 { 164 cpu = <&cpu6>; 165 }; 166 core3 { 167 cpu = <&cpu7>; 168 }; 169 }; 170 }; 171 172 l2_0: l2-cache-0 { 173 compatible = "cache"; 174 cache-level = <2>; 175 cache-unified; 176 }; 177 178 l2_1: l2-cache-1 { 179 compatible = "cache"; 180 cache-level = <2>; 181 cache-unified; 182 }; 183 }; 184 185 firmware { 186 scm: scm { 187 compatible = "qcom,scm-msm8953", "qcom,scm"; 188 clocks = <&gcc GCC_CRYPTO_CLK>, 189 <&gcc GCC_CRYPTO_AXI_CLK>, 190 <&gcc GCC_CRYPTO_AHB_CLK>; 191 clock-names = "core", "bus", "iface"; 192 #reset-cells = <1>; 193 }; 194 }; 195 196 memory@10000000 { 197 device_type = "memory"; 198 /* We expect the bootloader to fill in the reg */ 199 reg = <0 0x10000000 0 0>; 200 }; 201 202 pmu { 203 compatible = "arm,cortex-a53-pmu"; 204 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 205 }; 206 207 psci { 208 compatible = "arm,psci-1.0"; 209 method = "smc"; 210 }; 211 212 rpm: remoteproc { 213 compatible = "qcom,msm8953-rpm-proc", "qcom,rpm-proc"; 214 215 smd-edge { 216 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 217 mboxes = <&apcs 0>; 218 qcom,smd-edge = <15>; 219 220 rpm_requests: rpm-requests { 221 compatible = "qcom,rpm-msm8953", "qcom,smd-rpm"; 222 qcom,smd-channels = "rpm_requests"; 223 224 rpmcc: clock-controller { 225 compatible = "qcom,rpmcc-msm8953", "qcom,rpmcc"; 226 clocks = <&xo_board>; 227 clock-names = "xo"; 228 #clock-cells = <1>; 229 }; 230 231 rpmpd: power-controller { 232 compatible = "qcom,msm8953-rpmpd"; 233 #power-domain-cells = <1>; 234 operating-points-v2 = <&rpmpd_opp_table>; 235 236 rpmpd_opp_table: opp-table { 237 compatible = "operating-points-v2"; 238 239 rpmpd_opp_ret: opp1 { 240 opp-level = <RPM_SMD_LEVEL_RETENTION>; 241 }; 242 243 rpmpd_opp_ret_plus: opp2 { 244 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; 245 }; 246 247 rpmpd_opp_min_svs: opp3 { 248 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 249 }; 250 251 rpmpd_opp_low_svs: opp4 { 252 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 253 }; 254 255 rpmpd_opp_svs: opp5 { 256 opp-level = <RPM_SMD_LEVEL_SVS>; 257 }; 258 259 rpmpd_opp_svs_plus: opp6 { 260 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 261 }; 262 263 rpmpd_opp_nom: opp7 { 264 opp-level = <RPM_SMD_LEVEL_NOM>; 265 }; 266 267 rpmpd_opp_nom_plus: opp8 { 268 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 269 }; 270 271 rpmpd_opp_turbo: opp9 { 272 opp-level = <RPM_SMD_LEVEL_TURBO>; 273 }; 274 }; 275 }; 276 }; 277 }; 278 }; 279 280 reserved-memory { 281 #address-cells = <2>; 282 #size-cells = <2>; 283 ranges; 284 285 zap_shader_region: zap@81800000 { 286 compatible = "shared-dma-pool"; 287 reg = <0x0 0x81800000 0x0 0x2000>; 288 no-map; 289 }; 290 291 qseecom_mem: qseecom@85b00000 { 292 reg = <0x0 0x85b00000 0x0 0x800000>; 293 no-map; 294 }; 295 296 smem_mem: smem@86300000 { 297 compatible = "qcom,smem"; 298 reg = <0x0 0x86300000 0x0 0x100000>; 299 qcom,rpm-msg-ram = <&rpm_msg_ram>; 300 hwlocks = <&tcsr_mutex 3>; 301 no-map; 302 }; 303 304 reserved@86400000 { 305 reg = <0x0 0x86400000 0x0 0x400000>; 306 no-map; 307 }; 308 309 mpss_mem: mpss@86c00000 { 310 reg = <0x0 0x86c00000 0x0 0x6a00000>; 311 no-map; 312 }; 313 314 adsp_fw_mem: adsp@8d600000 { 315 reg = <0x0 0x8d600000 0x0 0x1100000>; 316 no-map; 317 }; 318 319 wcnss_fw_mem: wcnss@8e700000 { 320 reg = <0x0 0x8e700000 0x0 0x700000>; 321 no-map; 322 }; 323 324 dfps_data_mem: dfps-data@90000000 { 325 reg = <0 0x90000000 0 0x1000>; 326 no-map; 327 }; 328 329 cont_splash_mem: cont-splash@90001000 { 330 reg = <0x0 0x90001000 0x0 0x13ff000>; 331 no-map; 332 }; 333 334 venus_mem: venus@91400000 { 335 reg = <0x0 0x91400000 0x0 0x700000>; 336 no-map; 337 }; 338 339 mba_mem: mba@92000000 { 340 reg = <0x0 0x92000000 0x0 0x100000>; 341 no-map; 342 }; 343 344 rmtfs@f2d00000 { 345 compatible = "qcom,rmtfs-mem"; 346 reg = <0x0 0xf2d00000 0x0 0x180000>; 347 no-map; 348 349 qcom,client-id = <1>; 350 }; 351 }; 352 353 smp2p-adsp { 354 compatible = "qcom,smp2p"; 355 qcom,smem = <443>, <429>; 356 357 interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>; 358 359 mboxes = <&apcs 10>; 360 361 qcom,local-pid = <0>; 362 qcom,remote-pid = <2>; 363 364 smp2p_adsp_out: master-kernel { 365 qcom,entry-name = "master-kernel"; 366 #qcom,smem-state-cells = <1>; 367 }; 368 369 smp2p_adsp_in: slave-kernel { 370 qcom,entry-name = "slave-kernel"; 371 372 interrupt-controller; 373 #interrupt-cells = <2>; 374 }; 375 }; 376 377 smp2p-modem { 378 compatible = "qcom,smp2p"; 379 qcom,smem = <435>, <428>; 380 381 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; 382 383 mboxes = <&apcs 14>; 384 385 qcom,local-pid = <0>; 386 qcom,remote-pid = <1>; 387 388 smp2p_modem_out: master-kernel { 389 qcom,entry-name = "master-kernel"; 390 391 #qcom,smem-state-cells = <1>; 392 }; 393 394 smp2p_modem_in: slave-kernel { 395 qcom,entry-name = "slave-kernel"; 396 397 interrupt-controller; 398 #interrupt-cells = <2>; 399 }; 400 }; 401 402 smp2p-wcnss { 403 compatible = "qcom,smp2p"; 404 qcom,smem = <451>, <431>; 405 406 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; 407 408 mboxes = <&apcs 18>; 409 410 qcom,local-pid = <0>; 411 qcom,remote-pid = <4>; 412 413 smp2p_wcnss_out: master-kernel { 414 qcom,entry-name = "master-kernel"; 415 416 #qcom,smem-state-cells = <1>; 417 }; 418 419 smp2p_wcnss_in: slave-kernel { 420 qcom,entry-name = "slave-kernel"; 421 422 interrupt-controller; 423 #interrupt-cells = <2>; 424 }; 425 }; 426 427 smsm { 428 compatible = "qcom,smsm"; 429 430 #address-cells = <1>; 431 #size-cells = <0>; 432 433 mboxes = <0>, <&apcs 13>, <0>, <&apcs 19>; 434 435 apps_smsm: apps@0 { 436 reg = <0>; 437 438 #qcom,smem-state-cells = <1>; 439 }; 440 441 modem_smsm: modem@1 { 442 reg = <1>; 443 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 444 445 interrupt-controller; 446 #interrupt-cells = <2>; 447 }; 448 449 wcnss_smsm: wcnss@6 { 450 reg = <6>; 451 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; 452 453 interrupt-controller; 454 #interrupt-cells = <2>; 455 }; 456 }; 457 458 soc: soc@0 { 459 #address-cells = <1>; 460 #size-cells = <1>; 461 ranges = <0 0 0 0xffffffff>; 462 compatible = "simple-bus"; 463 464 rpm_msg_ram: sram@60000 { 465 compatible = "qcom,rpm-msg-ram"; 466 reg = <0x00060000 0x8000>; 467 }; 468 469 hsusb_phy: phy@79000 { 470 compatible = "qcom,msm8953-qusb2-phy"; 471 reg = <0x00079000 0x180>; 472 #phy-cells = <0>; 473 474 clocks = <&gcc GCC_USB_PHY_CFG_AHB_CLK>, 475 <&gcc GCC_QUSB_REF_CLK>; 476 clock-names = "cfg_ahb", "ref"; 477 478 qcom,tcsr-syscon = <&tcsr_phy_clk_scheme_sel>; 479 480 resets = <&gcc GCC_QUSB2_PHY_BCR>; 481 482 status = "disabled"; 483 }; 484 485 rng@e3000 { 486 compatible = "qcom,prng"; 487 reg = <0x000e3000 0x1000>; 488 clocks = <&gcc GCC_PRNG_AHB_CLK>; 489 clock-names = "core"; 490 }; 491 492 bimc: interconnect@400000 { 493 compatible = "qcom,msm8953-bimc"; 494 reg = <0x00400000 0x5a000>; 495 496 #interconnect-cells = <2>; 497 }; 498 499 tsens0: thermal-sensor@4a9000 { 500 compatible = "qcom,msm8953-tsens", "qcom,tsens-v2"; 501 reg = <0x004a9000 0x1000>, /* TM */ 502 <0x004a8000 0x1000>; /* SROT */ 503 #qcom,sensors = <16>; 504 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 505 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>; 506 interrupt-names = "uplow", "critical"; 507 #thermal-sensor-cells = <1>; 508 }; 509 510 restart@4ab000 { 511 compatible = "qcom,pshold"; 512 reg = <0x004ab000 0x4>; 513 }; 514 515 pcnoc: interconnect@500000 { 516 compatible = "qcom,msm8953-pcnoc"; 517 reg = <0x00500000 0x12080>; 518 519 clocks = <&gcc GCC_PCNOC_USB3_AXI_CLK>; 520 clock-names = "pcnoc_usb3_axi"; 521 522 #interconnect-cells = <2>; 523 }; 524 525 snoc: interconnect@580000 { 526 compatible = "qcom,msm8953-snoc"; 527 reg = <0x00580000 0x16080>; 528 529 #interconnect-cells = <2>; 530 531 snoc_mm: interconnect-snoc { 532 compatible = "qcom,msm8953-snoc-mm"; 533 534 #interconnect-cells = <2>; 535 }; 536 }; 537 538 tlmm: pinctrl@1000000 { 539 compatible = "qcom,msm8953-pinctrl"; 540 reg = <0x01000000 0x300000>; 541 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 542 gpio-controller; 543 gpio-ranges = <&tlmm 0 0 142>; 544 #gpio-cells = <2>; 545 interrupt-controller; 546 #interrupt-cells = <2>; 547 548 i2c_1_default: i2c-1-default-state { 549 pins = "gpio2", "gpio3"; 550 function = "blsp_i2c1"; 551 drive-strength = <2>; 552 bias-disable; 553 }; 554 555 i2c_1_sleep: i2c-1-sleep-state { 556 pins = "gpio2", "gpio3"; 557 function = "gpio"; 558 drive-strength = <2>; 559 bias-disable; 560 }; 561 562 uart_console_active: uart-console-active-state { 563 pins = "gpio4", "gpio5"; 564 function = "blsp_uart2"; 565 drive-strength = <2>; 566 bias-disable; 567 }; 568 569 uart_console_sleep: uart-console-sleep-state { 570 pins = "gpio4", "gpio5"; 571 function = "blsp_uart2"; 572 drive-strength = <2>; 573 bias-pull-down; 574 }; 575 576 i2c_2_default: i2c-2-default-state { 577 pins = "gpio6", "gpio7"; 578 function = "blsp_i2c2"; 579 drive-strength = <2>; 580 bias-disable; 581 }; 582 583 i2c_2_sleep: i2c-2-sleep-state { 584 pins = "gpio6", "gpio7"; 585 function = "gpio"; 586 drive-strength = <2>; 587 bias-disable; 588 }; 589 590 spi_3_default: spi-3-default-state { 591 cs-pins { 592 pins = "gpio10"; 593 function = "blsp_spi3"; 594 drive-strength = <2>; 595 bias-disable; 596 }; 597 598 spi-pins { 599 pins = "gpio8", "gpio9", "gpio11"; 600 function = "blsp_spi3"; 601 drive-strength = <12>; 602 bias-disable; 603 }; 604 }; 605 606 spi_3_sleep: spi-3-sleep-state { 607 cs-pins { 608 pins = "gpio10"; 609 function = "gpio"; 610 drive-strength = <2>; 611 bias-disable; 612 }; 613 614 spi-pins { 615 pins = "gpio8", "gpio9", "gpio11"; 616 function = "gpio"; 617 drive-strength = <2>; 618 bias-pull-down; 619 }; 620 }; 621 622 i2c_3_default: i2c-3-default-state { 623 pins = "gpio10", "gpio11"; 624 function = "blsp_i2c3"; 625 drive-strength = <2>; 626 bias-disable; 627 }; 628 629 i2c_3_sleep: i2c-3-sleep-state { 630 pins = "gpio10", "gpio11"; 631 function = "gpio"; 632 drive-strength = <2>; 633 bias-disable; 634 }; 635 636 i2c_4_default: i2c-4-default-state { 637 pins = "gpio14", "gpio15"; 638 function = "blsp_i2c4"; 639 drive-strength = <2>; 640 bias-disable; 641 }; 642 643 i2c_4_sleep: i2c-4-sleep-state { 644 pins = "gpio14", "gpio15"; 645 function = "gpio"; 646 drive-strength = <2>; 647 bias-disable; 648 }; 649 650 spi_5_default: spi-5-default-state { 651 cs-pins { 652 pins = "gpio18"; 653 function = "blsp_spi5"; 654 drive-strength = <2>; 655 bias-disable; 656 }; 657 658 spi-pins { 659 pins = "gpio16", "gpio17", "gpio19"; 660 function = "blsp_spi5"; 661 drive-strength = <12>; 662 bias-disable; 663 }; 664 }; 665 666 spi_5_sleep: spi-5-sleep-state { 667 cs-pins { 668 pins = "gpio18"; 669 function = "gpio"; 670 drive-strength = <2>; 671 bias-disable; 672 }; 673 674 spi-pins { 675 pins = "gpio16", "gpio17", "gpio19"; 676 function = "gpio"; 677 drive-strength = <2>; 678 bias-pull-down; 679 }; 680 }; 681 682 uart_5_default: uart-5-default-state { 683 pins = "gpio16", "gpio17", "gpio18", "gpio19"; 684 function = "blsp_uart5"; 685 drive-strength = <16>; 686 bias-disable; 687 }; 688 689 uart_5_sleep: uart-5-sleep-state { 690 pins = "gpio16", "gpio17", "gpio18", "gpio19"; 691 function = "gpio"; 692 drive-strength = <2>; 693 bias-disable; 694 }; 695 696 i2c_5_default: i2c-5-default-state { 697 pins = "gpio18", "gpio19"; 698 function = "blsp_i2c5"; 699 drive-strength = <2>; 700 bias-disable; 701 }; 702 703 i2c_5_sleep: i2c-5-sleep-state { 704 pins = "gpio18", "gpio19"; 705 function = "gpio"; 706 drive-strength = <2>; 707 bias-disable; 708 }; 709 710 spi_6_default: spi-6-default-state { 711 cs-pins { 712 pins = "gpio22"; 713 function = "blsp_spi6"; 714 drive-strength = <2>; 715 bias-disable; 716 }; 717 718 spi-pins { 719 pins = "gpio20", "gpio21", "gpio23"; 720 function = "blsp_spi6"; 721 drive-strength = <12>; 722 bias-disable; 723 }; 724 }; 725 726 spi_6_sleep: spi-6-sleep-state { 727 cs-pins { 728 pins = "gpio22"; 729 function = "gpio"; 730 drive-strength = <2>; 731 bias-disable; 732 }; 733 734 spi-pins { 735 pins = "gpio20", "gpio21", "gpio23"; 736 function = "gpio"; 737 drive-strength = <2>; 738 bias-pull-down; 739 }; 740 }; 741 742 i2c_6_default: i2c-6-default-state { 743 pins = "gpio22", "gpio23"; 744 function = "blsp_i2c6"; 745 drive-strength = <2>; 746 bias-disable; 747 }; 748 749 i2c_6_sleep: i2c-6-sleep-state { 750 pins = "gpio22", "gpio23"; 751 function = "gpio"; 752 drive-strength = <2>; 753 bias-disable; 754 }; 755 756 cci0_default: cci0-default-state { 757 pins = "gpio29", "gpio30"; 758 function = "cci_i2c"; 759 drive-strength = <2>; 760 bias-disable; 761 }; 762 763 cci1_default: cci1-default-state { 764 pins = "gpio31", "gpio32"; 765 function = "cci_i2c"; 766 drive-strength = <2>; 767 bias-disable; 768 }; 769 770 wcnss_pin_a: wcnss-active-state { 771 wcss-wlan2-pins { 772 pins = "gpio76"; 773 function = "wcss_wlan2"; 774 drive-strength = <6>; 775 bias-pull-up; 776 }; 777 778 wcss-wlan1-pins { 779 pins = "gpio77"; 780 function = "wcss_wlan1"; 781 drive-strength = <6>; 782 bias-pull-up; 783 }; 784 785 wcss-wlan0-pins { 786 pins = "gpio78"; 787 function = "wcss_wlan0"; 788 drive-strength = <6>; 789 bias-pull-up; 790 }; 791 792 wcss-wlan-pins { 793 pins = "gpio79", "gpio80"; 794 function = "wcss_wlan"; 795 drive-strength = <6>; 796 bias-pull-up; 797 }; 798 }; 799 800 gpio_key_default: gpio-key-default-state { 801 pins = "gpio85"; 802 function = "gpio"; 803 drive-strength = <2>; 804 bias-pull-up; 805 }; 806 807 i2c_8_default: i2c-8-default-state { 808 pins = "gpio98", "gpio99"; 809 function = "blsp_i2c8"; 810 drive-strength = <2>; 811 bias-disable; 812 }; 813 814 i2c_8_sleep: i2c-8-sleep-state { 815 pins = "gpio98", "gpio99"; 816 function = "gpio"; 817 drive-strength = <2>; 818 bias-disable; 819 }; 820 821 sdc2_cd_on: cd-on-state { 822 pins = "gpio133"; 823 function = "gpio"; 824 drive-strength = <2>; 825 bias-pull-up; 826 }; 827 828 sdc2_cd_off: cd-off-state { 829 pins = "gpio133"; 830 function = "gpio"; 831 drive-strength = <2>; 832 bias-disable; 833 }; 834 835 i2c_7_default: i2c-7-default-state { 836 pins = "gpio135", "gpio136"; 837 function = "blsp_i2c7"; 838 drive-strength = <2>; 839 bias-disable; 840 }; 841 842 i2c_7_sleep: i2c-7-sleep-state { 843 pins = "gpio135", "gpio136"; 844 function = "gpio"; 845 drive-strength = <2>; 846 bias-disable; 847 }; 848 849 spi_7_default: spi-7-default-state { 850 cs-pins { 851 pins = "gpio136"; 852 function = "blsp_spi7"; 853 drive-strength = <2>; 854 bias-disable; 855 }; 856 857 spi-pins { 858 pins = "gpio135", "gpio137", "gpio138"; 859 function = "blsp_spi7"; 860 drive-strength = <12>; 861 bias-disable; 862 }; 863 }; 864 865 spi_7_sleep: spi-7-sleep-state { 866 cs-pins { 867 pins = "gpio136"; 868 function = "gpio"; 869 drive-strength = <2>; 870 bias-disable; 871 }; 872 873 spi-pins { 874 pins = "gpio135", "gpio137", "gpio138"; 875 function = "gpio"; 876 drive-strength = <2>; 877 bias-pull-down; 878 }; 879 }; 880 881 sdc1_clk_on: sdc1-clk-on-state { 882 pins = "sdc1_clk"; 883 bias-disable; 884 drive-strength = <16>; 885 }; 886 887 sdc1_clk_off: sdc1-clk-off-state { 888 pins = "sdc1_clk"; 889 bias-disable; 890 drive-strength = <2>; 891 }; 892 893 sdc1_cmd_on: sdc1-cmd-on-state { 894 pins = "sdc1_cmd"; 895 bias-disable; 896 drive-strength = <10>; 897 }; 898 899 sdc1_cmd_off: sdc1-cmd-off-state { 900 pins = "sdc1_cmd"; 901 bias-disable; 902 drive-strength = <2>; 903 }; 904 905 sdc1_data_on: sdc1-data-on-state { 906 pins = "sdc1_data"; 907 bias-pull-up; 908 drive-strength = <10>; 909 }; 910 911 sdc1_data_off: sdc1-data-off-state { 912 pins = "sdc1_data"; 913 bias-pull-up; 914 drive-strength = <2>; 915 }; 916 917 sdc1_rclk_on: sdc1-rclk-on-state { 918 pins = "sdc1_rclk"; 919 bias-pull-down; 920 }; 921 922 sdc1_rclk_off: sdc1-rclk-off-state { 923 pins = "sdc1_rclk"; 924 bias-pull-down; 925 }; 926 927 sdc2_clk_on: sdc2-clk-on-state { 928 pins = "sdc2_clk"; 929 drive-strength = <16>; 930 bias-disable; 931 }; 932 933 sdc2_clk_off: sdc2-clk-off-state { 934 pins = "sdc2_clk"; 935 bias-disable; 936 drive-strength = <2>; 937 }; 938 939 sdc2_cmd_on: sdc2-cmd-on-state { 940 pins = "sdc2_cmd"; 941 bias-pull-up; 942 drive-strength = <10>; 943 }; 944 945 sdc2_cmd_off: sdc2-cmd-off-state { 946 pins = "sdc2_cmd"; 947 bias-pull-up; 948 drive-strength = <2>; 949 }; 950 951 sdc2_data_on: sdc2-data-on-state { 952 pins = "sdc2_data"; 953 bias-pull-up; 954 drive-strength = <10>; 955 }; 956 957 sdc2_data_off: sdc2-data-off-state { 958 pins = "sdc2_data"; 959 bias-pull-up; 960 drive-strength = <2>; 961 }; 962 }; 963 964 gcc: clock-controller@1800000 { 965 compatible = "qcom,gcc-msm8953"; 966 reg = <0x01800000 0x80000>; 967 #clock-cells = <1>; 968 #reset-cells = <1>; 969 #power-domain-cells = <1>; 970 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 971 <&sleep_clk>, 972 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 973 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 974 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, 975 <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>; 976 clock-names = "xo", 977 "sleep", 978 "dsi0pll", 979 "dsi0pllbyte", 980 "dsi1pll", 981 "dsi1pllbyte"; 982 }; 983 984 tcsr_mutex: hwlock@1905000 { 985 compatible = "qcom,tcsr-mutex"; 986 reg = <0x01905000 0x20000>; 987 #hwlock-cells = <1>; 988 }; 989 990 tcsr: syscon@1937000 { 991 compatible = "qcom,tcsr-msm8953", "syscon"; 992 reg = <0x01937000 0x30000>; 993 }; 994 995 tcsr_phy_clk_scheme_sel: syscon@193f044 { 996 compatible = "qcom,tcsr-msm8953", "syscon"; 997 reg = <0x0193f044 0x4>; 998 }; 999 1000 mdss: display-subsystem@1a00000 { 1001 compatible = "qcom,mdss"; 1002 1003 reg = <0x01a00000 0x1000>, 1004 <0x01ab0000 0x1040>; 1005 reg-names = "mdss_phys", 1006 "vbif_phys"; 1007 1008 power-domains = <&gcc MDSS_GDSC>; 1009 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1010 1011 interrupt-controller; 1012 #interrupt-cells = <1>; 1013 1014 interconnects = <&snoc_mm MAS_MDP RPM_ALWAYS_TAG 1015 &bimc SLV_EBI RPM_ALWAYS_TAG>, 1016 <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG 1017 &pcnoc SLV_DISP_SS_CFG RPM_ACTIVE_TAG>; 1018 interconnect-names = "mdp0-mem", 1019 "cpu-cfg"; 1020 1021 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1022 <&gcc GCC_MDSS_AXI_CLK>, 1023 <&gcc GCC_MDSS_VSYNC_CLK>, 1024 <&gcc GCC_MDSS_MDP_CLK>; 1025 clock-names = "iface", 1026 "bus", 1027 "vsync", 1028 "core"; 1029 1030 resets = <&gcc GCC_MDSS_BCR>; 1031 1032 #address-cells = <1>; 1033 #size-cells = <1>; 1034 ranges; 1035 1036 status = "disabled"; 1037 1038 mdp: display-controller@1a01000 { 1039 compatible = "qcom,msm8953-mdp5", "qcom,mdp5"; 1040 reg = <0x01a01000 0x89000>; 1041 reg-names = "mdp_phys"; 1042 1043 interrupt-parent = <&mdss>; 1044 interrupts = <0>; 1045 1046 power-domains = <&gcc MDSS_GDSC>; 1047 1048 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1049 <&gcc GCC_MDSS_AXI_CLK>, 1050 <&gcc GCC_MDSS_MDP_CLK>, 1051 <&gcc GCC_MDSS_VSYNC_CLK>; 1052 clock-names = "iface", 1053 "bus", 1054 "core", 1055 "vsync"; 1056 1057 iommus = <&apps_iommu 0x15>; 1058 1059 ports { 1060 #address-cells = <1>; 1061 #size-cells = <0>; 1062 1063 port@0 { 1064 reg = <0>; 1065 mdp5_intf1_out: endpoint { 1066 remote-endpoint = <&mdss_dsi0_in>; 1067 }; 1068 }; 1069 1070 port@1 { 1071 reg = <1>; 1072 mdp5_intf2_out: endpoint { 1073 remote-endpoint = <&mdss_dsi1_in>; 1074 }; 1075 }; 1076 }; 1077 }; 1078 1079 mdss_dsi0: dsi@1a94000 { 1080 compatible = "qcom,msm8953-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 1081 reg = <0x01a94000 0x400>; 1082 reg-names = "dsi_ctrl"; 1083 1084 interrupt-parent = <&mdss>; 1085 interrupts = <4>; 1086 1087 assigned-clocks = <&gcc BYTE0_CLK_SRC>, 1088 <&gcc PCLK0_CLK_SRC>; 1089 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 1090 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 1091 1092 clocks = <&gcc GCC_MDSS_MDP_CLK>, 1093 <&gcc GCC_MDSS_AHB_CLK>, 1094 <&gcc GCC_MDSS_AXI_CLK>, 1095 <&gcc GCC_MDSS_BYTE0_CLK>, 1096 <&gcc GCC_MDSS_PCLK0_CLK>, 1097 <&gcc GCC_MDSS_ESC0_CLK>; 1098 clock-names = "mdp_core", 1099 "iface", 1100 "bus", 1101 "byte", 1102 "pixel", 1103 "core"; 1104 1105 phys = <&mdss_dsi0_phy>; 1106 1107 #address-cells = <1>; 1108 #size-cells = <0>; 1109 1110 status = "disabled"; 1111 1112 ports { 1113 #address-cells = <1>; 1114 #size-cells = <0>; 1115 1116 port@0 { 1117 reg = <0>; 1118 mdss_dsi0_in: endpoint { 1119 remote-endpoint = <&mdp5_intf1_out>; 1120 }; 1121 }; 1122 1123 port@1 { 1124 reg = <1>; 1125 mdss_dsi0_out: endpoint { 1126 }; 1127 }; 1128 }; 1129 }; 1130 1131 mdss_dsi0_phy: phy@1a94400 { 1132 compatible = "qcom,dsi-phy-14nm-8953"; 1133 reg = <0x01a94400 0x100>, 1134 <0x01a94500 0x300>, 1135 <0x01a94800 0x188>; 1136 reg-names = "dsi_phy", 1137 "dsi_phy_lane", 1138 "dsi_pll"; 1139 1140 #clock-cells = <1>; 1141 #phy-cells = <0>; 1142 1143 clocks = <&gcc GCC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 1144 clock-names = "iface", "ref"; 1145 1146 status = "disabled"; 1147 }; 1148 1149 mdss_dsi1: dsi@1a96000 { 1150 compatible = "qcom,msm8953-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 1151 reg = <0x01a96000 0x400>; 1152 reg-names = "dsi_ctrl"; 1153 1154 interrupt-parent = <&mdss>; 1155 interrupts = <5>; 1156 1157 assigned-clocks = <&gcc BYTE1_CLK_SRC>, 1158 <&gcc PCLK1_CLK_SRC>; 1159 assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 1160 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; 1161 1162 clocks = <&gcc GCC_MDSS_MDP_CLK>, 1163 <&gcc GCC_MDSS_AHB_CLK>, 1164 <&gcc GCC_MDSS_AXI_CLK>, 1165 <&gcc GCC_MDSS_BYTE1_CLK>, 1166 <&gcc GCC_MDSS_PCLK1_CLK>, 1167 <&gcc GCC_MDSS_ESC1_CLK>; 1168 clock-names = "mdp_core", 1169 "iface", 1170 "bus", 1171 "byte", 1172 "pixel", 1173 "core"; 1174 1175 phys = <&mdss_dsi1_phy>; 1176 1177 status = "disabled"; 1178 1179 ports { 1180 #address-cells = <1>; 1181 #size-cells = <0>; 1182 1183 port@0 { 1184 reg = <0>; 1185 mdss_dsi1_in: endpoint { 1186 remote-endpoint = <&mdp5_intf2_out>; 1187 }; 1188 }; 1189 1190 port@1 { 1191 reg = <1>; 1192 mdss_dsi1_out: endpoint { 1193 }; 1194 }; 1195 }; 1196 }; 1197 1198 mdss_dsi1_phy: phy@1a96400 { 1199 compatible = "qcom,dsi-phy-14nm-8953"; 1200 reg = <0x01a96400 0x100>, 1201 <0x01a96500 0x300>, 1202 <0x01a96800 0x188>; 1203 reg-names = "dsi_phy", 1204 "dsi_phy_lane", 1205 "dsi_pll"; 1206 1207 #clock-cells = <1>; 1208 #phy-cells = <0>; 1209 1210 clocks = <&gcc GCC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 1211 clock-names = "iface", "ref"; 1212 1213 status = "disabled"; 1214 }; 1215 }; 1216 1217 cci: cci@1b0c000 { 1218 compatible = "qcom,msm8953-cci"; 1219 reg = <0x1b0c000 0x4000>; 1220 1221 interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>; 1222 1223 clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, 1224 <&gcc GCC_CAMSS_CCI_AHB_CLK>, 1225 <&gcc GCC_CAMSS_CCI_CLK>, 1226 <&gcc GCC_CAMSS_AHB_CLK>; 1227 clock-names = "camss_top_ahb", 1228 "cci_ahb", 1229 "cci", 1230 "camss_ahb"; 1231 1232 assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>, 1233 <&gcc GCC_CAMSS_CCI_CLK>; 1234 assigned-clock-rates = <80000000>, 1235 <19200000>; 1236 1237 pinctrl-0 = <&cci0_default &cci1_default>; 1238 pinctrl-names = "default"; 1239 1240 #address-cells = <1>; 1241 #size-cells = <0>; 1242 1243 status = "disabled"; 1244 1245 cci_i2c0: i2c-bus@0 { 1246 reg = <0>; 1247 clock-frequency = <400000>; 1248 #address-cells = <1>; 1249 #size-cells = <0>; 1250 }; 1251 1252 cci_i2c1: i2c-bus@1 { 1253 reg = <1>; 1254 clock-frequency = <400000>; 1255 #address-cells = <1>; 1256 #size-cells = <0>; 1257 }; 1258 }; 1259 1260 gpu: gpu@1c00000 { 1261 compatible = "qcom,adreno-506.0", "qcom,adreno"; 1262 reg = <0x01c00000 0x40000>; 1263 reg-names = "kgsl_3d0_reg_memory"; 1264 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1265 1266 clocks = <&gcc GCC_OXILI_GFX3D_CLK>, 1267 <&gcc GCC_OXILI_AHB_CLK>, 1268 <&gcc GCC_BIMC_GFX_CLK>, 1269 <&gcc GCC_BIMC_GPU_CLK>, 1270 <&gcc GCC_OXILI_TIMER_CLK>, 1271 <&gcc GCC_OXILI_AON_CLK>; 1272 clock-names = "core", 1273 "iface", 1274 "mem_iface", 1275 "alt_mem_iface", 1276 "rbbmtimer", 1277 "alwayson"; 1278 power-domains = <&gcc OXILI_GX_GDSC>; 1279 1280 interconnects = <&bimc MAS_OXILI RPM_ALWAYS_TAG 1281 &bimc SLV_EBI RPM_ALWAYS_TAG>, 1282 <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG 1283 &pcnoc SLV_GPU_CFG RPM_ACTIVE_TAG>; 1284 1285 iommus = <&gpu_iommu 0>; 1286 operating-points-v2 = <&gpu_opp_table>; 1287 1288 #cooling-cells = <2>; 1289 1290 status = "disabled"; 1291 1292 gpu_zap_shader: zap-shader { 1293 memory-region = <&zap_shader_region>; 1294 }; 1295 1296 gpu_opp_table: opp-table { 1297 compatible = "operating-points-v2"; 1298 1299 opp-19200000 { 1300 opp-hz = /bits/ 64 <19200000>; 1301 opp-supported-hw = <0xff>; 1302 required-opps = <&rpmpd_opp_min_svs>; 1303 }; 1304 1305 opp-133300000 { 1306 opp-hz = /bits/ 64 <133300000>; 1307 opp-supported-hw = <0xff>; 1308 required-opps = <&rpmpd_opp_min_svs>; 1309 }; 1310 1311 opp-216000000 { 1312 opp-hz = /bits/ 64 <216000000>; 1313 opp-supported-hw = <0xff>; 1314 required-opps = <&rpmpd_opp_low_svs>; 1315 }; 1316 1317 opp-320000000 { 1318 opp-hz = /bits/ 64 <320000000>; 1319 opp-supported-hw = <0xff>; 1320 required-opps = <&rpmpd_opp_svs>; 1321 }; 1322 1323 opp-400000000 { 1324 opp-hz = /bits/ 64 <400000000>; 1325 opp-supported-hw = <0xff>; 1326 required-opps = <&rpmpd_opp_svs_plus>; 1327 }; 1328 1329 opp-510000000 { 1330 opp-hz = /bits/ 64 <510000000>; 1331 opp-supported-hw = <0xff>; 1332 required-opps = <&rpmpd_opp_nom>; 1333 }; 1334 1335 opp-560000000 { 1336 opp-hz = /bits/ 64 <560000000>; 1337 opp-supported-hw = <0xff>; 1338 required-opps = <&rpmpd_opp_nom_plus>; 1339 }; 1340 1341 /* 1342 * This opp is only available on msm8953 and 1343 * sdm632, the max for sdm450 is 600MHz. 1344 */ 1345 opp-650000000 { 1346 opp-hz = /bits/ 64 <650000000>; 1347 opp-supported-hw = <0xff>; 1348 required-opps = <&rpmpd_opp_turbo>; 1349 }; 1350 }; 1351 }; 1352 1353 gpu_iommu: iommu@1c48000 { 1354 compatible = "qcom,msm8953-iommu", "qcom,msm-iommu-v2"; 1355 ranges = <0 0x01c48000 0x8000>; 1356 1357 clocks = <&gcc GCC_OXILI_AHB_CLK>, 1358 <&gcc GCC_BIMC_GFX_CLK>; 1359 clock-names = "iface", "bus"; 1360 1361 power-domains = <&gcc OXILI_CX_GDSC>; 1362 1363 qcom,iommu-secure-id = <18>; 1364 1365 #address-cells = <1>; 1366 #iommu-cells = <1>; 1367 #size-cells = <1>; 1368 1369 /* gfx3d_user */ 1370 iommu-ctx@0 { 1371 compatible = "qcom,msm-iommu-v2-ns"; 1372 reg = <0x0000 0x1000>; 1373 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 1374 }; 1375 1376 /* gfx3d_secure */ 1377 iommu-ctx@2000 { 1378 compatible = "qcom,msm-iommu-v2-sec"; 1379 reg = <0x2000 0x1000>; 1380 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 1381 }; 1382 }; 1383 1384 apps_iommu: iommu@1e20000 { 1385 compatible = "qcom,msm8953-iommu", "qcom,msm-iommu-v1"; 1386 ranges = <0 0x01e20000 0x20000>; 1387 1388 clocks = <&gcc GCC_SMMU_CFG_CLK>, 1389 <&gcc GCC_APSS_TCU_ASYNC_CLK>; 1390 clock-names = "iface", "bus"; 1391 1392 qcom,iommu-secure-id = <17>; 1393 1394 #address-cells = <1>; 1395 #iommu-cells = <1>; 1396 #size-cells = <1>; 1397 1398 /* VFE */ 1399 iommu-ctx@14000 { 1400 compatible = "qcom,msm-iommu-v1-ns"; 1401 reg = <0x14000 0x1000>; 1402 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 1403 }; 1404 1405 /* MDP_0 */ 1406 iommu-ctx@15000 { 1407 compatible = "qcom,msm-iommu-v1-ns"; 1408 reg = <0x15000 0x1000>; 1409 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1410 }; 1411 1412 /* VENUS_NS */ 1413 iommu-ctx@16000 { 1414 compatible = "qcom,msm-iommu-v1-ns"; 1415 reg = <0x16000 0x1000>; 1416 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1417 }; 1418 }; 1419 1420 spmi_bus: spmi@200f000 { 1421 compatible = "qcom,spmi-pmic-arb"; 1422 reg = <0x0200f000 0x1000>, 1423 <0x02400000 0x800000>, 1424 <0x02c00000 0x800000>, 1425 <0x03800000 0x200000>, 1426 <0x0200a000 0x2100>; 1427 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1428 interrupt-names = "periph_irq"; 1429 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1430 qcom,ee = <0>; 1431 qcom,channel = <0>; 1432 interrupt-controller; 1433 1434 #interrupt-cells = <4>; 1435 #address-cells = <2>; 1436 #size-cells = <0>; 1437 }; 1438 1439 mpss: remoteproc@4080000 { 1440 compatible = "qcom,msm8953-mss-pil"; 1441 reg = <0x04080000 0x100>, 1442 <0x04020000 0x040>; 1443 reg-names = "qdsp6", "rmb"; 1444 1445 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, 1446 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 1447 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 1448 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 1449 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>; 1450 interrupt-names = "wdog", "fatal", "ready", 1451 "handover", "stop-ack"; 1452 1453 power-domains = <&rpmpd MSM8953_VDDCX>, 1454 <&rpmpd MSM8953_VDDMX>, 1455 <&rpmpd MSM8953_VDDMD>; 1456 power-domain-names = "cx", "mx","mss"; 1457 1458 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1459 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, 1460 <&gcc GCC_BOOT_ROM_AHB_CLK>, 1461 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1462 clock-names = "iface", "bus", "mem", "xo"; 1463 1464 qcom,smem-states = <&smp2p_modem_out 0>; 1465 qcom,smem-state-names = "stop"; 1466 1467 resets = <&gcc GCC_MSS_BCR>; 1468 reset-names = "mss_restart"; 1469 1470 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>; 1471 1472 status = "disabled"; 1473 1474 mba { 1475 memory-region = <&mba_mem>; 1476 }; 1477 1478 mpss { 1479 memory-region = <&mpss_mem>; 1480 }; 1481 1482 smd-edge { 1483 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>; 1484 1485 qcom,smd-edge = <0>; 1486 mboxes = <&apcs 12>; 1487 qcom,remote-pid = <1>; 1488 1489 label = "modem"; 1490 }; 1491 }; 1492 1493 usb3: usb@70f8800 { 1494 compatible = "qcom,msm8953-dwc3", "qcom,dwc3"; 1495 reg = <0x070f8800 0x400>; 1496 #address-cells = <1>; 1497 #size-cells = <1>; 1498 ranges; 1499 1500 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1501 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1502 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 1503 interrupt-names = "pwr_event", 1504 "qusb2_phy", 1505 "ss_phy_irq"; 1506 1507 clocks = <&gcc GCC_USB_PHY_CFG_AHB_CLK>, 1508 <&gcc GCC_USB30_MASTER_CLK>, 1509 <&gcc GCC_PCNOC_USB3_AXI_CLK>, 1510 <&gcc GCC_USB30_SLEEP_CLK>, 1511 <&gcc GCC_USB30_MOCK_UTMI_CLK>; 1512 clock-names = "cfg_noc", 1513 "core", 1514 "iface", 1515 "sleep", 1516 "mock_utmi"; 1517 1518 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 1519 <&gcc GCC_USB30_MASTER_CLK>; 1520 assigned-clock-rates = <19200000>, <133330000>; 1521 1522 interconnects = <&pcnoc MAS_USB3 RPM_ALWAYS_TAG 1523 &bimc SLV_EBI RPM_ALWAYS_TAG>, 1524 <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG 1525 &pcnoc SLV_USB3 RPM_ACTIVE_TAG>; 1526 interconnect-names = "usb-ddr", 1527 "apps-usb"; 1528 1529 power-domains = <&gcc USB30_GDSC>; 1530 1531 qcom,select-utmi-as-pipe-clk; 1532 1533 status = "disabled"; 1534 1535 usb3_dwc3: usb@7000000 { 1536 compatible = "snps,dwc3"; 1537 reg = <0x07000000 0xcc00>; 1538 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1539 phys = <&hsusb_phy>; 1540 phy-names = "usb2-phy"; 1541 1542 snps,usb2-gadget-lpm-disable; 1543 snps,dis-u1-entry-quirk; 1544 snps,dis-u2-entry-quirk; 1545 snps,is-utmi-l1-suspend; 1546 snps,hird-threshold = /bits/ 8 <0x00>; 1547 1548 maximum-speed = "high-speed"; 1549 1550 usb-role-switch; 1551 1552 ports { 1553 #address-cells = <1>; 1554 #size-cells = <0>; 1555 1556 port@0 { 1557 reg = <0>; 1558 1559 usb_dwc3_hs: endpoint { 1560 }; 1561 }; 1562 }; 1563 }; 1564 }; 1565 1566 sdhc_1: mmc@7824900 { 1567 compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4"; 1568 1569 reg = <0x07824900 0x500>, <0x07824000 0x800>; 1570 reg-names = "hc", "core"; 1571 1572 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1573 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 1574 interrupt-names = "hc_irq", "pwr_irq"; 1575 1576 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 1577 <&gcc GCC_SDCC1_APPS_CLK>, 1578 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1579 clock-names = "iface", "core", "xo"; 1580 1581 interconnects = <&pcnoc MAS_SDCC_1 RPM_ALWAYS_TAG 1582 &bimc SLV_EBI RPM_ALWAYS_TAG>, 1583 <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG 1584 &pcnoc SLV_SDCC_1 RPM_ACTIVE_TAG>; 1585 interconnect-names = "sdhc-ddr", 1586 "cpu-sdhc"; 1587 1588 power-domains = <&rpmpd MSM8953_VDDCX>; 1589 operating-points-v2 = <&sdhc1_opp_table>; 1590 1591 pinctrl-names = "default", "sleep"; 1592 pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; 1593 pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; 1594 1595 mmc-hs400-1_8v; 1596 mmc-hs200-1_8v; 1597 mmc-ddr-1_8v; 1598 bus-width = <8>; 1599 non-removable; 1600 1601 status = "disabled"; 1602 1603 sdhc1_opp_table: opp-table-sdhc1 { 1604 compatible = "operating-points-v2"; 1605 1606 opp-25000000 { 1607 opp-hz = /bits/ 64 <25000000>; 1608 opp-peak-kBps = <200000>, <100000>; 1609 opp-avg-kBps = <65360>, <32768>; 1610 required-opps = <&rpmpd_opp_low_svs>; 1611 }; 1612 1613 opp-50000000 { 1614 opp-hz = /bits/ 64 <50000000>; 1615 opp-peak-kBps = <400000>, <200000>; 1616 opp-avg-kBps = <130718>, <65360>; 1617 required-opps = <&rpmpd_opp_svs>; 1618 }; 1619 1620 opp-100000000 { 1621 opp-hz = /bits/ 64 <100000000>; 1622 opp-peak-kBps = <400000>, <400000>; 1623 opp-avg-kBps = <130718>, <65360>; 1624 required-opps = <&rpmpd_opp_svs>; 1625 }; 1626 1627 opp-192000000 { 1628 opp-hz = /bits/ 64 <192000000>; 1629 opp-peak-kBps = <800000>, <600000>; 1630 opp-avg-kBps = <261438>, <130718>; 1631 required-opps = <&rpmpd_opp_nom>; 1632 }; 1633 1634 opp-384000000 { 1635 opp-hz = /bits/ 64 <384000000>; 1636 opp-peak-kBps = <800000>, <800000>; 1637 opp-avg-kBps = <261438>, <300000>; 1638 required-opps = <&rpmpd_opp_nom>; 1639 }; 1640 }; 1641 }; 1642 1643 sdhc_2: mmc@7864900 { 1644 compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4"; 1645 1646 reg = <0x07864900 0x500>, <0x07864000 0x800>; 1647 reg-names = "hc", "core"; 1648 1649 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1650 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 1651 interrupt-names = "hc_irq", "pwr_irq"; 1652 1653 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1654 <&gcc GCC_SDCC2_APPS_CLK>, 1655 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1656 clock-names = "iface", "core", "xo"; 1657 1658 interconnects = <&pcnoc MAS_SDCC_2 RPM_ALWAYS_TAG 1659 &bimc SLV_EBI RPM_ALWAYS_TAG>, 1660 <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG 1661 &pcnoc SLV_SDCC_2 RPM_ACTIVE_TAG>; 1662 interconnect-names = "sdhc-ddr", 1663 "cpu-sdhc"; 1664 1665 power-domains = <&rpmpd MSM8953_VDDCX>; 1666 operating-points-v2 = <&sdhc2_opp_table>; 1667 1668 pinctrl-names = "default", "sleep"; 1669 pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; 1670 pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; 1671 1672 bus-width = <4>; 1673 1674 status = "disabled"; 1675 1676 sdhc2_opp_table: opp-table-sdhc2 { 1677 compatible = "operating-points-v2"; 1678 1679 opp-25000000 { 1680 opp-hz = /bits/ 64 <25000000>; 1681 opp-peak-kBps = <200000>, <100000>; 1682 opp-avg-kBps = <65360>, <32768>; 1683 required-opps = <&rpmpd_opp_low_svs>; 1684 }; 1685 1686 opp-50000000 { 1687 opp-hz = /bits/ 64 <50000000>; 1688 opp-peak-kBps = <400000>, <400000>; 1689 opp-avg-kBps = <130718>, <65360>; 1690 required-opps = <&rpmpd_opp_svs>; 1691 }; 1692 1693 opp-100000000 { 1694 opp-hz = /bits/ 64 <100000000>; 1695 opp-peak-kBps = <800000>, <400000>; 1696 opp-avg-kBps = <130718>, <130718>; 1697 required-opps = <&rpmpd_opp_svs>; 1698 }; 1699 1700 opp-177770000 { 1701 opp-hz = /bits/ 64 <177770000>; 1702 opp-peak-kBps = <600000>, <600000>; 1703 opp-avg-kBps = <261438>, <130718>; 1704 required-opps = <&rpmpd_opp_nom>; 1705 }; 1706 1707 opp-200000000 { 1708 opp-hz = /bits/ 64 <200000000>; 1709 opp-peak-kBps = <800000>, <800000>; 1710 opp-avg-kBps = <261438>, <130718>; 1711 required-opps = <&rpmpd_opp_nom>; 1712 }; 1713 }; 1714 }; 1715 1716 blsp1_dma: dma-controller@7884000 { 1717 compatible = "qcom,bam-v1.7.0"; 1718 reg = <0x07884000 0x1f000>; 1719 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1720 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 1721 clock-names = "bam_clk"; 1722 num-channels = <12>; 1723 #dma-cells = <1>; 1724 qcom,ee = <0>; 1725 qcom,num-ees = <4>; 1726 qcom,controlled-remotely; 1727 }; 1728 1729 uart_0: serial@78af000 { 1730 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1731 reg = <0x078af000 0x200>; 1732 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1733 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 1734 <&gcc GCC_BLSP1_AHB_CLK>; 1735 clock-names = "core", "iface"; 1736 1737 status = "disabled"; 1738 }; 1739 1740 i2c_1: i2c@78b5000 { 1741 compatible = "qcom,i2c-qup-v2.2.1"; 1742 reg = <0x078b5000 0x600>; 1743 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1744 clock-names = "core", "iface"; 1745 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 1746 <&gcc GCC_BLSP1_AHB_CLK>; 1747 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; 1748 dma-names = "tx", "rx"; 1749 1750 pinctrl-names = "default", "sleep"; 1751 pinctrl-0 = <&i2c_1_default>; 1752 pinctrl-1 = <&i2c_1_sleep>; 1753 1754 #address-cells = <1>; 1755 #size-cells = <0>; 1756 1757 status = "disabled"; 1758 }; 1759 1760 i2c_2: i2c@78b6000 { 1761 compatible = "qcom,i2c-qup-v2.2.1"; 1762 reg = <0x078b6000 0x600>; 1763 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1764 clock-names = "core", "iface"; 1765 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 1766 <&gcc GCC_BLSP1_AHB_CLK>; 1767 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; 1768 dma-names = "tx", "rx"; 1769 1770 pinctrl-names = "default", "sleep"; 1771 pinctrl-0 = <&i2c_2_default>; 1772 pinctrl-1 = <&i2c_2_sleep>; 1773 1774 #address-cells = <1>; 1775 #size-cells = <0>; 1776 1777 status = "disabled"; 1778 }; 1779 1780 i2c_3: i2c@78b7000 { 1781 compatible = "qcom,i2c-qup-v2.2.1"; 1782 reg = <0x078b7000 0x600>; 1783 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1784 clock-names = "core", "iface"; 1785 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 1786 <&gcc GCC_BLSP1_AHB_CLK>; 1787 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; 1788 dma-names = "tx", "rx"; 1789 1790 pinctrl-names = "default", "sleep"; 1791 pinctrl-0 = <&i2c_3_default>; 1792 pinctrl-1 = <&i2c_3_sleep>; 1793 1794 #address-cells = <1>; 1795 #size-cells = <0>; 1796 1797 status = "disabled"; 1798 }; 1799 1800 spi_3: spi@78b7000 { 1801 compatible = "qcom,spi-qup-v2.2.1"; 1802 reg = <0x078b7000 0x600>; 1803 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1804 clock-names = "core", "iface"; 1805 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, 1806 <&gcc GCC_BLSP1_AHB_CLK>; 1807 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; 1808 dma-names = "tx", "rx"; 1809 1810 pinctrl-names = "default", "sleep"; 1811 pinctrl-0 = <&spi_3_default>; 1812 pinctrl-1 = <&spi_3_sleep>; 1813 1814 #address-cells = <1>; 1815 #size-cells = <0>; 1816 1817 status = "disabled"; 1818 }; 1819 1820 i2c_4: i2c@78b8000 { 1821 compatible = "qcom,i2c-qup-v2.2.1"; 1822 reg = <0x078b8000 0x600>; 1823 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1824 clock-names = "core", "iface"; 1825 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 1826 <&gcc GCC_BLSP1_AHB_CLK>; 1827 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; 1828 dma-names = "tx", "rx"; 1829 1830 pinctrl-names = "default", "sleep"; 1831 pinctrl-0 = <&i2c_4_default>; 1832 pinctrl-1 = <&i2c_4_sleep>; 1833 1834 #address-cells = <1>; 1835 #size-cells = <0>; 1836 1837 status = "disabled"; 1838 }; 1839 1840 blsp2_dma: dma-controller@7ac4000 { 1841 compatible = "qcom,bam-v1.7.0"; 1842 reg = <0x07ac4000 0x1f000>; 1843 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1844 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 1845 clock-names = "bam_clk"; 1846 num-channels = <12>; 1847 #dma-cells = <1>; 1848 qcom,ee = <0>; 1849 qcom,num-ees = <4>; 1850 qcom,controlled-remotely; 1851 }; 1852 1853 uart_5: serial@7aef000 { 1854 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1855 reg = <0x07aef000 0x200>; 1856 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 1857 clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, 1858 <&gcc GCC_BLSP2_AHB_CLK>; 1859 clock-names = "core", 1860 "iface"; 1861 dmas = <&blsp2_dma 0>, <&blsp2_dma 1>; 1862 dma-names = "tx", "rx"; 1863 1864 pinctrl-0 = <&uart_5_default>; 1865 pinctrl-1 = <&uart_5_sleep>; 1866 pinctrl-names = "default", "sleep"; 1867 1868 status = "disabled"; 1869 }; 1870 1871 i2c_5: i2c@7af5000 { 1872 compatible = "qcom,i2c-qup-v2.2.1"; 1873 reg = <0x07af5000 0x600>; 1874 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1875 clock-names = "core", "iface"; 1876 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 1877 <&gcc GCC_BLSP2_AHB_CLK>; 1878 dmas = <&blsp2_dma 4>, <&blsp2_dma 5>; 1879 dma-names = "tx", "rx"; 1880 1881 pinctrl-names = "default", "sleep"; 1882 pinctrl-0 = <&i2c_5_default>; 1883 pinctrl-1 = <&i2c_5_sleep>; 1884 1885 #address-cells = <1>; 1886 #size-cells = <0>; 1887 1888 status = "disabled"; 1889 }; 1890 1891 spi_5: spi@7af5000 { 1892 compatible = "qcom,spi-qup-v2.2.1"; 1893 reg = <0x07af5000 0x600>; 1894 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1895 clock-names = "core", "iface"; 1896 clocks = <&gcc GCC_BLSP2_QUP1_SPI_APPS_CLK>, 1897 <&gcc GCC_BLSP2_AHB_CLK>; 1898 dmas = <&blsp2_dma 4>, <&blsp2_dma 5>; 1899 dma-names = "tx", "rx"; 1900 1901 pinctrl-names = "default", "sleep"; 1902 pinctrl-0 = <&spi_5_default>; 1903 pinctrl-1 = <&spi_5_sleep>; 1904 1905 #address-cells = <1>; 1906 #size-cells = <0>; 1907 1908 status = "disabled"; 1909 }; 1910 1911 i2c_6: i2c@7af6000 { 1912 compatible = "qcom,i2c-qup-v2.2.1"; 1913 reg = <0x07af6000 0x600>; 1914 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1915 clock-names = "core", "iface"; 1916 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 1917 <&gcc GCC_BLSP2_AHB_CLK>; 1918 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; 1919 dma-names = "tx", "rx"; 1920 1921 pinctrl-names = "default", "sleep"; 1922 pinctrl-0 = <&i2c_6_default>; 1923 pinctrl-1 = <&i2c_6_sleep>; 1924 1925 #address-cells = <1>; 1926 #size-cells = <0>; 1927 1928 status = "disabled"; 1929 }; 1930 1931 spi_6: spi@7af6000 { 1932 compatible = "qcom,spi-qup-v2.2.1"; 1933 reg = <0x07af6000 0x600>; 1934 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1935 clock-names = "core", "iface"; 1936 clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>, 1937 <&gcc GCC_BLSP2_AHB_CLK>; 1938 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; 1939 dma-names = "tx", "rx"; 1940 1941 pinctrl-names = "default", "sleep"; 1942 pinctrl-0 = <&spi_6_default>; 1943 pinctrl-1 = <&spi_6_sleep>; 1944 1945 #address-cells = <1>; 1946 #size-cells = <0>; 1947 1948 status = "disabled"; 1949 }; 1950 1951 i2c_7: i2c@7af7000 { 1952 compatible = "qcom,i2c-qup-v2.2.1"; 1953 reg = <0x07af7000 0x600>; 1954 interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>; 1955 clock-names = "core", "iface"; 1956 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, 1957 <&gcc GCC_BLSP2_AHB_CLK>; 1958 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>; 1959 dma-names = "tx", "rx"; 1960 1961 pinctrl-names = "default", "sleep"; 1962 pinctrl-0 = <&i2c_7_default>; 1963 pinctrl-1 = <&i2c_7_sleep>; 1964 1965 #address-cells = <1>; 1966 #size-cells = <0>; 1967 1968 status = "disabled"; 1969 }; 1970 1971 spi_7: spi@7af7000 { 1972 compatible = "qcom,spi-qup-v2.2.1"; 1973 reg = <0x07af7000 0x600>; 1974 interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>; 1975 clock-names = "core", "iface"; 1976 clocks = <&gcc GCC_BLSP2_QUP3_SPI_APPS_CLK>, 1977 <&gcc GCC_BLSP2_AHB_CLK>; 1978 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>; 1979 dma-names = "tx", "rx"; 1980 1981 pinctrl-names = "default", "sleep"; 1982 pinctrl-0 = <&spi_7_default>; 1983 pinctrl-1 = <&spi_7_sleep>; 1984 1985 #address-cells = <1>; 1986 #size-cells = <0>; 1987 1988 status = "disabled"; 1989 }; 1990 1991 i2c_8: i2c@7af8000 { 1992 compatible = "qcom,i2c-qup-v2.2.1"; 1993 reg = <0x07af8000 0x600>; 1994 interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>; 1995 clock-names = "core", "iface"; 1996 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, 1997 <&gcc GCC_BLSP2_AHB_CLK>; 1998 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; 1999 dma-names = "tx", "rx"; 2000 2001 pinctrl-names = "default", "sleep"; 2002 pinctrl-0 = <&i2c_8_default>; 2003 pinctrl-1 = <&i2c_8_sleep>; 2004 2005 #address-cells = <1>; 2006 #size-cells = <0>; 2007 2008 status = "disabled"; 2009 }; 2010 2011 wcnss: remoteproc@a204000 { 2012 compatible = "qcom,pronto-v3-pil", "qcom,pronto"; 2013 reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>; 2014 reg-names = "ccu", "dxe", "pmu"; 2015 2016 memory-region = <&wcnss_fw_mem>; 2017 2018 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, 2019 <&smp2p_wcnss_in 0 IRQ_TYPE_EDGE_RISING>, 2020 <&smp2p_wcnss_in 1 IRQ_TYPE_EDGE_RISING>, 2021 <&smp2p_wcnss_in 2 IRQ_TYPE_EDGE_RISING>, 2022 <&smp2p_wcnss_in 3 IRQ_TYPE_EDGE_RISING>; 2023 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 2024 2025 power-domains = <&rpmpd MSM8953_VDDCX>, 2026 <&rpmpd MSM8953_VDDMX>; 2027 power-domain-names = "cx", "mx"; 2028 2029 qcom,smem-states = <&smp2p_wcnss_out 0>; 2030 qcom,smem-state-names = "stop"; 2031 2032 pinctrl-names = "default"; 2033 pinctrl-0 = <&wcnss_pin_a>; 2034 2035 status = "disabled"; 2036 2037 wcnss_iris: iris { 2038 /* Separate chip, compatible is board-specific */ 2039 clocks = <&rpmcc RPM_SMD_RF_CLK2>; 2040 clock-names = "xo"; 2041 }; 2042 2043 smd-edge { 2044 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>; 2045 2046 mboxes = <&apcs 17>; 2047 qcom,smd-edge = <6>; 2048 qcom,remote-pid = <4>; 2049 2050 label = "pronto"; 2051 2052 wcnss_ctrl: wcnss { 2053 compatible = "qcom,wcnss"; 2054 qcom,smd-channels = "WCNSS_CTRL"; 2055 2056 qcom,mmio = <&wcnss>; 2057 2058 wcnss_bt: bluetooth { 2059 compatible = "qcom,wcnss-bt"; 2060 }; 2061 2062 wcnss_wifi: wifi { 2063 compatible = "qcom,wcnss-wlan"; 2064 2065 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2066 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 2067 interrupt-names = "tx", "rx"; 2068 2069 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; 2070 qcom,smem-state-names = "tx-enable", 2071 "tx-rings-empty"; 2072 }; 2073 }; 2074 }; 2075 }; 2076 2077 intc: interrupt-controller@b000000 { 2078 compatible = "qcom,msm-qgic2"; 2079 interrupt-controller; 2080 #interrupt-cells = <3>; 2081 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; 2082 }; 2083 2084 apcs: mailbox@b011000 { 2085 compatible = "qcom,msm8953-apcs-kpss-global", "syscon"; 2086 reg = <0x0b011000 0x1000>; 2087 #mbox-cells = <1>; 2088 }; 2089 2090 timer@b120000 { 2091 compatible = "arm,armv7-timer-mem"; 2092 reg = <0x0b120000 0x1000>; 2093 #address-cells = <1>; 2094 #size-cells = <1>; 2095 ranges; 2096 2097 frame@b121000 { 2098 frame-number = <0>; 2099 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2100 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 2101 reg = <0x0b121000 0x1000>, 2102 <0x0b122000 0x1000>; 2103 }; 2104 2105 frame@b123000 { 2106 frame-number = <1>; 2107 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2108 reg = <0x0b123000 0x1000>; 2109 status = "disabled"; 2110 }; 2111 2112 frame@b124000 { 2113 frame-number = <2>; 2114 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2115 reg = <0x0b124000 0x1000>; 2116 status = "disabled"; 2117 }; 2118 2119 frame@b125000 { 2120 frame-number = <3>; 2121 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2122 reg = <0x0b125000 0x1000>; 2123 status = "disabled"; 2124 }; 2125 2126 frame@b126000 { 2127 frame-number = <4>; 2128 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2129 reg = <0x0b126000 0x1000>; 2130 status = "disabled"; 2131 }; 2132 2133 frame@b127000 { 2134 frame-number = <5>; 2135 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2136 reg = <0x0b127000 0x1000>; 2137 status = "disabled"; 2138 }; 2139 2140 frame@b128000 { 2141 frame-number = <6>; 2142 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2143 reg = <0x0b128000 0x1000>; 2144 status = "disabled"; 2145 }; 2146 }; 2147 2148 lpass: remoteproc@c200000 { 2149 compatible = "qcom,msm8953-adsp-pil"; 2150 reg = <0x0c200000 0x100>; 2151 2152 interrupts-extended = <&intc 0 293 IRQ_TYPE_EDGE_RISING>, 2153 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2154 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2155 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2156 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 2157 interrupt-names = "wdog", "fatal", "ready", 2158 "handover", "stop-ack"; 2159 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2160 clock-names = "xo"; 2161 2162 power-domains = <&rpmpd MSM8953_VDDCX>; 2163 power-domain-names = "cx"; 2164 2165 memory-region = <&adsp_fw_mem>; 2166 2167 qcom,smem-states = <&smp2p_adsp_out 0>; 2168 qcom,smem-state-names = "stop"; 2169 2170 status = "disabled"; 2171 2172 smd-edge { 2173 interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>; 2174 2175 label = "lpass"; 2176 mboxes = <&apcs 8>; 2177 qcom,smd-edge = <1>; 2178 qcom,remote-pid = <2>; 2179 2180 apr { 2181 compatible = "qcom,apr-v2"; 2182 qcom,smd-channels = "apr_audio_svc"; 2183 qcom,domain = <APR_DOMAIN_ADSP>; 2184 #address-cells = <1>; 2185 #size-cells = <0>; 2186 2187 q6core: service@3 { 2188 reg = <APR_SVC_ADSP_CORE>; 2189 compatible = "qcom,q6core"; 2190 }; 2191 2192 q6afe: service@4 { 2193 compatible = "qcom,q6afe"; 2194 reg = <APR_SVC_AFE>; 2195 q6afedai: dais { 2196 compatible = "qcom,q6afe-dais"; 2197 #address-cells = <1>; 2198 #size-cells = <0>; 2199 #sound-dai-cells = <1>; 2200 2201 dai@16 { 2202 reg = <PRIMARY_MI2S_RX>; 2203 qcom,sd-lines = <0 1>; 2204 }; 2205 dai@20 { 2206 reg = <TERTIARY_MI2S_TX>; 2207 qcom,sd-lines = <0 1>; 2208 }; 2209 dai@127 { 2210 reg = <QUINARY_MI2S_RX>; 2211 qcom,sd-lines = <0>; 2212 }; 2213 }; 2214 2215 q6afecc: clock-controller { 2216 compatible = "qcom,q6afe-clocks"; 2217 #clock-cells = <2>; 2218 }; 2219 }; 2220 2221 q6asm: service@7 { 2222 compatible = "qcom,q6asm"; 2223 reg = <APR_SVC_ASM>; 2224 q6asmdai: dais { 2225 compatible = "qcom,q6asm-dais"; 2226 #address-cells = <1>; 2227 #size-cells = <0>; 2228 #sound-dai-cells = <1>; 2229 2230 dai@0 { 2231 reg = <MSM_FRONTEND_DAI_MULTIMEDIA1>; 2232 direction = <Q6ASM_DAI_RX>; 2233 }; 2234 dai@1 { 2235 reg = <MSM_FRONTEND_DAI_MULTIMEDIA2>; 2236 direction = <Q6ASM_DAI_TX>; 2237 }; 2238 dai@2 { 2239 reg = <MSM_FRONTEND_DAI_MULTIMEDIA3>; 2240 direction = <Q6ASM_DAI_RX>; 2241 }; 2242 dai@3 { 2243 reg = <MSM_FRONTEND_DAI_MULTIMEDIA4>; 2244 direction = <Q6ASM_DAI_RX>; 2245 is-compress-dai; 2246 }; 2247 }; 2248 }; 2249 2250 q6adm: service@8 { 2251 compatible = "qcom,q6adm"; 2252 reg = <APR_SVC_ADM>; 2253 q6routing: routing { 2254 compatible = "qcom,q6adm-routing"; 2255 #sound-dai-cells = <0>; 2256 }; 2257 }; 2258 }; 2259 }; 2260 }; 2261 }; 2262 2263 thermal-zones { 2264 cpu0-thermal { 2265 polling-delay-passive = <250>; 2266 2267 thermal-sensors = <&tsens0 9>; 2268 2269 trips { 2270 cpu0_alert: trip-point0 { 2271 temperature = <80000>; 2272 hysteresis = <2000>; 2273 type = "passive"; 2274 }; 2275 cpu0_crit: crit { 2276 temperature = <100000>; 2277 hysteresis = <2000>; 2278 type = "critical"; 2279 }; 2280 }; 2281 cooling-maps { 2282 map0 { 2283 trip = <&cpu0_alert>; 2284 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2285 }; 2286 }; 2287 }; 2288 cpu1-thermal { 2289 polling-delay-passive = <250>; 2290 2291 thermal-sensors = <&tsens0 10>; 2292 2293 trips { 2294 cpu1_alert: trip-point0 { 2295 temperature = <80000>; 2296 hysteresis = <2000>; 2297 type = "passive"; 2298 }; 2299 cpu1_crit: crit { 2300 temperature = <100000>; 2301 hysteresis = <2000>; 2302 type = "critical"; 2303 }; 2304 }; 2305 cooling-maps { 2306 map0 { 2307 trip = <&cpu1_alert>; 2308 cooling-device = <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2309 }; 2310 }; 2311 }; 2312 cpu2-thermal { 2313 polling-delay-passive = <250>; 2314 2315 thermal-sensors = <&tsens0 11>; 2316 2317 trips { 2318 cpu2_alert: trip-point0 { 2319 temperature = <80000>; 2320 hysteresis = <2000>; 2321 type = "passive"; 2322 }; 2323 cpu2_crit: crit { 2324 temperature = <100000>; 2325 hysteresis = <2000>; 2326 type = "critical"; 2327 }; 2328 }; 2329 cooling-maps { 2330 map0 { 2331 trip = <&cpu2_alert>; 2332 cooling-device = <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2333 }; 2334 }; 2335 }; 2336 cpu3-thermal { 2337 polling-delay-passive = <250>; 2338 2339 thermal-sensors = <&tsens0 12>; 2340 2341 trips { 2342 cpu3_alert: trip-point0 { 2343 temperature = <80000>; 2344 hysteresis = <2000>; 2345 type = "passive"; 2346 }; 2347 cpu3_crit: crit { 2348 temperature = <100000>; 2349 hysteresis = <2000>; 2350 type = "critical"; 2351 }; 2352 }; 2353 cooling-maps { 2354 map0 { 2355 trip = <&cpu3_alert>; 2356 cooling-device = <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2357 }; 2358 }; 2359 }; 2360 cpu4-thermal { 2361 polling-delay-passive = <250>; 2362 thermal-sensors = <&tsens0 4>; 2363 trips { 2364 cpu4_alert: trip-point0 { 2365 temperature = <80000>; 2366 hysteresis = <2000>; 2367 type = "passive"; 2368 }; 2369 cpu4_crit: crit { 2370 temperature = <100000>; 2371 hysteresis = <2000>; 2372 type = "critical"; 2373 }; 2374 }; 2375 cooling-maps { 2376 map0 { 2377 trip = <&cpu4_alert>; 2378 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2379 }; 2380 }; 2381 }; 2382 cpu5-thermal { 2383 polling-delay-passive = <250>; 2384 thermal-sensors = <&tsens0 5>; 2385 trips { 2386 cpu5_alert: trip-point0 { 2387 temperature = <80000>; 2388 hysteresis = <2000>; 2389 type = "passive"; 2390 }; 2391 cpu5_crit: crit { 2392 temperature = <100000>; 2393 hysteresis = <2000>; 2394 type = "critical"; 2395 }; 2396 }; 2397 cooling-maps { 2398 map0 { 2399 trip = <&cpu5_alert>; 2400 cooling-device = <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2401 }; 2402 }; 2403 }; 2404 cpu6-thermal { 2405 polling-delay-passive = <250>; 2406 thermal-sensors = <&tsens0 6>; 2407 trips { 2408 cpu6_alert: trip-point0 { 2409 temperature = <80000>; 2410 hysteresis = <2000>; 2411 type = "passive"; 2412 }; 2413 cpu6_crit: crit { 2414 temperature = <100000>; 2415 hysteresis = <2000>; 2416 type = "critical"; 2417 }; 2418 }; 2419 cooling-maps { 2420 map0 { 2421 trip = <&cpu6_alert>; 2422 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2423 }; 2424 }; 2425 }; 2426 cpu7-thermal { 2427 polling-delay-passive = <250>; 2428 thermal-sensors = <&tsens0 7>; 2429 trips { 2430 cpu7_alert: trip-point0 { 2431 temperature = <80000>; 2432 hysteresis = <2000>; 2433 type = "passive"; 2434 }; 2435 cpu7_crit: crit { 2436 temperature = <100000>; 2437 hysteresis = <2000>; 2438 type = "critical"; 2439 }; 2440 }; 2441 cooling-maps { 2442 map0 { 2443 trip = <&cpu7_alert>; 2444 cooling-device = <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2445 }; 2446 }; 2447 }; 2448 2449 gpu-thermal { 2450 polling-delay-passive = <250>; 2451 thermal-sensors = <&tsens0 15>; 2452 2453 trips { 2454 gpu_alert: trip-point0 { 2455 temperature = <70000>; 2456 hysteresis = <2000>; 2457 type = "passive"; 2458 }; 2459 2460 gpu_crit: crit { 2461 temperature = <90000>; 2462 hysteresis = <2000>; 2463 type = "critical"; 2464 }; 2465 }; 2466 2467 cooling-maps { 2468 map0 { 2469 trip = <&gpu_alert>; 2470 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2471 }; 2472 }; 2473 }; 2474 }; 2475 2476 timer { 2477 compatible = "arm,armv8-timer"; 2478 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2479 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2480 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2481 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 2482 }; 2483}; 2484