1 /*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Shobhit Kumar <shobhit.kumar@intel.com>
25 * Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
26 */
27
28 #include <linux/kernel.h>
29 #include <linux/string_helpers.h>
30
31 #include <drm/drm_print.h>
32
33 #include "i915_utils.h"
34 #include "intel_de.h"
35 #include "intel_display_types.h"
36 #include "intel_dsi.h"
37 #include "vlv_dsi_pll.h"
38 #include "vlv_dsi_pll_regs.h"
39 #include "vlv_sideband.h"
40
41 static const u16 lfsr_converts[] = {
42 426, 469, 234, 373, 442, 221, 110, 311, 411, /* 62 - 70 */
43 461, 486, 243, 377, 188, 350, 175, 343, 427, 213, /* 71 - 80 */
44 106, 53, 282, 397, 454, 227, 113, 56, 284, 142, /* 81 - 90 */
45 71, 35, 273, 136, 324, 418, 465, 488, 500, 506 /* 91 - 100 */
46 };
47
48 /* Get DSI clock from pixel clock */
dsi_clk_from_pclk(u32 pclk,enum mipi_dsi_pixel_format fmt,int lane_count)49 static u32 dsi_clk_from_pclk(u32 pclk, enum mipi_dsi_pixel_format fmt,
50 int lane_count)
51 {
52 u32 dsi_clk_khz;
53 u32 bpp = mipi_dsi_pixel_format_to_bpp(fmt);
54
55 /* DSI data rate = pixel clock * bits per pixel / lane count
56 pixel clock is converted from KHz to Hz */
57 dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count);
58
59 return dsi_clk_khz;
60 }
61
dsi_calc_mnp(struct intel_display * display,struct intel_crtc_state * config,int target_dsi_clk)62 static int dsi_calc_mnp(struct intel_display *display,
63 struct intel_crtc_state *config,
64 int target_dsi_clk)
65 {
66 unsigned int m_min, m_max, p_min = 2, p_max = 6;
67 unsigned int m, n, p;
68 unsigned int calc_m, calc_p;
69 int delta, ref_clk;
70
71 /* target_dsi_clk is expected in kHz */
72 if (target_dsi_clk < 300000 || target_dsi_clk > 1150000) {
73 drm_err(display->drm, "DSI CLK Out of Range\n");
74 return -ECHRNG;
75 }
76
77 if (display->platform.cherryview) {
78 ref_clk = 100000;
79 n = 4;
80 m_min = 70;
81 m_max = 96;
82 } else {
83 ref_clk = 25000;
84 n = 1;
85 m_min = 62;
86 m_max = 92;
87 }
88
89 calc_p = p_min;
90 calc_m = m_min;
91 delta = abs(target_dsi_clk - (m_min * ref_clk) / (p_min * n));
92
93 for (m = m_min; m <= m_max && delta; m++) {
94 for (p = p_min; p <= p_max && delta; p++) {
95 /*
96 * Find the optimal m and p divisors with minimal delta
97 * +/- the required clock
98 */
99 int calc_dsi_clk = (m * ref_clk) / (p * n);
100 int d = abs(target_dsi_clk - calc_dsi_clk);
101 if (d < delta) {
102 delta = d;
103 calc_m = m;
104 calc_p = p;
105 }
106 }
107 }
108
109 /* register has log2(N1), this works fine for powers of two */
110 config->dsi_pll.ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2);
111 config->dsi_pll.div =
112 (ffs(n) - 1) << DSI_PLL_N1_DIV_SHIFT |
113 (u32)lfsr_converts[calc_m - 62] << DSI_PLL_M1_DIV_SHIFT;
114
115 return 0;
116 }
117
vlv_dsi_pclk(struct intel_encoder * encoder,struct intel_crtc_state * config)118 static int vlv_dsi_pclk(struct intel_encoder *encoder,
119 struct intel_crtc_state *config)
120 {
121 struct intel_display *display = to_intel_display(encoder);
122 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
123 int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
124 u32 dsi_clock;
125 u32 pll_ctl, pll_div;
126 u32 m = 0, p = 0, n;
127 int refclk = display->platform.cherryview ? 100000 : 25000;
128 int i;
129
130 pll_ctl = config->dsi_pll.ctrl;
131 pll_div = config->dsi_pll.div;
132
133 /* mask out other bits and extract the P1 divisor */
134 pll_ctl &= DSI_PLL_P1_POST_DIV_MASK;
135 pll_ctl = pll_ctl >> (DSI_PLL_P1_POST_DIV_SHIFT - 2);
136
137 /* N1 divisor */
138 n = (pll_div & DSI_PLL_N1_DIV_MASK) >> DSI_PLL_N1_DIV_SHIFT;
139 n = 1 << n; /* register has log2(N1) */
140
141 /* mask out the other bits and extract the M1 divisor */
142 pll_div &= DSI_PLL_M1_DIV_MASK;
143 pll_div = pll_div >> DSI_PLL_M1_DIV_SHIFT;
144
145 while (pll_ctl) {
146 pll_ctl = pll_ctl >> 1;
147 p++;
148 }
149 p--;
150
151 if (!p) {
152 drm_err(display->drm, "wrong P1 divisor\n");
153 return 0;
154 }
155
156 for (i = 0; i < ARRAY_SIZE(lfsr_converts); i++) {
157 if (lfsr_converts[i] == pll_div)
158 break;
159 }
160
161 if (i == ARRAY_SIZE(lfsr_converts)) {
162 drm_err(display->drm, "wrong m_seed programmed\n");
163 return 0;
164 }
165
166 m = i + 62;
167
168 dsi_clock = (m * refclk) / (p * n);
169
170 return DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, bpp);
171 }
172
173 /*
174 * XXX: The muxing and gating is hard coded for now. Need to add support for
175 * sharing PLLs with two DSI outputs.
176 */
vlv_dsi_pll_compute(struct intel_encoder * encoder,struct intel_crtc_state * config)177 int vlv_dsi_pll_compute(struct intel_encoder *encoder,
178 struct intel_crtc_state *config)
179 {
180 struct intel_display *display = to_intel_display(encoder);
181 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
182 int pclk, dsi_clk, ret;
183
184 dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
185 intel_dsi->lane_count);
186
187 ret = dsi_calc_mnp(display, config, dsi_clk);
188 if (ret) {
189 drm_dbg_kms(display->drm, "dsi_calc_mnp failed\n");
190 return ret;
191 }
192
193 if (intel_dsi->ports & (1 << PORT_A))
194 config->dsi_pll.ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL;
195
196 if (intel_dsi->ports & (1 << PORT_C))
197 config->dsi_pll.ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL;
198
199 config->dsi_pll.ctrl |= DSI_PLL_VCO_EN;
200
201 drm_dbg_kms(display->drm, "dsi pll div %08x, ctrl %08x\n",
202 config->dsi_pll.div, config->dsi_pll.ctrl);
203
204 pclk = vlv_dsi_pclk(encoder, config);
205 config->port_clock = pclk;
206
207 /* FIXME definitely not right for burst/cmd mode/pixel overlap */
208 config->hw.adjusted_mode.crtc_clock = pclk;
209 if (intel_dsi->dual_link)
210 config->hw.adjusted_mode.crtc_clock *= 2;
211
212 return 0;
213 }
214
vlv_dsi_pll_enable(struct intel_encoder * encoder,const struct intel_crtc_state * config)215 void vlv_dsi_pll_enable(struct intel_encoder *encoder,
216 const struct intel_crtc_state *config)
217 {
218 struct intel_display *display = to_intel_display(encoder);
219
220 drm_dbg_kms(display->drm, "\n");
221
222 vlv_cck_get(display->drm);
223
224 vlv_cck_write(display->drm, CCK_REG_DSI_PLL_CONTROL, 0);
225 vlv_cck_write(display->drm, CCK_REG_DSI_PLL_DIVIDER, config->dsi_pll.div);
226 vlv_cck_write(display->drm, CCK_REG_DSI_PLL_CONTROL,
227 config->dsi_pll.ctrl & ~DSI_PLL_VCO_EN);
228
229 /* wait at least 0.5 us after ungating before enabling VCO,
230 * allow hrtimer subsystem optimization by relaxing timing
231 */
232 usleep_range(10, 50);
233
234 vlv_cck_write(display->drm, CCK_REG_DSI_PLL_CONTROL, config->dsi_pll.ctrl);
235
236 if (wait_for(vlv_cck_read(display->drm, CCK_REG_DSI_PLL_CONTROL) &
237 DSI_PLL_LOCK, 20)) {
238
239 vlv_cck_put(display->drm);
240 drm_err(display->drm, "DSI PLL lock failed\n");
241 return;
242 }
243 vlv_cck_put(display->drm);
244
245 drm_dbg_kms(display->drm, "DSI PLL locked\n");
246 }
247
vlv_dsi_pll_disable(struct intel_encoder * encoder)248 void vlv_dsi_pll_disable(struct intel_encoder *encoder)
249 {
250 struct intel_display *display = to_intel_display(encoder);
251 u32 tmp;
252
253 drm_dbg_kms(display->drm, "\n");
254
255 vlv_cck_get(display->drm);
256
257 tmp = vlv_cck_read(display->drm, CCK_REG_DSI_PLL_CONTROL);
258 tmp &= ~DSI_PLL_VCO_EN;
259 tmp |= DSI_PLL_LDO_GATE;
260 vlv_cck_write(display->drm, CCK_REG_DSI_PLL_CONTROL, tmp);
261
262 vlv_cck_put(display->drm);
263 }
264
bxt_dsi_pll_is_enabled(struct intel_display * display)265 bool bxt_dsi_pll_is_enabled(struct intel_display *display)
266 {
267 bool enabled;
268 u32 val;
269 u32 mask;
270
271 mask = BXT_DSI_PLL_DO_ENABLE | BXT_DSI_PLL_LOCKED;
272 val = intel_de_read(display, BXT_DSI_PLL_ENABLE);
273 enabled = (val & mask) == mask;
274
275 if (!enabled)
276 return false;
277
278 /*
279 * Dividers must be programmed with valid values. As per BSEPC, for
280 * GEMINLAKE only PORT A divider values are checked while for BXT
281 * both divider values are validated. Check this here for
282 * paranoia, since BIOS is known to misconfigure PLLs in this way at
283 * times, and since accessing DSI registers with invalid dividers
284 * causes a system hang.
285 */
286 val = intel_de_read(display, BXT_DSI_PLL_CTL);
287 if (display->platform.geminilake) {
288 if (!(val & BXT_DSIA_16X_MASK)) {
289 drm_dbg_kms(display->drm,
290 "Invalid PLL divider (%08x)\n", val);
291 enabled = false;
292 }
293 } else {
294 if (!(val & BXT_DSIA_16X_MASK) || !(val & BXT_DSIC_16X_MASK)) {
295 drm_dbg_kms(display->drm,
296 "Invalid PLL divider (%08x)\n", val);
297 enabled = false;
298 }
299 }
300
301 return enabled;
302 }
303
bxt_dsi_pll_disable(struct intel_encoder * encoder)304 void bxt_dsi_pll_disable(struct intel_encoder *encoder)
305 {
306 struct intel_display *display = to_intel_display(encoder);
307
308 drm_dbg_kms(display->drm, "\n");
309
310 intel_de_rmw(display, BXT_DSI_PLL_ENABLE, BXT_DSI_PLL_DO_ENABLE, 0);
311
312 /*
313 * PLL lock should deassert within 200us.
314 * Wait up to 1ms before timing out.
315 */
316 if (intel_de_wait_for_clear(display, BXT_DSI_PLL_ENABLE,
317 BXT_DSI_PLL_LOCKED, 1))
318 drm_err(display->drm,
319 "Timeout waiting for PLL lock deassertion\n");
320 }
321
vlv_dsi_get_pclk(struct intel_encoder * encoder,struct intel_crtc_state * config)322 u32 vlv_dsi_get_pclk(struct intel_encoder *encoder,
323 struct intel_crtc_state *config)
324 {
325 struct intel_display *display = to_intel_display(encoder);
326 u32 pll_ctl, pll_div;
327
328 drm_dbg_kms(display->drm, "\n");
329
330 vlv_cck_get(display->drm);
331 pll_ctl = vlv_cck_read(display->drm, CCK_REG_DSI_PLL_CONTROL);
332 pll_div = vlv_cck_read(display->drm, CCK_REG_DSI_PLL_DIVIDER);
333 vlv_cck_put(display->drm);
334
335 config->dsi_pll.ctrl = pll_ctl & ~DSI_PLL_LOCK;
336 config->dsi_pll.div = pll_div;
337
338 return vlv_dsi_pclk(encoder, config);
339 }
340
bxt_dsi_pclk(struct intel_encoder * encoder,const struct intel_crtc_state * config)341 static int bxt_dsi_pclk(struct intel_encoder *encoder,
342 const struct intel_crtc_state *config)
343 {
344 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
345 int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
346 u32 dsi_ratio, dsi_clk;
347
348 dsi_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;
349 dsi_clk = (dsi_ratio * BXT_REF_CLOCK_KHZ) / 2;
350
351 return DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, bpp);
352 }
353
bxt_dsi_get_pclk(struct intel_encoder * encoder,struct intel_crtc_state * config)354 u32 bxt_dsi_get_pclk(struct intel_encoder *encoder,
355 struct intel_crtc_state *config)
356 {
357 struct intel_display *display = to_intel_display(encoder);
358 u32 pclk;
359
360 config->dsi_pll.ctrl = intel_de_read(display, BXT_DSI_PLL_CTL);
361
362 pclk = bxt_dsi_pclk(encoder, config);
363
364 drm_dbg_kms(display->drm, "Calculated pclk=%u\n", pclk);
365 return pclk;
366 }
367
vlv_dsi_reset_clocks(struct intel_encoder * encoder,enum port port)368 void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
369 {
370 struct intel_display *display = to_intel_display(encoder);
371 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
372 u32 temp;
373
374 temp = intel_de_read(display, MIPI_CTRL(display, port));
375 temp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
376 intel_de_write(display, MIPI_CTRL(display, port),
377 temp | intel_dsi->escape_clk_div << ESCAPE_CLOCK_DIVIDER_SHIFT);
378 }
379
glk_dsi_program_esc_clock(struct intel_display * display,const struct intel_crtc_state * config)380 static void glk_dsi_program_esc_clock(struct intel_display *display,
381 const struct intel_crtc_state *config)
382 {
383 u32 dsi_rate = 0;
384 u32 pll_ratio = 0;
385 u32 ddr_clk = 0;
386 u32 div1_value = 0;
387 u32 div2_value = 0;
388 u32 txesc1_div = 0;
389 u32 txesc2_div = 0;
390
391 pll_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;
392
393 dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2;
394
395 ddr_clk = dsi_rate / 2;
396
397 /* Variable divider value */
398 div1_value = DIV_ROUND_CLOSEST(ddr_clk, 20000);
399
400 /* Calculate TXESC1 divider */
401 if (div1_value <= 10)
402 txesc1_div = div1_value;
403 else if ((div1_value > 10) && (div1_value <= 20))
404 txesc1_div = DIV_ROUND_UP(div1_value, 2);
405 else if ((div1_value > 20) && (div1_value <= 30))
406 txesc1_div = DIV_ROUND_UP(div1_value, 4);
407 else if ((div1_value > 30) && (div1_value <= 40))
408 txesc1_div = DIV_ROUND_UP(div1_value, 6);
409 else if ((div1_value > 40) && (div1_value <= 50))
410 txesc1_div = DIV_ROUND_UP(div1_value, 8);
411 else
412 txesc1_div = 10;
413
414 /* Calculate TXESC2 divider */
415 div2_value = DIV_ROUND_UP(div1_value, txesc1_div);
416
417 txesc2_div = min_t(u32, div2_value, 10);
418
419 intel_de_write(display, MIPIO_TXESC_CLK_DIV1,
420 (1 << (txesc1_div - 1)) & GLK_TX_ESC_CLK_DIV1_MASK);
421 intel_de_write(display, MIPIO_TXESC_CLK_DIV2,
422 (1 << (txesc2_div - 1)) & GLK_TX_ESC_CLK_DIV2_MASK);
423 }
424
425 /* Program BXT Mipi clocks and dividers */
bxt_dsi_program_clocks(struct intel_display * display,enum port port,const struct intel_crtc_state * config)426 static void bxt_dsi_program_clocks(struct intel_display *display, enum port port,
427 const struct intel_crtc_state *config)
428 {
429 u32 tmp;
430 u32 dsi_rate = 0;
431 u32 pll_ratio = 0;
432 u32 rx_div;
433 u32 tx_div;
434 u32 rx_div_upper;
435 u32 rx_div_lower;
436 u32 mipi_8by3_divider;
437
438 /* Clear old configurations */
439 tmp = intel_de_read(display, BXT_MIPI_CLOCK_CTL);
440 tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
441 tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port));
442 tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
443 tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
444
445 /* Get the current DSI rate(actual) */
446 pll_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;
447 dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2;
448
449 /*
450 * tx clock should be <= 20MHz and the div value must be
451 * subtracted by 1 as per bspec
452 */
453 tx_div = DIV_ROUND_UP(dsi_rate, 20000) - 1;
454 /*
455 * rx clock should be <= 150MHz and the div value must be
456 * subtracted by 1 as per bspec
457 */
458 rx_div = DIV_ROUND_UP(dsi_rate, 150000) - 1;
459
460 /*
461 * rx divider value needs to be updated in the
462 * two different bit fields in the register hence splitting the
463 * rx divider value accordingly
464 */
465 rx_div_lower = rx_div & RX_DIVIDER_BIT_1_2;
466 rx_div_upper = (rx_div & RX_DIVIDER_BIT_3_4) >> 2;
467
468 mipi_8by3_divider = 0x2;
469
470 tmp |= BXT_MIPI_8X_BY3_DIVIDER(port, mipi_8by3_divider);
471 tmp |= BXT_MIPI_TX_ESCLK_DIVIDER(port, tx_div);
472 tmp |= BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, rx_div_lower);
473 tmp |= BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, rx_div_upper);
474
475 intel_de_write(display, BXT_MIPI_CLOCK_CTL, tmp);
476 }
477
bxt_dsi_pll_compute(struct intel_encoder * encoder,struct intel_crtc_state * config)478 int bxt_dsi_pll_compute(struct intel_encoder *encoder,
479 struct intel_crtc_state *config)
480 {
481 struct intel_display *display = to_intel_display(encoder);
482 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
483 u8 dsi_ratio, dsi_ratio_min, dsi_ratio_max;
484 u32 dsi_clk;
485 int pclk;
486
487 dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
488 intel_dsi->lane_count);
489
490 /*
491 * From clock diagram, to get PLL ratio divider, divide double of DSI
492 * link rate (i.e., 2*8x=16x frequency value) by ref clock. Make sure to
493 * round 'up' the result
494 */
495 dsi_ratio = DIV_ROUND_UP(dsi_clk * 2, BXT_REF_CLOCK_KHZ);
496
497 if (display->platform.broxton) {
498 dsi_ratio_min = BXT_DSI_PLL_RATIO_MIN;
499 dsi_ratio_max = BXT_DSI_PLL_RATIO_MAX;
500 } else {
501 dsi_ratio_min = GLK_DSI_PLL_RATIO_MIN;
502 dsi_ratio_max = GLK_DSI_PLL_RATIO_MAX;
503 }
504
505 if (dsi_ratio < dsi_ratio_min || dsi_ratio > dsi_ratio_max) {
506 drm_err(display->drm,
507 "Can't get a suitable ratio from DSI PLL ratios\n");
508 return -ECHRNG;
509 } else
510 drm_dbg_kms(display->drm, "DSI PLL calculation is Done!!\n");
511
512 /*
513 * Program DSI ratio and Select MIPIC and MIPIA PLL output as 8x
514 * Spec says both have to be programmed, even if one is not getting
515 * used. Configure MIPI_CLOCK_CTL dividers in modeset
516 */
517 config->dsi_pll.ctrl = dsi_ratio | BXT_DSIA_16X_BY2 | BXT_DSIC_16X_BY2;
518
519 /* As per recommendation from hardware team,
520 * Prog PVD ratio =1 if dsi ratio <= 50
521 */
522 if (display->platform.broxton && dsi_ratio <= 50)
523 config->dsi_pll.ctrl |= BXT_DSI_PLL_PVD_RATIO_1;
524
525 pclk = bxt_dsi_pclk(encoder, config);
526 config->port_clock = pclk;
527
528 /* FIXME definitely not right for burst/cmd mode/pixel overlap */
529 config->hw.adjusted_mode.crtc_clock = pclk;
530 if (intel_dsi->dual_link)
531 config->hw.adjusted_mode.crtc_clock *= 2;
532
533 return 0;
534 }
535
bxt_dsi_pll_enable(struct intel_encoder * encoder,const struct intel_crtc_state * config)536 void bxt_dsi_pll_enable(struct intel_encoder *encoder,
537 const struct intel_crtc_state *config)
538 {
539 struct intel_display *display = to_intel_display(encoder);
540 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
541 enum port port;
542
543 drm_dbg_kms(display->drm, "\n");
544
545 /* Configure PLL vales */
546 intel_de_write(display, BXT_DSI_PLL_CTL, config->dsi_pll.ctrl);
547 intel_de_posting_read(display, BXT_DSI_PLL_CTL);
548
549 /* Program TX, RX, Dphy clocks */
550 if (display->platform.broxton) {
551 for_each_dsi_port(port, intel_dsi->ports)
552 bxt_dsi_program_clocks(display, port, config);
553 } else {
554 glk_dsi_program_esc_clock(display, config);
555 }
556
557 /* Enable DSI PLL */
558 intel_de_rmw(display, BXT_DSI_PLL_ENABLE, 0, BXT_DSI_PLL_DO_ENABLE);
559
560 /* Timeout and fail if PLL not locked */
561 if (intel_de_wait_for_set(display, BXT_DSI_PLL_ENABLE,
562 BXT_DSI_PLL_LOCKED, 1)) {
563 drm_err(display->drm,
564 "Timed out waiting for DSI PLL to lock\n");
565 return;
566 }
567
568 drm_dbg_kms(display->drm, "DSI PLL locked\n");
569 }
570
bxt_dsi_reset_clocks(struct intel_encoder * encoder,enum port port)571 void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
572 {
573 struct intel_display *display = to_intel_display(encoder);
574 u32 tmp;
575
576 /* Clear old configurations */
577 if (display->platform.broxton) {
578 tmp = intel_de_read(display, BXT_MIPI_CLOCK_CTL);
579 tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
580 tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port));
581 tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
582 tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
583 intel_de_write(display, BXT_MIPI_CLOCK_CTL, tmp);
584 } else {
585 intel_de_rmw(display, MIPIO_TXESC_CLK_DIV1, GLK_TX_ESC_CLK_DIV1_MASK, 0);
586
587 intel_de_rmw(display, MIPIO_TXESC_CLK_DIV2, GLK_TX_ESC_CLK_DIV2_MASK, 0);
588 }
589 intel_de_write(display, MIPI_EOT_DISABLE(display, port), CLOCKSTOP);
590 }
591
assert_dsi_pll(struct intel_display * display,bool state)592 static void assert_dsi_pll(struct intel_display *display, bool state)
593 {
594 bool cur_state;
595
596 vlv_cck_get(display->drm);
597 cur_state = vlv_cck_read(display->drm, CCK_REG_DSI_PLL_CONTROL) & DSI_PLL_VCO_EN;
598 vlv_cck_put(display->drm);
599
600 INTEL_DISPLAY_STATE_WARN(display, cur_state != state,
601 "DSI PLL state assertion failure (expected %s, current %s)\n",
602 str_on_off(state), str_on_off(cur_state));
603 }
604
assert_dsi_pll_enabled(struct intel_display * display)605 void assert_dsi_pll_enabled(struct intel_display *display)
606 {
607 assert_dsi_pll(display, true);
608 }
609
assert_dsi_pll_disabled(struct intel_display * display)610 void assert_dsi_pll_disabled(struct intel_display *display)
611 {
612 assert_dsi_pll(display, false);
613 }
614