1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #ifndef _XE_GUC_ENGINE_TYPES_H_ 7 #define _XE_GUC_ENGINE_TYPES_H_ 8 9 #include <linux/spinlock.h> 10 #include <linux/workqueue.h> 11 12 #include "xe_gpu_scheduler_types.h" 13 14 struct dma_fence; 15 struct xe_exec_queue; 16 17 /** 18 * struct xe_guc_exec_queue - GuC specific state for an xe_exec_queue 19 */ 20 struct xe_guc_exec_queue { 21 /** @q: Backpointer to parent xe_exec_queue */ 22 struct xe_exec_queue *q; 23 /** @rcu: For safe freeing of exported dma fences */ 24 struct rcu_head rcu; 25 /** @sched: GPU scheduler for this xe_exec_queue */ 26 struct xe_gpu_scheduler sched; 27 /** @entity: Scheduler entity for this xe_exec_queue */ 28 struct xe_sched_entity entity; 29 /** 30 * @static_msgs: Static messages for this xe_exec_queue, used when 31 * a message needs to sent through the GPU scheduler but memory 32 * allocations are not allowed. 33 */ 34 #define MAX_STATIC_MSG_TYPE 3 35 struct xe_sched_msg static_msgs[MAX_STATIC_MSG_TYPE]; 36 /** @lr_tdr: long running TDR worker */ 37 struct work_struct lr_tdr; 38 /** @fini_async: do final fini async from this worker */ 39 struct work_struct fini_async; 40 /** @resume_time: time of last resume */ 41 u64 resume_time; 42 /** @state: GuC specific state for this xe_exec_queue */ 43 atomic_t state; 44 /** @wqi_head: work queue item tail */ 45 u32 wqi_head; 46 /** @wqi_tail: work queue item tail */ 47 u32 wqi_tail; 48 /** @id: GuC id for this exec_queue */ 49 u16 id; 50 /** @suspend_wait: wait queue used to wait on pending suspends */ 51 wait_queue_head_t suspend_wait; 52 /** @suspend_pending: a suspend of the exec_queue is pending */ 53 bool suspend_pending; 54 }; 55 56 #endif 57