1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2013-2021 Intel Corporation
4 */
5
6 #include "i915_drv.h"
7 #include "i915_reg.h"
8 #include "intel_pcode.h"
9
gen6_check_mailbox_status(u32 mbox)10 static int gen6_check_mailbox_status(u32 mbox)
11 {
12 switch (mbox & GEN6_PCODE_ERROR_MASK) {
13 case GEN6_PCODE_SUCCESS:
14 return 0;
15 case GEN6_PCODE_UNIMPLEMENTED_CMD:
16 return -ENODEV;
17 case GEN6_PCODE_ILLEGAL_CMD:
18 return -ENXIO;
19 case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
20 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
21 return -EOVERFLOW;
22 case GEN6_PCODE_TIMEOUT:
23 return -ETIMEDOUT;
24 default:
25 MISSING_CASE(mbox & GEN6_PCODE_ERROR_MASK);
26 return 0;
27 }
28 }
29
gen7_check_mailbox_status(u32 mbox)30 static int gen7_check_mailbox_status(u32 mbox)
31 {
32 switch (mbox & GEN6_PCODE_ERROR_MASK) {
33 case GEN6_PCODE_SUCCESS:
34 return 0;
35 case GEN6_PCODE_ILLEGAL_CMD:
36 return -ENXIO;
37 case GEN7_PCODE_TIMEOUT:
38 return -ETIMEDOUT;
39 case GEN7_PCODE_ILLEGAL_DATA:
40 return -EINVAL;
41 case GEN11_PCODE_ILLEGAL_SUBCOMMAND:
42 return -ENXIO;
43 case GEN11_PCODE_LOCKED:
44 return -EBUSY;
45 case GEN11_PCODE_REJECTED:
46 return -EACCES;
47 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
48 return -EOVERFLOW;
49 default:
50 MISSING_CASE(mbox & GEN6_PCODE_ERROR_MASK);
51 return 0;
52 }
53 }
54
__snb_pcode_rw(struct intel_uncore * uncore,u32 mbox,u32 * val,u32 * val1,int fast_timeout_us,int slow_timeout_ms,bool is_read)55 static int __snb_pcode_rw(struct intel_uncore *uncore, u32 mbox,
56 u32 *val, u32 *val1,
57 int fast_timeout_us, int slow_timeout_ms,
58 bool is_read)
59 {
60 lockdep_assert_held(&uncore->i915->sb_lock);
61
62 /*
63 * GEN6_PCODE_* are outside of the forcewake domain, we can use
64 * intel_uncore_read/write_fw variants to reduce the amount of work
65 * required when reading/writing.
66 */
67
68 if (intel_uncore_read_fw(uncore, GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY)
69 return -EAGAIN;
70
71 intel_uncore_write_fw(uncore, GEN6_PCODE_DATA, *val);
72 intel_uncore_write_fw(uncore, GEN6_PCODE_DATA1, val1 ? *val1 : 0);
73 intel_uncore_write_fw(uncore,
74 GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
75
76 if (__intel_wait_for_register_fw(uncore,
77 GEN6_PCODE_MAILBOX,
78 GEN6_PCODE_READY, 0,
79 fast_timeout_us,
80 slow_timeout_ms,
81 &mbox))
82 return -ETIMEDOUT;
83
84 if (is_read)
85 *val = intel_uncore_read_fw(uncore, GEN6_PCODE_DATA);
86 if (is_read && val1)
87 *val1 = intel_uncore_read_fw(uncore, GEN6_PCODE_DATA1);
88
89 if (GRAPHICS_VER(uncore->i915) > 6)
90 return gen7_check_mailbox_status(mbox);
91 else
92 return gen6_check_mailbox_status(mbox);
93 }
94
snb_pcode_read(struct intel_uncore * uncore,u32 mbox,u32 * val,u32 * val1)95 int snb_pcode_read(struct intel_uncore *uncore, u32 mbox, u32 *val, u32 *val1)
96 {
97 int err;
98
99 mutex_lock(&uncore->i915->sb_lock);
100 err = __snb_pcode_rw(uncore, mbox, val, val1, 500, 20, true);
101 mutex_unlock(&uncore->i915->sb_lock);
102
103 if (err) {
104 drm_dbg(&uncore->i915->drm,
105 "warning: pcode (read from mbox %x) mailbox access failed for %ps: %d\n",
106 mbox, __builtin_return_address(0), err);
107 }
108
109 return err;
110 }
111
snb_pcode_write_timeout(struct intel_uncore * uncore,u32 mbox,u32 val,int timeout_ms)112 int snb_pcode_write_timeout(struct intel_uncore *uncore, u32 mbox, u32 val,
113 int timeout_ms)
114 {
115 int err;
116
117 mutex_lock(&uncore->i915->sb_lock);
118 err = __snb_pcode_rw(uncore, mbox, &val, NULL, 250, timeout_ms, false);
119 mutex_unlock(&uncore->i915->sb_lock);
120
121 if (err) {
122 drm_dbg(&uncore->i915->drm,
123 "warning: pcode (write of 0x%08x to mbox %x) mailbox access failed for %ps: %d\n",
124 val, mbox, __builtin_return_address(0), err);
125 }
126
127 return err;
128 }
129
skl_pcode_try_request(struct intel_uncore * uncore,u32 mbox,u32 request,u32 reply_mask,u32 reply,u32 * status)130 static bool skl_pcode_try_request(struct intel_uncore *uncore, u32 mbox,
131 u32 request, u32 reply_mask, u32 reply,
132 u32 *status)
133 {
134 *status = __snb_pcode_rw(uncore, mbox, &request, NULL, 500, 0, true);
135
136 return (*status == 0) && ((request & reply_mask) == reply);
137 }
138
139 /**
140 * skl_pcode_request - send PCODE request until acknowledgment
141 * @uncore: uncore
142 * @mbox: PCODE mailbox ID the request is targeted for
143 * @request: request ID
144 * @reply_mask: mask used to check for request acknowledgment
145 * @reply: value used to check for request acknowledgment
146 * @timeout_base_ms: timeout for polling with preemption enabled
147 *
148 * Keep resending the @request to @mbox until PCODE acknowledges it, PCODE
149 * reports an error or an overall timeout of @timeout_base_ms+50 ms expires.
150 * The request is acknowledged once the PCODE reply dword equals @reply after
151 * applying @reply_mask. Polling is first attempted with preemption enabled
152 * for @timeout_base_ms and if this times out for another 50 ms with
153 * preemption disabled.
154 *
155 * Returns 0 on success, %-ETIMEDOUT in case of a timeout, <0 in case of some
156 * other error as reported by PCODE.
157 */
skl_pcode_request(struct intel_uncore * uncore,u32 mbox,u32 request,u32 reply_mask,u32 reply,int timeout_base_ms)158 int skl_pcode_request(struct intel_uncore *uncore, u32 mbox, u32 request,
159 u32 reply_mask, u32 reply, int timeout_base_ms)
160 {
161 u32 status;
162 int ret;
163
164 mutex_lock(&uncore->i915->sb_lock);
165
166 #define COND \
167 skl_pcode_try_request(uncore, mbox, request, reply_mask, reply, &status)
168
169 /*
170 * Prime the PCODE by doing a request first. Normally it guarantees
171 * that a subsequent request, at most @timeout_base_ms later, succeeds.
172 * _wait_for() doesn't guarantee when its passed condition is evaluated
173 * first, so send the first request explicitly.
174 */
175 if (COND) {
176 ret = 0;
177 goto out;
178 }
179 ret = _wait_for(COND, timeout_base_ms * 1000, 10, 10);
180 if (!ret)
181 goto out;
182
183 /*
184 * The above can time out if the number of requests was low (2 in the
185 * worst case) _and_ PCODE was busy for some reason even after a
186 * (queued) request and @timeout_base_ms delay. As a workaround retry
187 * the poll with preemption disabled to maximize the number of
188 * requests. Increase the timeout from @timeout_base_ms to 50ms to
189 * account for interrupts that could reduce the number of these
190 * requests, and for any quirks of the PCODE firmware that delays
191 * the request completion.
192 */
193 drm_dbg_kms(&uncore->i915->drm,
194 "PCODE timeout, retrying with preemption disabled\n");
195 drm_WARN_ON_ONCE(&uncore->i915->drm, timeout_base_ms > 3);
196 preempt_disable();
197 ret = wait_for_atomic(COND, 50);
198 preempt_enable();
199
200 out:
201 mutex_unlock(&uncore->i915->sb_lock);
202 return status ? status : ret;
203 #undef COND
204 }
205
pcode_init_wait(struct intel_uncore * uncore,int timeout_ms)206 static int pcode_init_wait(struct intel_uncore *uncore, int timeout_ms)
207 {
208 if (__intel_wait_for_register_fw(uncore,
209 GEN6_PCODE_MAILBOX,
210 GEN6_PCODE_READY, 0,
211 500, timeout_ms,
212 NULL))
213 return -EPROBE_DEFER;
214
215 return skl_pcode_request(uncore,
216 DG1_PCODE_STATUS,
217 DG1_UNCORE_GET_INIT_STATUS,
218 DG1_UNCORE_INIT_STATUS_COMPLETE,
219 DG1_UNCORE_INIT_STATUS_COMPLETE, timeout_ms);
220 }
221
intel_pcode_init(struct intel_uncore * uncore)222 int intel_pcode_init(struct intel_uncore *uncore)
223 {
224 int err;
225
226 if (!IS_DGFX(uncore->i915))
227 return 0;
228
229 /*
230 * Wait 10 seconds so that the punit to settle and complete
231 * any outstanding transactions upon module load
232 */
233 err = pcode_init_wait(uncore, 10000);
234
235 if (err) {
236 drm_notice(&uncore->i915->drm,
237 "Waiting for HW initialisation...\n");
238 err = pcode_init_wait(uncore, 180000);
239 }
240
241 return err;
242 }
243
snb_pcode_read_p(struct intel_uncore * uncore,u32 mbcmd,u32 p1,u32 p2,u32 * val)244 int snb_pcode_read_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u32 *val)
245 {
246 intel_wakeref_t wakeref;
247 u32 mbox;
248 int err;
249
250 mbox = REG_FIELD_PREP(GEN6_PCODE_MB_COMMAND, mbcmd)
251 | REG_FIELD_PREP(GEN6_PCODE_MB_PARAM1, p1)
252 | REG_FIELD_PREP(GEN6_PCODE_MB_PARAM2, p2);
253
254 with_intel_runtime_pm(uncore->rpm, wakeref)
255 err = snb_pcode_read(uncore, mbox, val, NULL);
256
257 return err;
258 }
259
snb_pcode_write_p(struct intel_uncore * uncore,u32 mbcmd,u32 p1,u32 p2,u32 val)260 int snb_pcode_write_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u32 val)
261 {
262 intel_wakeref_t wakeref;
263 u32 mbox;
264 int err;
265
266 mbox = REG_FIELD_PREP(GEN6_PCODE_MB_COMMAND, mbcmd)
267 | REG_FIELD_PREP(GEN6_PCODE_MB_PARAM1, p1)
268 | REG_FIELD_PREP(GEN6_PCODE_MB_PARAM2, p2);
269
270 with_intel_runtime_pm(uncore->rpm, wakeref)
271 err = snb_pcode_write(uncore, mbox, val);
272
273 return err;
274 }
275
276 /* Helpers with drm device */
intel_pcode_read(struct drm_device * drm,u32 mbox,u32 * val,u32 * val1)277 int intel_pcode_read(struct drm_device *drm, u32 mbox, u32 *val, u32 *val1)
278 {
279 struct drm_i915_private *i915 = to_i915(drm);
280
281 return snb_pcode_read(&i915->uncore, mbox, val, val1);
282 }
283
intel_pcode_write_timeout(struct drm_device * drm,u32 mbox,u32 val,int timeout_ms)284 int intel_pcode_write_timeout(struct drm_device *drm, u32 mbox, u32 val, int timeout_ms)
285 {
286 struct drm_i915_private *i915 = to_i915(drm);
287
288 return snb_pcode_write_timeout(&i915->uncore, mbox, val, timeout_ms);
289 }
290
intel_pcode_request(struct drm_device * drm,u32 mbox,u32 request,u32 reply_mask,u32 reply,int timeout_base_ms)291 int intel_pcode_request(struct drm_device *drm, u32 mbox, u32 request,
292 u32 reply_mask, u32 reply, int timeout_base_ms)
293 {
294 struct drm_i915_private *i915 = to_i915(drm);
295
296 return skl_pcode_request(&i915->uncore, mbox, request, reply_mask, reply,
297 timeout_base_ms);
298 }
299